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mmc: sdhci: Check and call config_dll callback functions
[thirdparty/u-boot.git] / drivers / mmc / sdhci.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
af62a557
LW		 2/*
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
5 *
af62a557
LW		 6 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
8 */
9
10#include <common.h>
1eb69ae4 11#include <cpu_func.h>
3d296365 12#include <dm.h>
2a809093 13#include <errno.h>
f7ae49fc 14#include <log.h>
af62a557
LW		 15#include <malloc.h>
16#include <mmc.h>
17#include <sdhci.h>
90526e9f 18#include <asm/cache.h>
cd93d625 19#include <linux/bitops.h>
c05ed00a 20#include <linux/delay.h>
58d8ace1 21#include <linux/dma-mapping.h>
fac8bfd4 22#include <phys2bus.h>
43392b55 23#include <power/regulator.h>
af62a557 24
af62a557
LW		 25static void sdhci_reset(struct sdhci_host *host, u8 mask)
26{
27 unsigned long timeout;
28
29 /* Wait max 100 ms */
30 timeout = 100;
31 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
32 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
33 if (timeout == 0) {
30e6d979
DR		 34 printf("%s: Reset 0x%x never completed.\n",
35 __func__, (int)mask);
af62a557
LW		 36 return;
37 }
38 timeout--;
39 udelay(1000);
40 }
41}
42
43static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
44{
45 int i;
46 if (cmd->resp_type & MMC_RSP_136) {
47 /* CRC is stripped so we need to do some shifting. */
48 for (i = 0; i < 4; i++) {
49 cmd->response[i] = sdhci_readl(host,
50 SDHCI_RESPONSE + (3-i)*4) << 8;
51 if (i != 3)
52 cmd->response[i] |= sdhci_readb(host,
53 SDHCI_RESPONSE + (3-i)*4-1);
54 }
55 } else {
56 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
57 }
58}
59
60static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
61{
62 int i;
63 char *offs;
64 for (i = 0; i < data->blocksize; i += 4) {
65 offs = data->dest + i;
66 if (data->flags == MMC_DATA_READ)
67 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
68 else
69 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
70 }
71}
37cb626d 72
37cb626d 73#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
6d6af205
FA		 74static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
75 int *is_aligned, int trans_bytes)
76{
c89c96d3 77 dma_addr_t dma_addr;
804c7f42 78 unsigned char ctrl;
58d8ace1 79 void *buf;
6d6af205
FA		 80
81 if (data->flags == MMC_DATA_READ)
58d8ace1 82 buf = data->dest;
6d6af205 83 else
58d8ace1 84 buf = (void *)data->src;
6d6af205 85
2c011847 86 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
804c7f42 87 ctrl &= ~SDHCI_CTRL_DMA_MASK;
37cb626d
FA		 88 if (host->flags & USE_ADMA64)
89 ctrl |= SDHCI_CTRL_ADMA64;
90 else if (host->flags & USE_ADMA)
91 ctrl |= SDHCI_CTRL_ADMA32;
2c011847 92 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
6d6af205 93
58d8ace1
MY		 94 if (host->flags & USE_SDMA &&
95 (host->force_align_buffer ||
96 (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
97 ((unsigned long)buf & 0x7) != 0x0))) {
98 *is_aligned = 0;
99 if (data->flags != MMC_DATA_READ)
100 memcpy(host->align_buffer, buf, trans_bytes);
101 buf = host->align_buffer;
102 }
103
104 host->start_addr = dma_map_single(buf, trans_bytes,
105 mmc_get_dma_dir(data));
106
37cb626d 107 if (host->flags & USE_SDMA) {
c89c96d3
NSJ		 108 dma_addr = dev_phys_to_bus(mmc_to_dev(host->mmc), host->start_addr);
109 sdhci_writel(host, dma_addr, SDHCI_DMA_ADDRESS);
4d6a773b
MW		 110 }
111#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
112 else if (host->flags & (USE_ADMA | USE_ADMA64)) {
113 sdhci_prepare_adma_table(host->adma_desc_table, data,
114 host->start_addr);
37cb626d 115
a2b0221c
MY		 116 sdhci_writel(host, lower_32_bits(host->adma_addr),
117 SDHCI_ADMA_ADDRESS);
37cb626d 118 if (host->flags & USE_ADMA64)
a2b0221c 119 sdhci_writel(host, upper_32_bits(host->adma_addr),
37cb626d
FA		 120 SDHCI_ADMA_ADDRESS_HI);
121 }
4d6a773b 122#endif
6d6af205
FA		 123}
124#else
125static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
126 int *is_aligned, int trans_bytes)
127{}
804c7f42 128#endif
6d6af205
FA		 129static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
130{
131 dma_addr_t start_addr = host->start_addr;
132 unsigned int stat, rdy, mask, timeout, block = 0;
133 bool transfer_done = false;
af62a557 134
5d48e422 135 timeout = 1000000;
af62a557
LW		 136 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
137 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
138 do {
139 stat = sdhci_readl(host, SDHCI_INT_STATUS);
140 if (stat & SDHCI_INT_ERROR) {
61f2e5ee
MY		 141 pr_debug("%s: Error detected in status(0x%X)!\n",
142 __func__, stat);
2cb5d67c 143 return -EIO;
af62a557 144 }
7dde50d7 145 if (!transfer_done && (stat & rdy)) {
af62a557
LW		 146 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
147 continue;
148 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
149 sdhci_transfer_pio(host, data);
150 data->dest += data->blocksize;
7dde50d7
AD		 151 if (++block >= data->blocks) {
152 /* Keep looping until the SDHCI_INT_DATA_END is
153 * cleared, even if we finished sending all the
154 * blocks.
155 */
156 transfer_done = true;
157 continue;
158 }
af62a557 159 }
37cb626d 160 if ((host->flags & USE_DMA) && !transfer_done &&
6d6af205 161 (stat & SDHCI_INT_DMA_END)) {
af62a557 162 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
37cb626d
FA		 163 if (host->flags & USE_SDMA) {
164 start_addr &=
165 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
166 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
c89c96d3
NSJ		 167 start_addr = dev_phys_to_bus(mmc_to_dev(host->mmc),
168 start_addr);
169 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
37cb626d 170 }
af62a557 171 }
a004abde
LW		 172 if (timeout-- > 0)
173 udelay(10);
174 else {
30e6d979 175 printf("%s: Transfer data timeout\n", __func__);
2cb5d67c 176 return -ETIMEDOUT;
a004abde 177 }
af62a557 178 } while (!(stat & SDHCI_INT_DATA_END));
4155ad9a 179
37e1362e 180#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
4155ad9a
MY		 181 dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
182 mmc_get_dma_dir(data));
37e1362e 183#endif
4155ad9a 184
af62a557
LW		 185 return 0;
186}
187
56b34bc6
PM		 188/*
189 * No command will be sent by driver if card is busy, so driver must wait
190 * for card ready state.
191 * Every time when card is busy after timeout then (last) timeout value will be
192 * increased twice but only if it doesn't exceed global defined maximum.
65a25b20 193 * Each function call will use last timeout value.
56b34bc6 194 */
65a25b20 195#define SDHCI_CMD_MAX_TIMEOUT 3200
d8ce77b2 196#define SDHCI_CMD_DEFAULT_TIMEOUT 100
d90bb439 197#define SDHCI_READ_STATUS_TIMEOUT 1000
56b34bc6 198
e7881d85 199#ifdef CONFIG_DM_MMC
ef1e4eda
SG		 200static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
201 struct mmc_data *data)
202{
203 struct mmc *mmc = mmc_get_mmc_dev(dev);
204
205#else
6588c78b 206static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
ef1e4eda 207 struct mmc_data *data)
af62a557 208{
ef1e4eda 209#endif
93bfd616 210 struct sdhci_host *host = mmc->priv;
af62a557
LW		 211 unsigned int stat = 0;
212 int ret = 0;
213 int trans_bytes = 0, is_aligned = 1;
2b0dd417 214 u32 mask, flags, mode = 0;
6d6af205 215 unsigned int time = 0;
19d2e342 216 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
36332b6e 217 ulong start = get_timer(0);
af62a557 218
6d6af205 219 host->start_addr = 0;
56b34bc6 220 /* Timeout unit - ms */
d8ce77b2 221 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
af62a557 222
af62a557
LW		 223 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
224
225 /* We shouldn't wait for data inihibit for stop commands, even
226 though they might use busy signaling */
b88a7a4c 227 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
1a7414f6
SDPP		 228 ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
229 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
af62a557
LW		 230 mask &= ~SDHCI_DATA_INHIBIT;
231
232 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
56b34bc6 233 if (time >= cmd_timeout) {
30e6d979 234 printf("%s: MMC: %d busy ", __func__, mmc_dev);
65a25b20 235 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
56b34bc6
PM		 236 cmd_timeout += cmd_timeout;
237 printf("timeout increasing to: %u ms.\n",
238 cmd_timeout);
239 } else {
240 puts("timeout.\n");
915ffa52 241 return -ECOMM;
56b34bc6 242 }
af62a557 243 }
56b34bc6 244 time++;
af62a557
LW		 245 udelay(1000);
246 }
247
713e6815
JRO		 248 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
249
af62a557 250 mask = SDHCI_INT_RESPONSE;
1a7414f6
SDPP		 251 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
252 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
b88a7a4c
SDPP		 253 mask = SDHCI_INT_DATA_AVAIL;
254
af62a557
LW		 255 if (!(cmd->resp_type & MMC_RSP_PRESENT))
256 flags = SDHCI_CMD_RESP_NONE;
257 else if (cmd->resp_type & MMC_RSP_136)
258 flags = SDHCI_CMD_RESP_LONG;
259 else if (cmd->resp_type & MMC_RSP_BUSY) {
260 flags = SDHCI_CMD_RESP_SHORT_BUSY;
4a3ea75d 261 mask |= SDHCI_INT_DATA_END;
af62a557
LW		 262 } else
263 flags = SDHCI_CMD_RESP_SHORT;
264
265 if (cmd->resp_type & MMC_RSP_CRC)
266 flags |= SDHCI_CMD_CRC;
267 if (cmd->resp_type & MMC_RSP_OPCODE)
268 flags |= SDHCI_CMD_INDEX;
434f9d45
SDPP		 269 if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
270 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
af62a557
LW		 271 flags |= SDHCI_CMD_DATA;
272
30e6d979 273 /* Set Transfer mode regarding to data flag */
bb7b4ef3 274 if (data) {
af62a557 275 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
2b0dd417
KH		 276
277 if (!(host->quirks & SDHCI_QUIRK_SUPPORT_SINGLE))
278 mode = SDHCI_TRNS_BLK_CNT_EN;
af62a557
LW		 279 trans_bytes = data->blocks * data->blocksize;
280 if (data->blocks > 1)
2b0dd417 281 mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN;
af62a557
LW		 282
283 if (data->flags == MMC_DATA_READ)
284 mode |= SDHCI_TRNS_READ;
285
37cb626d 286 if (host->flags & USE_DMA) {
6d6af205
FA		 287 mode |= SDHCI_TRNS_DMA;
288 sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
af62a557
LW		 289 }
290
af62a557
LW		 291 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
292 data->blocksize),
293 SDHCI_BLOCK_SIZE);
294 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
295 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
5e1c23cd
KL		 296 } else if (cmd->resp_type & MMC_RSP_BUSY) {
297 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
af62a557
LW		 298 }
299
300 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
af62a557 301 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
29905a45 302 start = get_timer(0);
af62a557
LW		 303 do {
304 stat = sdhci_readl(host, SDHCI_INT_STATUS);
305 if (stat & SDHCI_INT_ERROR)
306 break;
af62a557 307
bae4a1fd
MY		 308 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
309 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
310 return 0;
311 } else {
312 printf("%s: Timeout for status update!\n",
313 __func__);
915ffa52 314 return -ETIMEDOUT;
bae4a1fd 315 }
3a638320 316 }
bae4a1fd 317 } while ((stat & mask) != mask);
3a638320 318
af62a557
LW		 319 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
320 sdhci_cmd_done(host, cmd);
321 sdhci_writel(host, mask, SDHCI_INT_STATUS);
322 } else
323 ret = -1;
324
325 if (!ret && data)
6d6af205 326 ret = sdhci_transfer_data(host, data);
af62a557 327
13243f2e
TB		 328 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
329 udelay(1000);
330
af62a557
LW		 331 stat = sdhci_readl(host, SDHCI_INT_STATUS);
332 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
333 if (!ret) {
334 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
335 !is_aligned && (data->flags == MMC_DATA_READ))
c8cc18b7 336 memcpy(data->dest, host->align_buffer, trans_bytes);
af62a557
LW		 337 return 0;
338 }
339
340 sdhci_reset(host, SDHCI_RESET_CMD);
341 sdhci_reset(host, SDHCI_RESET_DATA);
342 if (stat & SDHCI_INT_TIMEOUT)
915ffa52 343 return -ETIMEDOUT;
af62a557 344 else
915ffa52 345 return -ECOMM;
af62a557
LW		 346}
347
ca992e82
SDPP		 348#if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
349static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
350{
351 int err;
352 struct mmc *mmc = mmc_get_mmc_dev(dev);
353 struct sdhci_host *host = mmc->priv;
354
355 debug("%s\n", __func__);
356
b70fe965 357 if (host->ops && host->ops->platform_execute_tuning) {
ca992e82
SDPP		 358 err = host->ops->platform_execute_tuning(mmc, opcode);
359 if (err)
360 return err;
361 return 0;
362 }
363 return 0;
364}
365#endif
3966c7d0 366int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
af62a557 367{
93bfd616 368 struct sdhci_host *host = mmc->priv;
899fb9e3 369 unsigned int div, clk = 0, timeout;
16b593be 370 int ret;
af62a557 371
79667b7b
WY		 372 /* Wait max 20 ms */
373 timeout = 200;
374 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
375 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
376 if (timeout == 0) {
377 printf("%s: Timeout to wait cmd & data inhibit\n",
378 __func__);
2cb5d67c 379 return -EBUSY;
79667b7b
WY		 380 }
381
382 timeout--;
383 udelay(100);
384 }
385
899fb9e3 386 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
af62a557
LW		 387
388 if (clock == 0)
389 return 0;
390
16b593be
ARS		 391 if (host->ops && host->ops->set_delay) {
392 ret = host->ops->set_delay(host);
393 if (ret) {
394 printf("%s: Error while setting tap delay\n", __func__);
395 return ret;
396 }
397 }
ca992e82 398
6f5bb991
ARS		 399 if (host->ops && host->ops->config_dll) {
400 ret = host->ops->config_dll(host, clock, false);
401 if (ret) {
402 printf("%s: Error while configuring dll\n", __func__);
403 return ret;
404 }
405 }
406
113e5dfc 407 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
6dffdbc3
WY		 408 /*
409 * Check if the Host Controller supports Programmable Clock
410 * Mode.
411 */
412 if (host->clk_mul) {
413 for (div = 1; div <= 1024; div++) {
0e0dcc19 414 if ((host->max_clk / div) <= clock)
af62a557
LW		 415 break;
416 }
6dffdbc3
WY		 417
418 /*
419 * Set Programmable Clock Mode in the Clock
420 * Control register.
421 */
422 clk = SDHCI_PROG_CLOCK_MODE;
423 div--;
424 } else {
425 /* Version 3.00 divisors must be a multiple of 2. */
6d0e34bf 426 if (host->max_clk <= clock) {
6dffdbc3
WY		 427 div = 1;
428 } else {
429 for (div = 2;
430 div < SDHCI_MAX_DIV_SPEC_300;
431 div += 2) {
6d0e34bf 432 if ((host->max_clk / div) <= clock)
6dffdbc3
WY		 433 break;
434 }
435 }
436 div >>= 1;
af62a557
LW		 437 }
438 } else {
439 /* Version 2.00 divisors must be a power of 2. */
440 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
6d0e34bf 441 if ((host->max_clk / div) <= clock)
af62a557
LW		 442 break;
443 }
6dffdbc3 444 div >>= 1;
af62a557 445 }
af62a557 446
bf9c4d14 447 if (host->ops && host->ops->set_clock)
62226b68 448 host->ops->set_clock(host, div);
b09ed6e4 449
6f5bb991
ARS		 450 if (host->ops && host->ops->config_dll) {
451 ret = host->ops->config_dll(host, clock, true);
452 if (ret) {
453 printf("%s: Error while configuring dll\n", __func__);
454 return ret;
455 }
456 }
457
6dffdbc3 458 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
af62a557
LW		 459 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
460 << SDHCI_DIVIDER_HI_SHIFT;
461 clk |= SDHCI_CLOCK_INT_EN;
462 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
463
464 /* Wait max 20 ms */
465 timeout = 20;
466 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
467 & SDHCI_CLOCK_INT_STABLE)) {
468 if (timeout == 0) {
30e6d979
DR		 469 printf("%s: Internal clock never stabilised.\n",
470 __func__);
2cb5d67c 471 return -EBUSY;
af62a557
LW		 472 }
473 timeout--;
474 udelay(1000);
475 }
476
477 clk |= SDHCI_CLOCK_CARD_EN;
478 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
479 return 0;
480}
481
482static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
483{
484 u8 pwr = 0;
485
486 if (power != (unsigned short)-1) {
487 switch (1 << power) {
488 case MMC_VDD_165_195:
489 pwr = SDHCI_POWER_180;
490 break;
491 case MMC_VDD_29_30:
492 case MMC_VDD_30_31:
493 pwr = SDHCI_POWER_300;
494 break;
495 case MMC_VDD_32_33:
496 case MMC_VDD_33_34:
497 pwr = SDHCI_POWER_330;
498 break;
499 }
500 }
501
502 if (pwr == 0) {
503 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
504 return;
505 }
506
507 pwr |= SDHCI_POWER_ON;
508
509 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
510}
511
d1c0a220
FA		 512void sdhci_set_uhs_timing(struct sdhci_host *host)
513{
fdd84c8b 514 struct mmc *mmc = host->mmc;
d1c0a220
FA		 515 u32 reg;
516
517 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
518 reg &= ~SDHCI_CTRL_UHS_MASK;
519
520 switch (mmc->selected_mode) {
521 case UHS_SDR50:
522 case MMC_HS_52:
523 reg |= SDHCI_CTRL_UHS_SDR50;
524 break;
525 case UHS_DDR50:
526 case MMC_DDR_52:
527 reg |= SDHCI_CTRL_UHS_DDR50;
528 break;
529 case UHS_SDR104:
530 case MMC_HS_200:
531 reg |= SDHCI_CTRL_UHS_SDR104;
532 break;
bda47bef 533 case MMC_HS_400:
2a1d7c63 534 case MMC_HS_400_ES:
bda47bef
FA		 535 reg |= SDHCI_CTRL_HS400;
536 break;
d1c0a220
FA		 537 default:
538 reg |= SDHCI_CTRL_UHS_SDR12;
539 }
540
541 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
542}
543
43392b55
FA		 544static void sdhci_set_voltage(struct sdhci_host *host)
545{
546 if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) {
547 struct mmc *mmc = (struct mmc *)host->mmc;
548 u32 ctrl;
549
550 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
551
552 switch (mmc->signal_voltage) {
553 case MMC_SIGNAL_VOLTAGE_330:
554#if CONFIG_IS_ENABLED(DM_REGULATOR)
555 if (mmc->vqmmc_supply) {
556 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
557 pr_err("failed to disable vqmmc-supply\n");
558 return;
559 }
560
561 if (regulator_set_value(mmc->vqmmc_supply, 3300000)) {
562 pr_err("failed to set vqmmc-voltage to 3.3V\n");
563 return;
564 }
565
566 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
567 pr_err("failed to enable vqmmc-supply\n");
568 return;
569 }
570 }
571#endif
572 if (IS_SD(mmc)) {
573 ctrl &= ~SDHCI_CTRL_VDD_180;
574 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
575 }
576
577 /* Wait for 5ms */
578 mdelay(5);
579
580 /* 3.3V regulator output should be stable within 5 ms */
581 if (IS_SD(mmc)) {
582 if (ctrl & SDHCI_CTRL_VDD_180) {
583 pr_err("3.3V regulator output did not become stable\n");
584 return;
585 }
586 }
587
588 break;
589 case MMC_SIGNAL_VOLTAGE_180:
590#if CONFIG_IS_ENABLED(DM_REGULATOR)
591 if (mmc->vqmmc_supply) {
592 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
593 pr_err("failed to disable vqmmc-supply\n");
594 return;
595 }
596
597 if (regulator_set_value(mmc->vqmmc_supply, 1800000)) {
598 pr_err("failed to set vqmmc-voltage to 1.8V\n");
599 return;
600 }
601
602 if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
603 pr_err("failed to enable vqmmc-supply\n");
604 return;
605 }
606 }
607#endif
608 if (IS_SD(mmc)) {
609 ctrl |= SDHCI_CTRL_VDD_180;
610 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
611 }
612
613 /* Wait for 5 ms */
614 mdelay(5);
615
616 /* 1.8V regulator output has to be stable within 5 ms */
617 if (IS_SD(mmc)) {
618 if (!(ctrl & SDHCI_CTRL_VDD_180)) {
619 pr_err("1.8V regulator output did not become stable\n");
620 return;
621 }
622 }
623
624 break;
625 default:
626 /* No signal voltage switch required */
627 return;
628 }
629 }
630}
631
632void sdhci_set_control_reg(struct sdhci_host *host)
633{
634 sdhci_set_voltage(host);
635 sdhci_set_uhs_timing(host);
636}
637
e7881d85 638#ifdef CONFIG_DM_MMC
ef1e4eda
SG		 639static int sdhci_set_ios(struct udevice *dev)
640{
641 struct mmc *mmc = mmc_get_mmc_dev(dev);
642#else
07b0b9c0 643static int sdhci_set_ios(struct mmc *mmc)
af62a557 644{
ef1e4eda 645#endif
af62a557 646 u32 ctrl;
93bfd616 647 struct sdhci_host *host = mmc->priv;
f12341a9 648 bool no_hispd_bit = false;
af62a557 649
bf9c4d14 650 if (host->ops && host->ops->set_control_reg)
62226b68 651 host->ops->set_control_reg(host);
236bfecf 652
af62a557
LW		 653 if (mmc->clock != host->clock)
654 sdhci_set_clock(mmc, mmc->clock);
655
2a2d7efe
SDPP		 656 if (mmc->clk_disable)
657 sdhci_set_clock(mmc, 0);
658
af62a557
LW		 659 /* Set bus width */
660 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
661 if (mmc->bus_width == 8) {
662 ctrl &= ~SDHCI_CTRL_4BITBUS;
113e5dfc
JC		 663 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
664 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
af62a557
LW		 665 ctrl |= SDHCI_CTRL_8BITBUS;
666 } else {
f88a429f
MR		 667 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
668 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
af62a557
LW		 669 ctrl &= ~SDHCI_CTRL_8BITBUS;
670 if (mmc->bus_width == 4)
671 ctrl |= SDHCI_CTRL_4BITBUS;
672 else
673 ctrl &= ~SDHCI_CTRL_4BITBUS;
674 }
675
88a57125 676 if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
f12341a9 677 (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
236bfecf 678 ctrl &= ~SDHCI_CTRL_HISPD;
f12341a9
JT		 679 no_hispd_bit = true;
680 }
681
682 if (!no_hispd_bit) {
683 if (mmc->selected_mode == MMC_HS ||
684 mmc->selected_mode == SD_HS ||
685 mmc->selected_mode == MMC_DDR_52 ||
686 mmc->selected_mode == MMC_HS_200 ||
687 mmc->selected_mode == MMC_HS_400 ||
2a1d7c63 688 mmc->selected_mode == MMC_HS_400_ES ||
f12341a9
JT		 689 mmc->selected_mode == UHS_SDR25 ||
690 mmc->selected_mode == UHS_SDR50 ||
691 mmc->selected_mode == UHS_SDR104 ||
692 mmc->selected_mode == UHS_DDR50)
693 ctrl |= SDHCI_CTRL_HISPD;
694 else
695 ctrl &= ~SDHCI_CTRL_HISPD;
696 }
236bfecf 697
af62a557 698 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
07b0b9c0 699
210841c6
SR		 700 /* If available, call the driver specific "post" set_ios() function */
701 if (host->ops && host->ops->set_ios_post)
a8185c50 702 return host->ops->set_ios_post(host);
210841c6 703
ef1e4eda 704 return 0;
af62a557
LW		 705}
706
6588c78b 707static int sdhci_init(struct mmc *mmc)
af62a557 708{
93bfd616 709 struct sdhci_host *host = mmc->priv;
451931ea
KR		 710#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
711 struct udevice *dev = mmc->dev;
712
58d65d50 713 gpio_request_by_name(dev, "cd-gpios", 0,
451931ea
KR		 714 &host->cd_gpio, GPIOD_IS_IN);
715#endif
af62a557 716
8d549b61
MY		 717 sdhci_reset(host, SDHCI_RESET_ALL);
718
c8cc18b7
MY		 719#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
720 host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
f5df6aa1
MY		 721 /*
722 * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
723 * is defined.
724 */
725 host->force_align_buffer = true;
c8cc18b7
MY		 726#else
727 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
728 host->align_buffer = memalign(8, 512 * 1024);
729 if (!host->align_buffer) {
30e6d979
DR		 730 printf("%s: Aligned buffer alloc failed!!!\n",
731 __func__);
2cb5d67c 732 return -ENOMEM;
af62a557
LW		 733 }
734 }
c8cc18b7 735#endif
af62a557 736
93bfd616 737 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
470dcc75 738
bf9c4d14 739 if (host->ops && host->ops->get_cd)
6f88a3a5 740 host->ops->get_cd(host);
470dcc75 741
ce0c1bc1 742 /* Enable only interrupts served by the SD controller */
30e6d979
DR		 743 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
744 SDHCI_INT_ENABLE);
ce0c1bc1
ŁM		 745 /* Mask all sdhci interrupt sources */
746 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
af62a557 747
af62a557
LW		 748 return 0;
749}
750
e7881d85 751#ifdef CONFIG_DM_MMC
ef1e4eda
SG		 752int sdhci_probe(struct udevice *dev)
753{
754 struct mmc *mmc = mmc_get_mmc_dev(dev);
755
756 return sdhci_init(mmc);
757}
ab769f22 758
cb884347
FA		 759static int sdhci_deferred_probe(struct udevice *dev)
760{
761 int err;
762 struct mmc *mmc = mmc_get_mmc_dev(dev);
763 struct sdhci_host *host = mmc->priv;
764
765 if (host->ops && host->ops->deferred_probe) {
766 err = host->ops->deferred_probe(host);
767 if (err)
768 return err;
769 }
770 return 0;
771}
772
1b716952 773static int sdhci_get_cd(struct udevice *dev)
da18c62b
KR		 774{
775 struct mmc *mmc = mmc_get_mmc_dev(dev);
776 struct sdhci_host *host = mmc->priv;
777 int value;
778
779 /* If nonremovable, assume that the card is always present. */
780 if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
781 return 1;
782 /* If polling, assume that the card is always present. */
783 if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
784 return 1;
785
786#if CONFIG_IS_ENABLED(DM_GPIO)
787 value = dm_gpio_get_value(&host->cd_gpio);
788 if (value >= 0) {
789 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
790 return !value;
791 else
792 return value;
793 }
794#endif
795 value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
796 SDHCI_CARD_PRESENT);
797 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
798 return !value;
799 else
800 return value;
801}
802
40e6f524
SC		 803static int sdhci_wait_dat0(struct udevice *dev, int state,
804 int timeout_us)
805{
806 int tmp;
807 struct mmc *mmc = mmc_get_mmc_dev(dev);
808 struct sdhci_host *host = mmc->priv;
809 unsigned long timeout = timer_get_us() + timeout_us;
810
811 // readx_poll_timeout is unsuitable because sdhci_readl accepts
812 // two arguments
813 do {
814 tmp = sdhci_readl(host, SDHCI_PRESENT_STATE);
815 if (!!(tmp & SDHCI_DATA_0_LVL_MASK) == !!state)
816 return 0;
817 } while (!timeout_us || !time_after(timer_get_us(), timeout));
818
819 return -ETIMEDOUT;
820}
821
2a1d7c63
ANY		 822#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
823static int sdhci_set_enhanced_strobe(struct udevice *dev)
824{
825 struct mmc *mmc = mmc_get_mmc_dev(dev);
826 struct sdhci_host *host = mmc->priv;
827
828 if (host->ops && host->ops->set_enhanced_strobe)
829 return host->ops->set_enhanced_strobe(host);
830
831 return -ENOTSUPP;
832}
833#endif
834
ef1e4eda
SG		 835const struct dm_mmc_ops sdhci_ops = {
836 .send_cmd = sdhci_send_command,
837 .set_ios = sdhci_set_ios,
da18c62b 838 .get_cd = sdhci_get_cd,
cb884347 839 .deferred_probe = sdhci_deferred_probe,
ca992e82
SDPP		 840#ifdef MMC_SUPPORTS_TUNING
841 .execute_tuning = sdhci_execute_tuning,
842#endif
40e6f524 843 .wait_dat0 = sdhci_wait_dat0,
2a1d7c63
ANY		 844#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
845 .set_enhanced_strobe = sdhci_set_enhanced_strobe,
846#endif
ef1e4eda
SG		 847};
848#else
ab769f22
PA		 849static const struct mmc_ops sdhci_ops = {
850 .send_cmd = sdhci_send_command,
851 .set_ios = sdhci_set_ios,
852 .init = sdhci_init,
853};
ef1e4eda 854#endif
ab769f22 855
14bed52d 856int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
6d0e34bf 857 u32 f_max, u32 f_min)
af62a557 858{
b8e25ef1 859 u32 caps, caps_1 = 0;
3d296365 860#if CONFIG_IS_ENABLED(DM_MMC)
cd45d6f3
KR		 861 u64 dt_caps, dt_caps_mask;
862
863 dt_caps_mask = dev_read_u64_default(host->mmc->dev,
864 "sdhci-caps-mask", 0);
865 dt_caps = dev_read_u64_default(host->mmc->dev,
866 "sdhci-caps", 0);
b5a3387d 867 caps = ~lower_32_bits(dt_caps_mask) &
cd45d6f3 868 sdhci_readl(host, SDHCI_CAPABILITIES);
b5a3387d 869 caps |= lower_32_bits(dt_caps);
3d296365 870#else
14bed52d 871 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
3d296365 872#endif
cd45d6f3 873 debug("%s, caps: 0x%x\n", __func__, caps);
15bd0995 874
45a68fe2 875#ifdef CONFIG_MMC_SDHCI_SDMA
fabb3a43
JC		 876 if ((caps & SDHCI_CAN_DO_SDMA)) {
877 host->flags |= USE_SDMA;
878 } else {
7acdc9aa
MB		 879 debug("%s: Your controller doesn't support SDMA!!\n",
880 __func__);
15bd0995 881 }
37cb626d
FA		 882#endif
883#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
884 if (!(caps & SDHCI_CAN_DO_ADMA2)) {
885 printf("%s: Your controller doesn't support SDMA!!\n",
886 __func__);
887 return -EINVAL;
888 }
4d6a773b 889 host->adma_desc_table = sdhci_adma_init();
37cb626d 890 host->adma_addr = (dma_addr_t)host->adma_desc_table;
4d6a773b 891
37cb626d
FA		 892#ifdef CONFIG_DMA_ADDR_T_64BIT
893 host->flags |= USE_ADMA64;
894#else
895 host->flags |= USE_ADMA;
896#endif
15bd0995 897#endif
895549a2
JC		 898 if (host->quirks & SDHCI_QUIRK_REG32_RW)
899 host->version =
900 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
901 else
902 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
14bed52d
JC		 903
904 cfg->name = host->name;
e7881d85 905#ifndef CONFIG_DM_MMC
2a809093 906 cfg->ops = &sdhci_ops;
af62a557 907#endif
0e0dcc19
WY		 908
909 /* Check whether the clock multiplier is supported or not */
910 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
3d296365 911#if CONFIG_IS_ENABLED(DM_MMC)
b5a3387d 912 caps_1 = ~upper_32_bits(dt_caps_mask) &
cd45d6f3 913 sdhci_readl(host, SDHCI_CAPABILITIES_1);
b5a3387d 914 caps_1 |= upper_32_bits(dt_caps);
3d296365 915#else
0e0dcc19 916 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
3d296365 917#endif
cd45d6f3 918 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
0e0dcc19
WY		 919 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
920 SDHCI_CLOCK_MUL_SHIFT;
921 }
922
6d0e34bf 923 if (host->max_clk == 0) {
14bed52d 924 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
6d0e34bf 925 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
2a809093 926 SDHCI_CLOCK_BASE_SHIFT;
af62a557 927 else
6d0e34bf 928 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
2a809093 929 SDHCI_CLOCK_BASE_SHIFT;
6d0e34bf 930 host->max_clk *= 1000000;
0e0dcc19
WY		 931 if (host->clk_mul)
932 host->max_clk *= host->clk_mul;
af62a557 933 }
6d0e34bf 934 if (host->max_clk == 0) {
6c67954c
MY		 935 printf("%s: Hardware doesn't specify base clock frequency\n",
936 __func__);
2a809093 937 return -EINVAL;
6c67954c 938 }
6d0e34bf
SH		 939 if (f_max && (f_max < host->max_clk))
940 cfg->f_max = f_max;
941 else
942 cfg->f_max = host->max_clk;
943 if (f_min)
944 cfg->f_min = f_min;
af62a557 945 else {
14bed52d 946 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
2a809093 947 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
af62a557 948 else
2a809093 949 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
af62a557 950 }
2a809093 951 cfg->voltages = 0;
af62a557 952 if (caps & SDHCI_CAN_VDD_330)
2a809093 953 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
af62a557 954 if (caps & SDHCI_CAN_VDD_300)
2a809093 955 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
af62a557 956 if (caps & SDHCI_CAN_VDD_180)
2a809093 957 cfg->voltages |= MMC_VDD_165_195;
236bfecf 958
3137e645
MY		 959 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
960 cfg->voltages |= host->voltages;
961
620bb46e
FA		 962 if (caps & SDHCI_CAN_DO_HISPD)
963 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
964
965 cfg->host_caps |= MMC_MODE_4BIT;
3fd0a9ba
JC		 966
967 /* Since Host Controller Version3.0 */
14bed52d 968 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
ecd7b246
JC		 969 if (!(caps & SDHCI_CAN_DO_8BIT))
970 cfg->host_caps &= ~MMC_MODE_8BIT;
1695b29a 971 }
42979002 972
88a57125
HS		 973 if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
974 cfg->host_caps &= ~MMC_MODE_HS;
975 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
976 }
977
7a49a16e
ARS		 978 if (!(cfg->voltages & MMC_VDD_165_195) ||
979 (host->quirks & SDHCI_QUIRK_NO_1_8_V))
b8e25ef1
SDPP		 980 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
981 SDHCI_SUPPORT_DDR50);
982
983 if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
984 SDHCI_SUPPORT_DDR50))
985 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
986
987 if (caps_1 & SDHCI_SUPPORT_SDR104) {
988 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
989 /*
990 * SD3.0: SDR104 is supported so (for eMMC) the caps2
991 * field can be promoted to support HS200.
992 */
993 cfg->host_caps |= MMC_CAP(MMC_HS_200);
994 } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
995 cfg->host_caps |= MMC_CAP(UHS_SDR50);
996 }
997
998 if (caps_1 & SDHCI_SUPPORT_DDR50)
999 cfg->host_caps |= MMC_CAP(UHS_DDR50);
1000
14bed52d
JC		 1001 if (host->host_caps)
1002 cfg->host_caps |= host->host_caps;
42979002 1003
2a809093 1004 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
93bfd616 1005
2a809093
SG		 1006 return 0;
1007}
1008
ef1e4eda
SG		 1009#ifdef CONFIG_BLK
1010int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
1011{
1012 return mmc_bind(dev, mmc, cfg);
1013}
1014#else
6d0e34bf 1015int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
2a809093 1016{
6c67954c
MY		 1017 int ret;
1018
6d0e34bf 1019 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
6c67954c
MY		 1020 if (ret)
1021 return ret;
2a809093 1022
93bfd616
PA		 1023 host->mmc = mmc_create(&host->cfg, host);
1024 if (host->mmc == NULL) {
1025 printf("%s: mmc create fail!\n", __func__);
2cb5d67c 1026 return -ENOMEM;
93bfd616 1027 }
af62a557
LW		 1028
1029 return 0;
1030}
ef1e4eda 1031#endif
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