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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
b312c590 | 2 | /* |
3bc599c9 | 3 | * Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
0f8106f8 | 4 | * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. |
b312c590 PC |
5 | */ |
6 | ||
4dbaa1b6 PD |
7 | #define LOG_CATEGORY UCLASS_MMC |
8 | ||
d678a59d | 9 | #include <common.h> |
b312c590 | 10 | #include <clk.h> |
1eb69ae4 | 11 | #include <cpu_func.h> |
b312c590 PC |
12 | #include <dm.h> |
13 | #include <fdtdec.h> | |
f7ae49fc | 14 | #include <log.h> |
336d4615 | 15 | #include <malloc.h> |
cd93d625 | 16 | #include <asm/bitops.h> |
90526e9f | 17 | #include <asm/cache.h> |
4dbaa1b6 | 18 | #include <dm/device_compat.h> |
8e5266ee | 19 | #include <dm/pinctrl.h> |
cd93d625 | 20 | #include <linux/bitops.h> |
c05ed00a | 21 | #include <linux/delay.h> |
b08c8c48 | 22 | #include <linux/libfdt.h> |
b312c590 PC |
23 | #include <mmc.h> |
24 | #include <reset.h> | |
25 | #include <asm/io.h> | |
26 | #include <asm/gpio.h> | |
27 | #include <linux/iopoll.h> | |
359c176d | 28 | #include <power/regulator.h> |
48ac723a | 29 | #include <watchdog.h> |
1e94b46f | 30 | #include <linux/printk.h> |
b312c590 PC |
31 | |
32 | struct stm32_sdmmc2_plat { | |
33 | struct mmc_config cfg; | |
34 | struct mmc mmc; | |
b312c590 PC |
35 | fdt_addr_t base; |
36 | struct clk clk; | |
37 | struct reset_ctl reset_ctl; | |
38 | struct gpio_desc cd_gpio; | |
39 | u32 clk_reg_msk; | |
40 | u32 pwr_reg_msk; | |
359c176d YG |
41 | #if CONFIG_IS_ENABLED(DM_REGULATOR) |
42 | bool vqmmc_enabled; | |
43 | #endif | |
b312c590 PC |
44 | }; |
45 | ||
46 | struct stm32_sdmmc2_ctx { | |
47 | u32 cache_start; | |
48 | u32 cache_end; | |
49 | u32 data_length; | |
50 | bool dpsm_abort; | |
51 | }; | |
52 | ||
53 | /* SDMMC REGISTERS OFFSET */ | |
54 | #define SDMMC_POWER 0x00 /* SDMMC power control */ | |
55 | #define SDMMC_CLKCR 0x04 /* SDMMC clock control */ | |
56 | #define SDMMC_ARG 0x08 /* SDMMC argument */ | |
57 | #define SDMMC_CMD 0x0C /* SDMMC command */ | |
58 | #define SDMMC_RESP1 0x14 /* SDMMC response 1 */ | |
59 | #define SDMMC_RESP2 0x18 /* SDMMC response 2 */ | |
60 | #define SDMMC_RESP3 0x1C /* SDMMC response 3 */ | |
61 | #define SDMMC_RESP4 0x20 /* SDMMC response 4 */ | |
62 | #define SDMMC_DTIMER 0x24 /* SDMMC data timer */ | |
63 | #define SDMMC_DLEN 0x28 /* SDMMC data length */ | |
64 | #define SDMMC_DCTRL 0x2C /* SDMMC data control */ | |
65 | #define SDMMC_DCOUNT 0x30 /* SDMMC data counter */ | |
66 | #define SDMMC_STA 0x34 /* SDMMC status */ | |
67 | #define SDMMC_ICR 0x38 /* SDMMC interrupt clear */ | |
68 | #define SDMMC_MASK 0x3C /* SDMMC mask */ | |
69 | #define SDMMC_IDMACTRL 0x50 /* SDMMC DMA control */ | |
70 | #define SDMMC_IDMABASE0 0x58 /* SDMMC DMA buffer 0 base address */ | |
71 | ||
72 | /* SDMMC_POWER register */ | |
7d118161 PD |
73 | #define SDMMC_POWER_PWRCTRL_MASK GENMASK(1, 0) |
74 | #define SDMMC_POWER_PWRCTRL_OFF 0 | |
75 | #define SDMMC_POWER_PWRCTRL_CYCLE 2 | |
76 | #define SDMMC_POWER_PWRCTRL_ON 3 | |
b312c590 PC |
77 | #define SDMMC_POWER_VSWITCH BIT(2) |
78 | #define SDMMC_POWER_VSWITCHEN BIT(3) | |
79 | #define SDMMC_POWER_DIRPOL BIT(4) | |
80 | ||
81 | /* SDMMC_CLKCR register */ | |
82 | #define SDMMC_CLKCR_CLKDIV GENMASK(9, 0) | |
83 | #define SDMMC_CLKCR_CLKDIV_MAX SDMMC_CLKCR_CLKDIV | |
84 | #define SDMMC_CLKCR_PWRSAV BIT(12) | |
85 | #define SDMMC_CLKCR_WIDBUS_4 BIT(14) | |
86 | #define SDMMC_CLKCR_WIDBUS_8 BIT(15) | |
87 | #define SDMMC_CLKCR_NEGEDGE BIT(16) | |
88 | #define SDMMC_CLKCR_HWFC_EN BIT(17) | |
89 | #define SDMMC_CLKCR_DDR BIT(18) | |
90 | #define SDMMC_CLKCR_BUSSPEED BIT(19) | |
167f2c90 PD |
91 | #define SDMMC_CLKCR_SELCLKRX_MASK GENMASK(21, 20) |
92 | #define SDMMC_CLKCR_SELCLKRX_CK 0 | |
93 | #define SDMMC_CLKCR_SELCLKRX_CKIN BIT(20) | |
94 | #define SDMMC_CLKCR_SELCLKRX_FBCK BIT(21) | |
b312c590 PC |
95 | |
96 | /* SDMMC_CMD register */ | |
97 | #define SDMMC_CMD_CMDINDEX GENMASK(5, 0) | |
98 | #define SDMMC_CMD_CMDTRANS BIT(6) | |
99 | #define SDMMC_CMD_CMDSTOP BIT(7) | |
100 | #define SDMMC_CMD_WAITRESP GENMASK(9, 8) | |
101 | #define SDMMC_CMD_WAITRESP_0 BIT(8) | |
102 | #define SDMMC_CMD_WAITRESP_1 BIT(9) | |
103 | #define SDMMC_CMD_WAITINT BIT(10) | |
104 | #define SDMMC_CMD_WAITPEND BIT(11) | |
105 | #define SDMMC_CMD_CPSMEN BIT(12) | |
106 | #define SDMMC_CMD_DTHOLD BIT(13) | |
107 | #define SDMMC_CMD_BOOTMODE BIT(14) | |
108 | #define SDMMC_CMD_BOOTEN BIT(15) | |
109 | #define SDMMC_CMD_CMDSUSPEND BIT(16) | |
110 | ||
111 | /* SDMMC_DCTRL register */ | |
112 | #define SDMMC_DCTRL_DTEN BIT(0) | |
113 | #define SDMMC_DCTRL_DTDIR BIT(1) | |
114 | #define SDMMC_DCTRL_DTMODE GENMASK(3, 2) | |
115 | #define SDMMC_DCTRL_DBLOCKSIZE GENMASK(7, 4) | |
116 | #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT 4 | |
117 | #define SDMMC_DCTRL_RWSTART BIT(8) | |
118 | #define SDMMC_DCTRL_RWSTOP BIT(9) | |
119 | #define SDMMC_DCTRL_RWMOD BIT(10) | |
120 | #define SDMMC_DCTRL_SDMMCEN BIT(11) | |
121 | #define SDMMC_DCTRL_BOOTACKEN BIT(12) | |
122 | #define SDMMC_DCTRL_FIFORST BIT(13) | |
123 | ||
124 | /* SDMMC_STA register */ | |
125 | #define SDMMC_STA_CCRCFAIL BIT(0) | |
126 | #define SDMMC_STA_DCRCFAIL BIT(1) | |
127 | #define SDMMC_STA_CTIMEOUT BIT(2) | |
128 | #define SDMMC_STA_DTIMEOUT BIT(3) | |
129 | #define SDMMC_STA_TXUNDERR BIT(4) | |
130 | #define SDMMC_STA_RXOVERR BIT(5) | |
131 | #define SDMMC_STA_CMDREND BIT(6) | |
132 | #define SDMMC_STA_CMDSENT BIT(7) | |
133 | #define SDMMC_STA_DATAEND BIT(8) | |
134 | #define SDMMC_STA_DHOLD BIT(9) | |
135 | #define SDMMC_STA_DBCKEND BIT(10) | |
136 | #define SDMMC_STA_DABORT BIT(11) | |
137 | #define SDMMC_STA_DPSMACT BIT(12) | |
138 | #define SDMMC_STA_CPSMACT BIT(13) | |
139 | #define SDMMC_STA_TXFIFOHE BIT(14) | |
140 | #define SDMMC_STA_RXFIFOHF BIT(15) | |
141 | #define SDMMC_STA_TXFIFOF BIT(16) | |
142 | #define SDMMC_STA_RXFIFOF BIT(17) | |
143 | #define SDMMC_STA_TXFIFOE BIT(18) | |
144 | #define SDMMC_STA_RXFIFOE BIT(19) | |
145 | #define SDMMC_STA_BUSYD0 BIT(20) | |
146 | #define SDMMC_STA_BUSYD0END BIT(21) | |
147 | #define SDMMC_STA_SDMMCIT BIT(22) | |
148 | #define SDMMC_STA_ACKFAIL BIT(23) | |
149 | #define SDMMC_STA_ACKTIMEOUT BIT(24) | |
150 | #define SDMMC_STA_VSWEND BIT(25) | |
151 | #define SDMMC_STA_CKSTOP BIT(26) | |
152 | #define SDMMC_STA_IDMATE BIT(27) | |
153 | #define SDMMC_STA_IDMABTC BIT(28) | |
154 | ||
155 | /* SDMMC_ICR register */ | |
156 | #define SDMMC_ICR_CCRCFAILC BIT(0) | |
157 | #define SDMMC_ICR_DCRCFAILC BIT(1) | |
158 | #define SDMMC_ICR_CTIMEOUTC BIT(2) | |
159 | #define SDMMC_ICR_DTIMEOUTC BIT(3) | |
160 | #define SDMMC_ICR_TXUNDERRC BIT(4) | |
161 | #define SDMMC_ICR_RXOVERRC BIT(5) | |
162 | #define SDMMC_ICR_CMDRENDC BIT(6) | |
163 | #define SDMMC_ICR_CMDSENTC BIT(7) | |
164 | #define SDMMC_ICR_DATAENDC BIT(8) | |
165 | #define SDMMC_ICR_DHOLDC BIT(9) | |
166 | #define SDMMC_ICR_DBCKENDC BIT(10) | |
167 | #define SDMMC_ICR_DABORTC BIT(11) | |
168 | #define SDMMC_ICR_BUSYD0ENDC BIT(21) | |
169 | #define SDMMC_ICR_SDMMCITC BIT(22) | |
170 | #define SDMMC_ICR_ACKFAILC BIT(23) | |
171 | #define SDMMC_ICR_ACKTIMEOUTC BIT(24) | |
172 | #define SDMMC_ICR_VSWENDC BIT(25) | |
173 | #define SDMMC_ICR_CKSTOPC BIT(26) | |
174 | #define SDMMC_ICR_IDMATEC BIT(27) | |
175 | #define SDMMC_ICR_IDMABTCC BIT(28) | |
176 | #define SDMMC_ICR_STATIC_FLAGS ((GENMASK(28, 21)) | (GENMASK(11, 0))) | |
177 | ||
178 | /* SDMMC_MASK register */ | |
179 | #define SDMMC_MASK_CCRCFAILIE BIT(0) | |
180 | #define SDMMC_MASK_DCRCFAILIE BIT(1) | |
181 | #define SDMMC_MASK_CTIMEOUTIE BIT(2) | |
182 | #define SDMMC_MASK_DTIMEOUTIE BIT(3) | |
183 | #define SDMMC_MASK_TXUNDERRIE BIT(4) | |
184 | #define SDMMC_MASK_RXOVERRIE BIT(5) | |
185 | #define SDMMC_MASK_CMDRENDIE BIT(6) | |
186 | #define SDMMC_MASK_CMDSENTIE BIT(7) | |
187 | #define SDMMC_MASK_DATAENDIE BIT(8) | |
188 | #define SDMMC_MASK_DHOLDIE BIT(9) | |
189 | #define SDMMC_MASK_DBCKENDIE BIT(10) | |
190 | #define SDMMC_MASK_DABORTIE BIT(11) | |
191 | #define SDMMC_MASK_TXFIFOHEIE BIT(14) | |
192 | #define SDMMC_MASK_RXFIFOHFIE BIT(15) | |
193 | #define SDMMC_MASK_RXFIFOFIE BIT(17) | |
194 | #define SDMMC_MASK_TXFIFOEIE BIT(18) | |
195 | #define SDMMC_MASK_BUSYD0ENDIE BIT(21) | |
196 | #define SDMMC_MASK_SDMMCITIE BIT(22) | |
197 | #define SDMMC_MASK_ACKFAILIE BIT(23) | |
198 | #define SDMMC_MASK_ACKTIMEOUTIE BIT(24) | |
199 | #define SDMMC_MASK_VSWENDIE BIT(25) | |
200 | #define SDMMC_MASK_CKSTOPIE BIT(26) | |
201 | #define SDMMC_MASK_IDMABTCIE BIT(28) | |
202 | ||
203 | /* SDMMC_IDMACTRL register */ | |
204 | #define SDMMC_IDMACTRL_IDMAEN BIT(0) | |
205 | ||
206 | #define SDMMC_CMD_TIMEOUT 0xFFFFFFFF | |
23441fbf | 207 | #define SDMMC_BUSYD0END_TIMEOUT_US 2000000 |
b312c590 | 208 | |
4dbaa1b6 | 209 | static void stm32_sdmmc2_start_data(struct udevice *dev, |
b312c590 PC |
210 | struct mmc_data *data, |
211 | struct stm32_sdmmc2_ctx *ctx) | |
212 | { | |
efd77dbc | 213 | struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); |
b312c590 PC |
214 | u32 data_ctrl, idmabase0; |
215 | ||
216 | /* Configure the SDMMC DPSM (Data Path State Machine) */ | |
217 | data_ctrl = (__ilog2(data->blocksize) << | |
218 | SDMMC_DCTRL_DBLOCKSIZE_SHIFT) & | |
219 | SDMMC_DCTRL_DBLOCKSIZE; | |
220 | ||
221 | if (data->flags & MMC_DATA_READ) { | |
222 | data_ctrl |= SDMMC_DCTRL_DTDIR; | |
e725682d | 223 | idmabase0 = (u32)(long)data->dest; |
b312c590 | 224 | } else { |
e725682d | 225 | idmabase0 = (u32)(long)data->src; |
b312c590 PC |
226 | } |
227 | ||
b312c590 | 228 | /* Set the SDMMC DataLength value */ |
efd77dbc | 229 | writel(ctx->data_length, plat->base + SDMMC_DLEN); |
b312c590 PC |
230 | |
231 | /* Write to SDMMC DCTRL */ | |
efd77dbc | 232 | writel(data_ctrl, plat->base + SDMMC_DCTRL); |
b312c590 PC |
233 | |
234 | /* Cache align */ | |
235 | ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN); | |
236 | ctx->cache_end = roundup(idmabase0 + ctx->data_length, | |
237 | ARCH_DMA_MINALIGN); | |
238 | ||
239 | /* | |
240 | * Flush data cache before DMA start (clean and invalidate) | |
241 | * Clean also needed for read | |
242 | * Avoid issue on buffer not cached-aligned | |
243 | */ | |
244 | flush_dcache_range(ctx->cache_start, ctx->cache_end); | |
245 | ||
246 | /* Enable internal DMA */ | |
efd77dbc PD |
247 | writel(idmabase0, plat->base + SDMMC_IDMABASE0); |
248 | writel(SDMMC_IDMACTRL_IDMAEN, plat->base + SDMMC_IDMACTRL); | |
b312c590 PC |
249 | } |
250 | ||
4dbaa1b6 | 251 | static void stm32_sdmmc2_start_cmd(struct udevice *dev, |
c406a474 CK |
252 | struct mmc_cmd *cmd, u32 cmd_param, |
253 | struct stm32_sdmmc2_ctx *ctx) | |
b312c590 | 254 | { |
efd77dbc | 255 | struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); |
c406a474 CK |
256 | u32 timeout = 0; |
257 | ||
efd77dbc PD |
258 | if (readl(plat->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN) |
259 | writel(0, plat->base + SDMMC_CMD); | |
b312c590 PC |
260 | |
261 | cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN; | |
262 | if (cmd->resp_type & MMC_RSP_PRESENT) { | |
263 | if (cmd->resp_type & MMC_RSP_136) | |
264 | cmd_param |= SDMMC_CMD_WAITRESP; | |
265 | else if (cmd->resp_type & MMC_RSP_CRC) | |
266 | cmd_param |= SDMMC_CMD_WAITRESP_0; | |
267 | else | |
268 | cmd_param |= SDMMC_CMD_WAITRESP_1; | |
269 | } | |
270 | ||
c406a474 CK |
271 | /* |
272 | * SDMMC_DTIME must be set in two case: | |
273 | * - on data transfert. | |
274 | * - on busy request. | |
275 | * If not done or too short, the dtimeout flag occurs and DPSM stays | |
276 | * enabled/busy and waits for abort (stop transmission cmd). | |
277 | * Next data command is not possible whereas DPSM is activated. | |
278 | */ | |
279 | if (ctx->data_length) { | |
280 | timeout = SDMMC_CMD_TIMEOUT; | |
281 | } else { | |
efd77dbc | 282 | writel(0, plat->base + SDMMC_DCTRL); |
c406a474 CK |
283 | |
284 | if (cmd->resp_type & MMC_RSP_BUSY) | |
285 | timeout = SDMMC_CMD_TIMEOUT; | |
286 | } | |
287 | ||
288 | /* Set the SDMMC Data TimeOut value */ | |
efd77dbc | 289 | writel(timeout, plat->base + SDMMC_DTIMER); |
c406a474 | 290 | |
b312c590 | 291 | /* Clear flags */ |
efd77dbc | 292 | writel(SDMMC_ICR_STATIC_FLAGS, plat->base + SDMMC_ICR); |
b312c590 PC |
293 | |
294 | /* Set SDMMC argument value */ | |
efd77dbc | 295 | writel(cmd->cmdarg, plat->base + SDMMC_ARG); |
b312c590 PC |
296 | |
297 | /* Set SDMMC command parameters */ | |
efd77dbc | 298 | writel(cmd_param, plat->base + SDMMC_CMD); |
b312c590 PC |
299 | } |
300 | ||
4dbaa1b6 | 301 | static int stm32_sdmmc2_end_cmd(struct udevice *dev, |
b312c590 PC |
302 | struct mmc_cmd *cmd, |
303 | struct stm32_sdmmc2_ctx *ctx) | |
304 | { | |
efd77dbc | 305 | struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); |
b312c590 PC |
306 | u32 mask = SDMMC_STA_CTIMEOUT; |
307 | u32 status; | |
308 | int ret; | |
309 | ||
310 | if (cmd->resp_type & MMC_RSP_PRESENT) { | |
311 | mask |= SDMMC_STA_CMDREND; | |
312 | if (cmd->resp_type & MMC_RSP_CRC) | |
313 | mask |= SDMMC_STA_CCRCFAIL; | |
314 | } else { | |
315 | mask |= SDMMC_STA_CMDSENT; | |
316 | } | |
317 | ||
318 | /* Polling status register */ | |
efd77dbc | 319 | ret = readl_poll_timeout(plat->base + SDMMC_STA, status, status & mask, |
6c36e97b | 320 | 10000); |
b312c590 PC |
321 | |
322 | if (ret < 0) { | |
4dbaa1b6 | 323 | dev_dbg(dev, "timeout reading SDMMC_STA register\n"); |
b312c590 PC |
324 | ctx->dpsm_abort = true; |
325 | return ret; | |
326 | } | |
327 | ||
328 | /* Check status */ | |
329 | if (status & SDMMC_STA_CTIMEOUT) { | |
4dbaa1b6 PD |
330 | dev_dbg(dev, "error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n", |
331 | status, cmd->cmdidx); | |
b312c590 PC |
332 | ctx->dpsm_abort = true; |
333 | return -ETIMEDOUT; | |
334 | } | |
335 | ||
336 | if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) { | |
4dbaa1b6 PD |
337 | dev_dbg(dev, "error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n", |
338 | status, cmd->cmdidx); | |
b312c590 PC |
339 | ctx->dpsm_abort = true; |
340 | return -EILSEQ; | |
341 | } | |
342 | ||
343 | if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) { | |
efd77dbc | 344 | cmd->response[0] = readl(plat->base + SDMMC_RESP1); |
b312c590 | 345 | if (cmd->resp_type & MMC_RSP_136) { |
efd77dbc PD |
346 | cmd->response[1] = readl(plat->base + SDMMC_RESP2); |
347 | cmd->response[2] = readl(plat->base + SDMMC_RESP3); | |
348 | cmd->response[3] = readl(plat->base + SDMMC_RESP4); | |
b312c590 | 349 | } |
c406a474 CK |
350 | |
351 | /* Wait for BUSYD0END flag if busy status is detected */ | |
352 | if (cmd->resp_type & MMC_RSP_BUSY && | |
353 | status & SDMMC_STA_BUSYD0) { | |
354 | mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END; | |
355 | ||
356 | /* Polling status register */ | |
efd77dbc | 357 | ret = readl_poll_timeout(plat->base + SDMMC_STA, |
c406a474 CK |
358 | status, status & mask, |
359 | SDMMC_BUSYD0END_TIMEOUT_US); | |
360 | ||
361 | if (ret < 0) { | |
4dbaa1b6 | 362 | dev_dbg(dev, "timeout reading SDMMC_STA\n"); |
c406a474 CK |
363 | ctx->dpsm_abort = true; |
364 | return ret; | |
365 | } | |
366 | ||
367 | if (status & SDMMC_STA_DTIMEOUT) { | |
4dbaa1b6 PD |
368 | dev_dbg(dev, |
369 | "error SDMMC_STA_DTIMEOUT (0x%x)\n", | |
370 | status); | |
c406a474 CK |
371 | ctx->dpsm_abort = true; |
372 | return -ETIMEDOUT; | |
373 | } | |
374 | } | |
b312c590 PC |
375 | } |
376 | ||
377 | return 0; | |
378 | } | |
379 | ||
4dbaa1b6 | 380 | static int stm32_sdmmc2_end_data(struct udevice *dev, |
b312c590 PC |
381 | struct mmc_cmd *cmd, |
382 | struct mmc_data *data, | |
383 | struct stm32_sdmmc2_ctx *ctx) | |
384 | { | |
efd77dbc | 385 | struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); |
b312c590 PC |
386 | u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT | |
387 | SDMMC_STA_IDMATE | SDMMC_STA_DATAEND; | |
388 | u32 status; | |
389 | ||
390 | if (data->flags & MMC_DATA_READ) | |
391 | mask |= SDMMC_STA_RXOVERR; | |
392 | else | |
393 | mask |= SDMMC_STA_TXUNDERR; | |
394 | ||
efd77dbc | 395 | status = readl(plat->base + SDMMC_STA); |
b312c590 | 396 | while (!(status & mask)) |
efd77dbc | 397 | status = readl(plat->base + SDMMC_STA); |
b312c590 PC |
398 | |
399 | /* | |
400 | * Need invalidate the dcache again to avoid any | |
401 | * cache-refill during the DMA operations (pre-fetching) | |
402 | */ | |
403 | if (data->flags & MMC_DATA_READ) | |
404 | invalidate_dcache_range(ctx->cache_start, ctx->cache_end); | |
405 | ||
406 | if (status & SDMMC_STA_DCRCFAIL) { | |
4dbaa1b6 PD |
407 | dev_dbg(dev, "error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n", |
408 | status, cmd->cmdidx); | |
efd77dbc | 409 | if (readl(plat->base + SDMMC_DCOUNT)) |
b312c590 PC |
410 | ctx->dpsm_abort = true; |
411 | return -EILSEQ; | |
412 | } | |
413 | ||
414 | if (status & SDMMC_STA_DTIMEOUT) { | |
4dbaa1b6 PD |
415 | dev_dbg(dev, "error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n", |
416 | status, cmd->cmdidx); | |
b312c590 PC |
417 | ctx->dpsm_abort = true; |
418 | return -ETIMEDOUT; | |
419 | } | |
420 | ||
421 | if (status & SDMMC_STA_TXUNDERR) { | |
4dbaa1b6 PD |
422 | dev_dbg(dev, "error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n", |
423 | status, cmd->cmdidx); | |
b312c590 PC |
424 | ctx->dpsm_abort = true; |
425 | return -EIO; | |
426 | } | |
427 | ||
428 | if (status & SDMMC_STA_RXOVERR) { | |
4dbaa1b6 PD |
429 | dev_dbg(dev, "error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n", |
430 | status, cmd->cmdidx); | |
b312c590 PC |
431 | ctx->dpsm_abort = true; |
432 | return -EIO; | |
433 | } | |
434 | ||
435 | if (status & SDMMC_STA_IDMATE) { | |
4dbaa1b6 PD |
436 | dev_dbg(dev, "error SDMMC_STA_IDMATE (0x%x) for cmd %d\n", |
437 | status, cmd->cmdidx); | |
b312c590 PC |
438 | ctx->dpsm_abort = true; |
439 | return -EIO; | |
440 | } | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
445 | static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, | |
446 | struct mmc_data *data) | |
447 | { | |
efd77dbc | 448 | struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); |
b312c590 PC |
449 | struct stm32_sdmmc2_ctx ctx; |
450 | u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0; | |
451 | int ret, retry = 3; | |
452 | ||
29caf930 | 453 | schedule(); |
48ac723a | 454 | |
b312c590 PC |
455 | retry_cmd: |
456 | ctx.data_length = 0; | |
457 | ctx.dpsm_abort = false; | |
458 | ||
459 | if (data) { | |
460 | ctx.data_length = data->blocks * data->blocksize; | |
4dbaa1b6 | 461 | stm32_sdmmc2_start_data(dev, data, &ctx); |
b312c590 PC |
462 | } |
463 | ||
4dbaa1b6 | 464 | stm32_sdmmc2_start_cmd(dev, cmd, cmdat, &ctx); |
b312c590 | 465 | |
e725682d PC |
466 | dev_dbg(dev, "send cmd %d data: 0x%x @ 0x%p\n", |
467 | cmd->cmdidx, data ? ctx.data_length : 0, data); | |
b312c590 | 468 | |
4dbaa1b6 | 469 | ret = stm32_sdmmc2_end_cmd(dev, cmd, &ctx); |
b312c590 PC |
470 | |
471 | if (data && !ret) | |
4dbaa1b6 | 472 | ret = stm32_sdmmc2_end_data(dev, cmd, data, &ctx); |
b312c590 PC |
473 | |
474 | /* Clear flags */ | |
efd77dbc | 475 | writel(SDMMC_ICR_STATIC_FLAGS, plat->base + SDMMC_ICR); |
b312c590 | 476 | if (data) |
efd77dbc | 477 | writel(0x0, plat->base + SDMMC_IDMACTRL); |
b312c590 PC |
478 | |
479 | /* | |
480 | * To stop Data Path State Machine, a stop_transmission command | |
481 | * shall be send on cmd or data errors. | |
482 | */ | |
483 | if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) { | |
484 | struct mmc_cmd stop_cmd; | |
485 | ||
486 | stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; | |
487 | stop_cmd.cmdarg = 0; | |
488 | stop_cmd.resp_type = MMC_RSP_R1b; | |
489 | ||
4dbaa1b6 | 490 | dev_dbg(dev, "send STOP command to abort dpsm treatments\n"); |
b312c590 | 491 | |
c406a474 CK |
492 | ctx.data_length = 0; |
493 | ||
4dbaa1b6 | 494 | stm32_sdmmc2_start_cmd(dev, &stop_cmd, |
c406a474 | 495 | SDMMC_CMD_CMDSTOP, &ctx); |
4dbaa1b6 | 496 | stm32_sdmmc2_end_cmd(dev, &stop_cmd, &ctx); |
b312c590 | 497 | |
efd77dbc | 498 | writel(SDMMC_ICR_STATIC_FLAGS, plat->base + SDMMC_ICR); |
b312c590 PC |
499 | } |
500 | ||
501 | if ((ret != -ETIMEDOUT) && (ret != 0) && retry) { | |
4dbaa1b6 | 502 | dev_err(dev, "cmd %d failed, retrying ...\n", cmd->cmdidx); |
b312c590 PC |
503 | retry--; |
504 | goto retry_cmd; | |
505 | } | |
506 | ||
4dbaa1b6 | 507 | dev_dbg(dev, "end for CMD %d, ret = %d\n", cmd->cmdidx, ret); |
b312c590 PC |
508 | |
509 | return ret; | |
510 | } | |
511 | ||
7d118161 PD |
512 | /* |
513 | * Reset the SDMMC with the RCC.SDMMCxRST register bit. | |
514 | * This will reset the SDMMC to the reset state and the CPSM and DPSM | |
515 | * to the Idle state. SDMMC is disabled, Signals Hiz. | |
516 | */ | |
efd77dbc | 517 | static void stm32_sdmmc2_reset(struct stm32_sdmmc2_plat *plat) |
b312c590 | 518 | { |
efd77dbc | 519 | if (reset_valid(&plat->reset_ctl)) { |
79bdcd88 | 520 | /* Reset */ |
efd77dbc | 521 | reset_assert(&plat->reset_ctl); |
79bdcd88 | 522 | udelay(2); |
efd77dbc | 523 | reset_deassert(&plat->reset_ctl); |
79bdcd88 | 524 | } |
b312c590 | 525 | |
7d118161 | 526 | /* init the needed SDMMC register after reset */ |
efd77dbc | 527 | writel(plat->pwr_reg_msk, plat->base + SDMMC_POWER); |
7d118161 PD |
528 | } |
529 | ||
530 | /* | |
531 | * Set the SDMMC in power-cycle state. | |
532 | * This will make that the SDMMC_D[7:0], | |
533 | * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being | |
534 | * supplied through the signal lines. | |
535 | */ | |
efd77dbc | 536 | static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_plat *plat) |
7d118161 | 537 | { |
efd77dbc | 538 | if ((readl(plat->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) == |
7d118161 PD |
539 | SDMMC_POWER_PWRCTRL_CYCLE) |
540 | return; | |
b312c590 | 541 | |
efd77dbc | 542 | stm32_sdmmc2_reset(plat); |
7d118161 PD |
543 | } |
544 | ||
545 | /* | |
546 | * set the SDMMC state Power-on: the card is clocked | |
547 | * manage the SDMMC state control: | |
548 | * Reset => Power-Cycle => Power-Off => Power | |
549 | * PWRCTRL=10 PWCTRL=00 PWCTRL=11 | |
550 | */ | |
efd77dbc | 551 | static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_plat *plat) |
7d118161 PD |
552 | { |
553 | u32 pwrctrl = | |
efd77dbc | 554 | readl(plat->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK; |
7d118161 PD |
555 | |
556 | if (pwrctrl == SDMMC_POWER_PWRCTRL_ON) | |
557 | return; | |
558 | ||
559 | /* warning: same PWRCTRL value after reset and for power-off state | |
560 | * it is the reset state here = the only managed by the driver | |
561 | */ | |
562 | if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) { | |
efd77dbc PD |
563 | writel(SDMMC_POWER_PWRCTRL_CYCLE | plat->pwr_reg_msk, |
564 | plat->base + SDMMC_POWER); | |
7d118161 | 565 | } |
b312c590 PC |
566 | |
567 | /* | |
7d118161 PD |
568 | * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE |
569 | * switch to Power-Off state: SDMCC disable, signals drive 1 | |
b312c590 | 570 | */ |
efd77dbc PD |
571 | writel(SDMMC_POWER_PWRCTRL_OFF | plat->pwr_reg_msk, |
572 | plat->base + SDMMC_POWER); | |
7d118161 PD |
573 | |
574 | /* After the 1ms delay set the SDMMC to power-on */ | |
575 | mdelay(1); | |
efd77dbc PD |
576 | writel(SDMMC_POWER_PWRCTRL_ON | plat->pwr_reg_msk, |
577 | plat->base + SDMMC_POWER); | |
7d118161 PD |
578 | |
579 | /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */ | |
359c176d YG |
580 | |
581 | #if CONFIG_IS_ENABLED(DM_REGULATOR) | |
582 | if (plat->mmc.vqmmc_supply && !plat->vqmmc_enabled) { | |
583 | if (regulator_set_enable_if_allowed(plat->mmc.vqmmc_supply, true)) | |
584 | dev_dbg(plat->mmc.dev, "failed to enable vqmmc-supply\n"); | |
585 | else | |
586 | plat->vqmmc_enabled = true; | |
587 | } | |
588 | #endif | |
b312c590 PC |
589 | } |
590 | ||
591 | #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1) | |
592 | static int stm32_sdmmc2_set_ios(struct udevice *dev) | |
593 | { | |
594 | struct mmc *mmc = mmc_get_mmc_dev(dev); | |
efd77dbc | 595 | struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); |
b312c590 | 596 | u32 desired = mmc->clock; |
efd77dbc | 597 | u32 sys_clock = clk_get_rate(&plat->clk); |
b312c590 PC |
598 | u32 clk = 0; |
599 | ||
4dbaa1b6 PD |
600 | dev_dbg(dev, "bus_with = %d, clock = %d\n", |
601 | mmc->bus_width, mmc->clock); | |
b312c590 | 602 | |
7d118161 | 603 | if (mmc->clk_disable) |
efd77dbc | 604 | stm32_sdmmc2_pwrcycle(plat); |
7d118161 | 605 | else |
efd77dbc | 606 | stm32_sdmmc2_pwron(plat); |
b312c590 PC |
607 | |
608 | /* | |
609 | * clk_div = 0 => command and data generated on SDMMCCLK falling edge | |
610 | * clk_div > 0 and NEGEDGE = 0 => command and data generated on | |
611 | * SDMMCCLK rising edge | |
612 | * clk_div > 0 and NEGEDGE = 1 => command and data generated on | |
613 | * SDMMCCLK falling edge | |
614 | */ | |
be187298 | 615 | if (desired && (sys_clock > desired || mmc->ddr_mode || |
efd77dbc | 616 | IS_RISING_EDGE(plat->clk_reg_msk))) { |
b312c590 PC |
617 | clk = DIV_ROUND_UP(sys_clock, 2 * desired); |
618 | if (clk > SDMMC_CLKCR_CLKDIV_MAX) | |
619 | clk = SDMMC_CLKCR_CLKDIV_MAX; | |
620 | } | |
621 | ||
be187298 YG |
622 | if (mmc->ddr_mode) |
623 | clk |= SDMMC_CLKCR_DDR; | |
624 | ||
b312c590 PC |
625 | if (mmc->bus_width == 4) |
626 | clk |= SDMMC_CLKCR_WIDBUS_4; | |
627 | if (mmc->bus_width == 8) | |
628 | clk |= SDMMC_CLKCR_WIDBUS_8; | |
629 | ||
efd77dbc PD |
630 | writel(clk | plat->clk_reg_msk | SDMMC_CLKCR_HWFC_EN, |
631 | plat->base + SDMMC_CLKCR); | |
b312c590 PC |
632 | |
633 | return 0; | |
634 | } | |
635 | ||
636 | static int stm32_sdmmc2_getcd(struct udevice *dev) | |
637 | { | |
efd77dbc | 638 | struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); |
b312c590 | 639 | |
4dbaa1b6 | 640 | dev_dbg(dev, "%s called\n", __func__); |
b312c590 | 641 | |
efd77dbc PD |
642 | if (dm_gpio_is_valid(&plat->cd_gpio)) |
643 | return dm_gpio_get_value(&plat->cd_gpio); | |
b312c590 PC |
644 | |
645 | return 1; | |
646 | } | |
647 | ||
a8ef8b22 YG |
648 | static int stm32_sdmmc2_host_power_cycle(struct udevice *dev) |
649 | { | |
efd77dbc | 650 | struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); |
a8ef8b22 | 651 | |
efd77dbc PD |
652 | writel(SDMMC_POWER_PWRCTRL_CYCLE | plat->pwr_reg_msk, |
653 | plat->base + SDMMC_POWER); | |
a8ef8b22 YG |
654 | |
655 | return 0; | |
656 | } | |
657 | ||
b312c590 PC |
658 | static const struct dm_mmc_ops stm32_sdmmc2_ops = { |
659 | .send_cmd = stm32_sdmmc2_send_cmd, | |
660 | .set_ios = stm32_sdmmc2_set_ios, | |
661 | .get_cd = stm32_sdmmc2_getcd, | |
a8ef8b22 | 662 | .host_power_cycle = stm32_sdmmc2_host_power_cycle, |
b312c590 PC |
663 | }; |
664 | ||
cb8edb99 PD |
665 | static int stm32_sdmmc2_of_to_plat(struct udevice *dev) |
666 | { | |
667 | struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); | |
668 | struct mmc_config *cfg = &plat->cfg; | |
669 | int ret; | |
670 | ||
671 | plat->base = dev_read_addr(dev); | |
672 | if (plat->base == FDT_ADDR_T_NONE) | |
673 | return -EINVAL; | |
674 | ||
675 | if (dev_read_bool(dev, "st,neg-edge")) | |
676 | plat->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE; | |
677 | if (dev_read_bool(dev, "st,sig-dir")) | |
678 | plat->pwr_reg_msk |= SDMMC_POWER_DIRPOL; | |
679 | if (dev_read_bool(dev, "st,use-ckin")) | |
680 | plat->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN; | |
681 | ||
682 | cfg->f_min = 400000; | |
683 | cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; | |
684 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; | |
685 | cfg->name = "STM32 SD/MMC"; | |
686 | cfg->host_caps = 0; | |
687 | cfg->f_max = 52000000; | |
688 | ret = mmc_of_parse(dev, cfg); | |
689 | if (ret) | |
690 | return ret; | |
691 | ||
27fbce43 YG |
692 | cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES); |
693 | ||
cb8edb99 PD |
694 | ret = clk_get_by_index(dev, 0, &plat->clk); |
695 | if (ret) | |
696 | return ret; | |
697 | ||
698 | ret = reset_get_by_index(dev, 0, &plat->reset_ctl); | |
699 | if (ret) | |
700 | dev_dbg(dev, "No reset provided\n"); | |
701 | ||
702 | gpio_request_by_name(dev, "cd-gpios", 0, &plat->cd_gpio, | |
703 | GPIOD_IS_IN); | |
704 | ||
705 | return 0; | |
706 | } | |
707 | ||
8e5266ee MV |
708 | static int stm32_sdmmc2_probe_level_translator(struct udevice *dev) |
709 | { | |
efd77dbc | 710 | struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); |
8e5266ee MV |
711 | struct gpio_desc cmd_gpio; |
712 | struct gpio_desc ck_gpio; | |
713 | struct gpio_desc ckin_gpio; | |
714 | int clk_hi, clk_lo, ret; | |
715 | ||
8e5266ee MV |
716 | ret = gpio_request_by_name(dev, "st,cmd-gpios", 0, &cmd_gpio, |
717 | GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); | |
718 | if (ret) | |
719 | goto exit_cmd; | |
720 | ||
721 | ret = gpio_request_by_name(dev, "st,ck-gpios", 0, &ck_gpio, | |
722 | GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); | |
723 | if (ret) | |
724 | goto exit_ck; | |
725 | ||
726 | ret = gpio_request_by_name(dev, "st,ckin-gpios", 0, &ckin_gpio, | |
727 | GPIOD_IS_IN); | |
728 | if (ret) | |
729 | goto exit_ckin; | |
730 | ||
731 | /* All GPIOs are valid, test whether level translator works */ | |
732 | ||
733 | /* Sample CKIN */ | |
734 | clk_hi = !!dm_gpio_get_value(&ckin_gpio); | |
735 | ||
736 | /* Set CK low */ | |
737 | dm_gpio_set_value(&ck_gpio, 0); | |
738 | ||
739 | /* Sample CKIN */ | |
740 | clk_lo = !!dm_gpio_get_value(&ckin_gpio); | |
741 | ||
742 | /* Tristate all */ | |
743 | dm_gpio_set_dir_flags(&cmd_gpio, GPIOD_IS_IN); | |
744 | dm_gpio_set_dir_flags(&ck_gpio, GPIOD_IS_IN); | |
745 | ||
746 | /* Level translator is present if CK signal is propagated to CKIN */ | |
747 | if (!clk_hi || clk_lo) | |
efd77dbc | 748 | plat->clk_reg_msk &= ~SDMMC_CLKCR_SELCLKRX_CKIN; |
8e5266ee MV |
749 | |
750 | dm_gpio_free(dev, &ckin_gpio); | |
751 | ||
752 | exit_ckin: | |
753 | dm_gpio_free(dev, &ck_gpio); | |
754 | exit_ck: | |
755 | dm_gpio_free(dev, &cmd_gpio); | |
756 | exit_cmd: | |
757 | pinctrl_select_state(dev, "default"); | |
758 | ||
759 | return 0; | |
760 | } | |
761 | ||
b312c590 PC |
762 | static int stm32_sdmmc2_probe(struct udevice *dev) |
763 | { | |
764 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); | |
c69cda25 | 765 | struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); |
b312c590 PC |
766 | int ret; |
767 | ||
efd77dbc | 768 | ret = clk_enable(&plat->clk); |
c9309f40 | 769 | if (ret) |
cb8edb99 | 770 | return ret; |
b312c590 PC |
771 | |
772 | upriv->mmc = &plat->mmc; | |
773 | ||
cb8edb99 PD |
774 | if (plat->clk_reg_msk & SDMMC_CLKCR_SELCLKRX_CKIN) |
775 | stm32_sdmmc2_probe_level_translator(dev); | |
776 | ||
7d118161 | 777 | /* SDMMC init */ |
efd77dbc | 778 | stm32_sdmmc2_reset(plat); |
b312c590 | 779 | |
cb8edb99 | 780 | return 0; |
b312c590 PC |
781 | } |
782 | ||
5f1e6b63 | 783 | static int stm32_sdmmc2_bind(struct udevice *dev) |
b312c590 | 784 | { |
c69cda25 | 785 | struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); |
b312c590 PC |
786 | |
787 | return mmc_bind(dev, &plat->mmc, &plat->cfg); | |
788 | } | |
789 | ||
790 | static const struct udevice_id stm32_sdmmc2_ids[] = { | |
791 | { .compatible = "st,stm32-sdmmc2" }, | |
f3901e80 | 792 | { .compatible = "st,stm32mp25-sdmmc2" }, |
b312c590 PC |
793 | { } |
794 | }; | |
795 | ||
796 | U_BOOT_DRIVER(stm32_sdmmc2) = { | |
797 | .name = "stm32_sdmmc2", | |
798 | .id = UCLASS_MMC, | |
799 | .of_match = stm32_sdmmc2_ids, | |
800 | .ops = &stm32_sdmmc2_ops, | |
801 | .probe = stm32_sdmmc2_probe, | |
5f1e6b63 | 802 | .bind = stm32_sdmmc2_bind, |
cb8edb99 | 803 | .of_to_plat = stm32_sdmmc2_of_to_plat, |
caa4daa2 | 804 | .plat_auto = sizeof(struct stm32_sdmmc2_plat), |
b312c590 | 805 | }; |