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Commit | Line | Data |
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5653fc33 | 1 | /* |
bf9e3b38 | 2 | * (C) Copyright 2002-2004 |
5653fc33 WD |
3 | * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com |
4 | * | |
5 | * Copyright (C) 2003 Arabella Software Ltd. | |
6 | * Yuli Barcohen <yuli@arabellasw.com> | |
5653fc33 | 7 | * |
bf9e3b38 WD |
8 | * Copyright (C) 2004 |
9 | * Ed Okerson | |
260421a2 SR |
10 | * |
11 | * Copyright (C) 2006 | |
12 | * Tolunay Orkun <listmember@orkun.us> | |
bf9e3b38 | 13 | * |
1a459660 | 14 | * SPDX-License-Identifier: GPL-2.0+ |
5653fc33 WD |
15 | */ |
16 | ||
17 | /* The DEBUG define must be before common to enable debugging */ | |
2d1a537d WD |
18 | /* #define DEBUG */ |
19 | ||
5653fc33 | 20 | #include <common.h> |
24b852a7 | 21 | #include <console.h> |
f1056910 TC |
22 | #include <dm.h> |
23 | #include <errno.h> | |
24 | #include <fdt_support.h> | |
5653fc33 | 25 | #include <asm/processor.h> |
3a197b2f | 26 | #include <asm/io.h> |
4c0d4c3b | 27 | #include <asm/byteorder.h> |
aedadf10 | 28 | #include <asm/unaligned.h> |
2a8af187 | 29 | #include <environment.h> |
fa36ae79 | 30 | #include <mtd/cfi_flash.h> |
a9f5faba | 31 | #include <watchdog.h> |
028ab6b5 | 32 | |
5653fc33 | 33 | /* |
7e5b9b47 HS |
34 | * This file implements a Common Flash Interface (CFI) driver for |
35 | * U-Boot. | |
36 | * | |
37 | * The width of the port and the width of the chips are determined at | |
38 | * initialization. These widths are used to calculate the address for | |
39 | * access CFI data structures. | |
5653fc33 WD |
40 | * |
41 | * References | |
42 | * JEDEC Standard JESD68 - Common Flash Interface (CFI) | |
43 | * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes | |
44 | * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets | |
45 | * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet | |
260421a2 SR |
46 | * AMD CFI Specification, Release 2.0 December 1, 2001 |
47 | * AMD/Spansion Application Note: Migration from Single-byte to Three-byte | |
48 | * Device IDs, Publication Number 25538 Revision A, November 8, 2001 | |
5653fc33 | 49 | * |
6d0f6bcf | 50 | * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between |
d0b6e140 | 51 | * reading and writing ... (yes there is such a Hardware). |
5653fc33 WD |
52 | */ |
53 | ||
f1056910 TC |
54 | DECLARE_GLOBAL_DATA_PTR; |
55 | ||
7e5b9b47 | 56 | static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; |
4ffeab2c | 57 | #ifdef CONFIG_FLASH_CFI_MTD |
6ea808ef | 58 | static uint flash_verbose = 1; |
4ffeab2c MF |
59 | #else |
60 | #define flash_verbose 1 | |
61 | #endif | |
92eb729b | 62 | |
2a112b23 WD |
63 | flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ |
64 | ||
79b4cda0 SR |
65 | /* |
66 | * Check if chip width is defined. If not, start detecting with 8bit. | |
67 | */ | |
6d0f6bcf JCPV |
68 | #ifndef CONFIG_SYS_FLASH_CFI_WIDTH |
69 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT | |
79b4cda0 SR |
70 | #endif |
71 | ||
00dcb07c JH |
72 | #ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS |
73 | #define __maybe_weak __weak | |
74 | #else | |
75 | #define __maybe_weak static | |
76 | #endif | |
77 | ||
6f726f95 SR |
78 | /* |
79 | * 0xffff is an undefined value for the configuration register. When | |
80 | * this value is returned, the configuration register shall not be | |
81 | * written at all (default mode). | |
82 | */ | |
83 | static u16 cfi_flash_config_reg(int i) | |
84 | { | |
85 | #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS | |
86 | return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i]; | |
87 | #else | |
88 | return 0xffff; | |
89 | #endif | |
90 | } | |
91 | ||
ca5def3f SR |
92 | #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) |
93 | int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; | |
94 | #endif | |
95 | ||
f1056910 TC |
96 | #ifdef CONFIG_CFI_FLASH /* for driver model */ |
97 | static void cfi_flash_init_dm(void) | |
98 | { | |
99 | struct udevice *dev; | |
100 | ||
101 | cfi_flash_num_flash_banks = 0; | |
102 | /* | |
103 | * The uclass_first_device() will probe the first device and | |
104 | * uclass_next_device() will probe the rest if they exist. So | |
105 | * that cfi_flash_probe() will get called assigning the base | |
106 | * addresses that are available. | |
107 | */ | |
108 | for (uclass_first_device(UCLASS_MTD, &dev); | |
109 | dev; | |
110 | uclass_next_device(&dev)) { | |
111 | } | |
112 | } | |
113 | ||
f1056910 TC |
114 | phys_addr_t cfi_flash_bank_addr(int i) |
115 | { | |
1ec0a37e | 116 | return flash_info[i].base; |
f1056910 TC |
117 | } |
118 | #else | |
00dcb07c | 119 | __weak phys_addr_t cfi_flash_bank_addr(int i) |
b00e19cc SR |
120 | { |
121 | return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; | |
122 | } | |
f1056910 | 123 | #endif |
b00e19cc | 124 | |
00dcb07c | 125 | __weak unsigned long cfi_flash_bank_size(int i) |
ec50a8e3 IY |
126 | { |
127 | #ifdef CONFIG_SYS_FLASH_BANKS_SIZES | |
128 | return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i]; | |
129 | #else | |
130 | return 0; | |
131 | #endif | |
132 | } | |
ec50a8e3 | 133 | |
00dcb07c | 134 | __maybe_weak void flash_write8(u8 value, void *addr) |
cdbaefb5 HS |
135 | { |
136 | __raw_writeb(value, addr); | |
137 | } | |
138 | ||
00dcb07c | 139 | __maybe_weak void flash_write16(u16 value, void *addr) |
cdbaefb5 HS |
140 | { |
141 | __raw_writew(value, addr); | |
142 | } | |
143 | ||
00dcb07c | 144 | __maybe_weak void flash_write32(u32 value, void *addr) |
cdbaefb5 HS |
145 | { |
146 | __raw_writel(value, addr); | |
147 | } | |
148 | ||
00dcb07c | 149 | __maybe_weak void flash_write64(u64 value, void *addr) |
cdbaefb5 HS |
150 | { |
151 | /* No architectures currently implement __raw_writeq() */ | |
152 | *(volatile u64 *)addr = value; | |
153 | } | |
154 | ||
00dcb07c | 155 | __maybe_weak u8 flash_read8(void *addr) |
cdbaefb5 HS |
156 | { |
157 | return __raw_readb(addr); | |
158 | } | |
159 | ||
00dcb07c | 160 | __maybe_weak u16 flash_read16(void *addr) |
cdbaefb5 HS |
161 | { |
162 | return __raw_readw(addr); | |
163 | } | |
164 | ||
00dcb07c | 165 | __maybe_weak u32 flash_read32(void *addr) |
cdbaefb5 HS |
166 | { |
167 | return __raw_readl(addr); | |
168 | } | |
169 | ||
00dcb07c | 170 | __maybe_weak u64 flash_read64(void *addr) |
cdbaefb5 HS |
171 | { |
172 | /* No architectures currently implement __raw_readq() */ | |
173 | return *(volatile u64 *)addr; | |
174 | } | |
175 | ||
5653fc33 | 176 | /*----------------------------------------------------------------------- |
5653fc33 | 177 | */ |
6d0f6bcf | 178 | #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) |
236c49a1 | 179 | static flash_info_t *flash_get_info(ulong base) |
be60a902 HS |
180 | { |
181 | int i; | |
24c185cf | 182 | flash_info_t *info; |
5653fc33 | 183 | |
6d0f6bcf | 184 | for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { |
e2e273a3 | 185 | info = &flash_info[i]; |
be60a902 HS |
186 | if (info->size && info->start[0] <= base && |
187 | base <= info->start[0] + info->size - 1) | |
24c185cf | 188 | return info; |
be60a902 | 189 | } |
5653fc33 | 190 | |
24c185cf | 191 | return NULL; |
be60a902 | 192 | } |
5653fc33 WD |
193 | #endif |
194 | ||
12d30aa7 HS |
195 | unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) |
196 | { | |
197 | if (sect != (info->sector_count - 1)) | |
198 | return info->start[sect + 1] - info->start[sect]; | |
199 | else | |
200 | return info->start[0] + info->size - info->start[sect]; | |
201 | } | |
202 | ||
bf9e3b38 WD |
203 | /*----------------------------------------------------------------------- |
204 | * create an address based on the offset and the port width | |
205 | */ | |
12d30aa7 | 206 | static inline void * |
ca2b07a8 | 207 | flash_map(flash_info_t *info, flash_sect_t sect, uint offset) |
bf9e3b38 | 208 | { |
e303be2d | 209 | unsigned int byte_offset = offset * info->portwidth; |
12d30aa7 | 210 | |
e303be2d | 211 | return (void *)(info->start[sect] + byte_offset); |
12d30aa7 HS |
212 | } |
213 | ||
214 | static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, | |
215 | unsigned int offset, void *addr) | |
216 | { | |
bf9e3b38 WD |
217 | } |
218 | ||
be60a902 HS |
219 | /*----------------------------------------------------------------------- |
220 | * make a proper sized command based on the port and chip widths | |
221 | */ | |
7288f972 | 222 | static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf) |
be60a902 HS |
223 | { |
224 | int i; | |
93c56f21 VL |
225 | int cword_offset; |
226 | int cp_offset; | |
6d0f6bcf | 227 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
340ccb26 SS |
228 | u32 cmd_le = cpu_to_le32(cmd); |
229 | #endif | |
93c56f21 | 230 | uchar val; |
be60a902 HS |
231 | uchar *cp = (uchar *) cmdbuf; |
232 | ||
b168386b | 233 | for (i = info->portwidth; i > 0; i--) { |
640f4e35 | 234 | cword_offset = (info->portwidth - i) % info->chipwidth; |
6d0f6bcf | 235 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
93c56f21 | 236 | cp_offset = info->portwidth - i; |
db91bb24 | 237 | val = *((uchar *)&cmd_le + cword_offset); |
be60a902 | 238 | #else |
93c56f21 | 239 | cp_offset = i - 1; |
db91bb24 | 240 | val = *((uchar *)&cmd + sizeof(u32) - cword_offset - 1); |
be60a902 | 241 | #endif |
7288f972 | 242 | cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val; |
93c56f21 | 243 | } |
be60a902 HS |
244 | } |
245 | ||
5653fc33 | 246 | #ifdef DEBUG |
bf9e3b38 WD |
247 | /*----------------------------------------------------------------------- |
248 | * Debug support | |
249 | */ | |
188a5565 | 250 | static void print_longlong(char *str, unsigned long long data) |
5653fc33 WD |
251 | { |
252 | int i; | |
253 | char *cp; | |
bf9e3b38 | 254 | |
640f4e35 | 255 | cp = (char *)&data; |
bf9e3b38 | 256 | for (i = 0; i < 8; i++) |
188a5565 | 257 | sprintf(&str[i * 2], "%2.2x", *cp++); |
bf9e3b38 | 258 | } |
be60a902 | 259 | |
188a5565 | 260 | static void flash_printqry(struct cfi_qry *qry) |
bf9e3b38 | 261 | { |
e23741f4 | 262 | u8 *p = (u8 *)qry; |
bf9e3b38 WD |
263 | int x, y; |
264 | ||
e23741f4 HS |
265 | for (x = 0; x < sizeof(struct cfi_qry); x += 16) { |
266 | debug("%02x : ", x); | |
267 | for (y = 0; y < 16; y++) | |
268 | debug("%2.2x ", p[x + y]); | |
269 | debug(" "); | |
bf9e3b38 | 270 | for (y = 0; y < 16; y++) { |
e23741f4 | 271 | unsigned char c = p[x + y]; |
7223a8cb | 272 | |
e23741f4 HS |
273 | if (c >= 0x20 && c <= 0x7e) |
274 | debug("%c", c); | |
275 | else | |
276 | debug("."); | |
bf9e3b38 | 277 | } |
e23741f4 | 278 | debug("\n"); |
bf9e3b38 | 279 | } |
5653fc33 WD |
280 | } |
281 | #endif | |
282 | ||
5653fc33 WD |
283 | /*----------------------------------------------------------------------- |
284 | * read a character at a port width address | |
285 | */ | |
ca2b07a8 | 286 | static inline uchar flash_read_uchar(flash_info_t *info, uint offset) |
5653fc33 WD |
287 | { |
288 | uchar *cp; | |
12d30aa7 | 289 | uchar retval; |
bf9e3b38 | 290 | |
188a5565 | 291 | cp = flash_map(info, 0, offset); |
6d0f6bcf | 292 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
12d30aa7 | 293 | retval = flash_read8(cp); |
bf9e3b38 | 294 | #else |
12d30aa7 | 295 | retval = flash_read8(cp + info->portwidth - 1); |
bf9e3b38 | 296 | #endif |
188a5565 | 297 | flash_unmap(info, 0, offset, cp); |
12d30aa7 | 298 | return retval; |
5653fc33 WD |
299 | } |
300 | ||
90447ecb TK |
301 | /*----------------------------------------------------------------------- |
302 | * read a word at a port width address, assume 16bit bus | |
303 | */ | |
ca2b07a8 | 304 | static inline ushort flash_read_word(flash_info_t *info, uint offset) |
90447ecb TK |
305 | { |
306 | ushort *addr, retval; | |
307 | ||
188a5565 MS |
308 | addr = flash_map(info, 0, offset); |
309 | retval = flash_read16(addr); | |
310 | flash_unmap(info, 0, offset, addr); | |
90447ecb TK |
311 | return retval; |
312 | } | |
313 | ||
5653fc33 | 314 | /*----------------------------------------------------------------------- |
260421a2 | 315 | * read a long word by picking the least significant byte of each maximum |
5653fc33 WD |
316 | * port size word. Swap for ppc format. |
317 | */ | |
ca2b07a8 | 318 | static ulong flash_read_long (flash_info_t *info, flash_sect_t sect, |
3055793b | 319 | uint offset) |
5653fc33 | 320 | { |
bf9e3b38 WD |
321 | uchar *addr; |
322 | ulong retval; | |
323 | ||
324 | #ifdef DEBUG | |
325 | int x; | |
326 | #endif | |
188a5565 | 327 | addr = flash_map(info, sect, offset); |
5653fc33 | 328 | |
bf9e3b38 | 329 | #ifdef DEBUG |
188a5565 | 330 | debug("long addr is at %p info->portwidth = %d\n", addr, |
bf9e3b38 | 331 | info->portwidth); |
0412e903 | 332 | for (x = 0; x < 4 * info->portwidth; x++) |
188a5565 | 333 | debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x)); |
bf9e3b38 | 334 | #endif |
6d0f6bcf | 335 | #if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
12d30aa7 HS |
336 | retval = ((flash_read8(addr) << 16) | |
337 | (flash_read8(addr + info->portwidth) << 24) | | |
338 | (flash_read8(addr + 2 * info->portwidth)) | | |
339 | (flash_read8(addr + 3 * info->portwidth) << 8)); | |
bf9e3b38 | 340 | #else |
12d30aa7 HS |
341 | retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) | |
342 | (flash_read8(addr + info->portwidth - 1) << 16) | | |
343 | (flash_read8(addr + 4 * info->portwidth - 1) << 8) | | |
344 | (flash_read8(addr + 3 * info->portwidth - 1))); | |
bf9e3b38 | 345 | #endif |
12d30aa7 HS |
346 | flash_unmap(info, sect, offset, addr); |
347 | ||
bf9e3b38 | 348 | return retval; |
5653fc33 WD |
349 | } |
350 | ||
be60a902 HS |
351 | /* |
352 | * Write a proper sized command to the correct address | |
81b20ccc | 353 | */ |
236c49a1 MV |
354 | static void flash_write_cmd(flash_info_t *info, flash_sect_t sect, |
355 | uint offset, u32 cmd) | |
81b20ccc | 356 | { |
cdbaefb5 | 357 | void *addr; |
be60a902 | 358 | cfiword_t cword; |
81b20ccc | 359 | |
188a5565 MS |
360 | addr = flash_map(info, sect, offset); |
361 | flash_make_cmd(info, cmd, &cword); | |
be60a902 HS |
362 | switch (info->portwidth) { |
363 | case FLASH_CFI_8BIT: | |
188a5565 | 364 | debug("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd, |
622b9527 RH |
365 | cword.w8, info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
366 | flash_write8(cword.w8, addr); | |
be60a902 HS |
367 | break; |
368 | case FLASH_CFI_16BIT: | |
188a5565 | 369 | debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr, |
622b9527 | 370 | cmd, cword.w16, |
be60a902 | 371 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
622b9527 | 372 | flash_write16(cword.w16, addr); |
be60a902 HS |
373 | break; |
374 | case FLASH_CFI_32BIT: | |
188a5565 | 375 | debug("fwc addr %p cmd %x %8.8x 32bit x %d bit\n", addr, |
622b9527 | 376 | cmd, cword.w32, |
be60a902 | 377 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
622b9527 | 378 | flash_write32(cword.w32, addr); |
be60a902 HS |
379 | break; |
380 | case FLASH_CFI_64BIT: | |
381 | #ifdef DEBUG | |
382 | { | |
383 | char str[20]; | |
7e5b9b47 | 384 | |
188a5565 | 385 | print_longlong(str, cword.w64); |
be60a902 | 386 | |
188a5565 | 387 | debug("fwrite addr %p cmd %x %s 64 bit x %d bit\n", |
cdbaefb5 | 388 | addr, cmd, str, |
be60a902 | 389 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); |
81b20ccc | 390 | } |
be60a902 | 391 | #endif |
622b9527 | 392 | flash_write64(cword.w64, addr); |
be60a902 | 393 | break; |
81b20ccc | 394 | } |
be60a902 HS |
395 | |
396 | /* Ensure all the instructions are fully finished */ | |
397 | sync(); | |
12d30aa7 HS |
398 | |
399 | flash_unmap(info, sect, offset, addr); | |
81b20ccc | 400 | } |
be60a902 | 401 | |
ca2b07a8 | 402 | static void flash_unlock_seq(flash_info_t *info, flash_sect_t sect) |
81b20ccc | 403 | { |
188a5565 MS |
404 | flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START); |
405 | flash_write_cmd(info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK); | |
81b20ccc | 406 | } |
81b20ccc | 407 | |
5653fc33 WD |
408 | /*----------------------------------------------------------------------- |
409 | */ | |
ca2b07a8 | 410 | static int flash_isequal(flash_info_t *info, flash_sect_t sect, |
be60a902 | 411 | uint offset, uchar cmd) |
5653fc33 | 412 | { |
cdbaefb5 | 413 | void *addr; |
be60a902 HS |
414 | cfiword_t cword; |
415 | int retval; | |
5653fc33 | 416 | |
188a5565 MS |
417 | addr = flash_map(info, sect, offset); |
418 | flash_make_cmd(info, cmd, &cword); | |
2662b40c | 419 | |
188a5565 | 420 | debug("is= cmd %x(%c) addr %p ", cmd, cmd, addr); |
be60a902 HS |
421 | switch (info->portwidth) { |
422 | case FLASH_CFI_8BIT: | |
188a5565 | 423 | debug("is= %x %x\n", flash_read8(addr), cword.w8); |
622b9527 | 424 | retval = (flash_read8(addr) == cword.w8); |
be60a902 HS |
425 | break; |
426 | case FLASH_CFI_16BIT: | |
188a5565 | 427 | debug("is= %4.4x %4.4x\n", flash_read16(addr), cword.w16); |
622b9527 | 428 | retval = (flash_read16(addr) == cword.w16); |
be60a902 HS |
429 | break; |
430 | case FLASH_CFI_32BIT: | |
188a5565 | 431 | debug("is= %8.8x %8.8x\n", flash_read32(addr), cword.w32); |
622b9527 | 432 | retval = (flash_read32(addr) == cword.w32); |
be60a902 HS |
433 | break; |
434 | case FLASH_CFI_64BIT: | |
435 | #ifdef DEBUG | |
436 | { | |
437 | char str1[20]; | |
438 | char str2[20]; | |
81b20ccc | 439 | |
188a5565 MS |
440 | print_longlong(str1, flash_read64(addr)); |
441 | print_longlong(str2, cword.w64); | |
442 | debug("is= %s %s\n", str1, str2); | |
5653fc33 | 443 | } |
be60a902 | 444 | #endif |
622b9527 | 445 | retval = (flash_read64(addr) == cword.w64); |
be60a902 HS |
446 | break; |
447 | default: | |
448 | retval = 0; | |
449 | break; | |
450 | } | |
12d30aa7 HS |
451 | flash_unmap(info, sect, offset, addr); |
452 | ||
be60a902 HS |
453 | return retval; |
454 | } | |
79b4cda0 | 455 | |
be60a902 HS |
456 | /*----------------------------------------------------------------------- |
457 | */ | |
ca2b07a8 | 458 | static int flash_isset(flash_info_t *info, flash_sect_t sect, |
be60a902 HS |
459 | uint offset, uchar cmd) |
460 | { | |
cdbaefb5 | 461 | void *addr; |
be60a902 HS |
462 | cfiword_t cword; |
463 | int retval; | |
2662b40c | 464 | |
188a5565 MS |
465 | addr = flash_map(info, sect, offset); |
466 | flash_make_cmd(info, cmd, &cword); | |
be60a902 HS |
467 | switch (info->portwidth) { |
468 | case FLASH_CFI_8BIT: | |
622b9527 | 469 | retval = ((flash_read8(addr) & cword.w8) == cword.w8); |
be60a902 HS |
470 | break; |
471 | case FLASH_CFI_16BIT: | |
622b9527 | 472 | retval = ((flash_read16(addr) & cword.w16) == cword.w16); |
be60a902 HS |
473 | break; |
474 | case FLASH_CFI_32BIT: | |
622b9527 | 475 | retval = ((flash_read32(addr) & cword.w32) == cword.w32); |
be60a902 HS |
476 | break; |
477 | case FLASH_CFI_64BIT: | |
622b9527 | 478 | retval = ((flash_read64(addr) & cword.w64) == cword.w64); |
be60a902 HS |
479 | break; |
480 | default: | |
481 | retval = 0; | |
482 | break; | |
483 | } | |
12d30aa7 HS |
484 | flash_unmap(info, sect, offset, addr); |
485 | ||
be60a902 HS |
486 | return retval; |
487 | } | |
2662b40c | 488 | |
be60a902 HS |
489 | /*----------------------------------------------------------------------- |
490 | */ | |
ca2b07a8 | 491 | static int flash_toggle(flash_info_t *info, flash_sect_t sect, |
be60a902 HS |
492 | uint offset, uchar cmd) |
493 | { | |
5312838d | 494 | u8 *addr; |
be60a902 HS |
495 | cfiword_t cword; |
496 | int retval; | |
656658dd | 497 | |
188a5565 MS |
498 | addr = flash_map(info, sect, offset); |
499 | flash_make_cmd(info, cmd, &cword); | |
be60a902 HS |
500 | switch (info->portwidth) { |
501 | case FLASH_CFI_8BIT: | |
fb8c061e | 502 | retval = flash_read8(addr) != flash_read8(addr); |
be60a902 HS |
503 | break; |
504 | case FLASH_CFI_16BIT: | |
fb8c061e | 505 | retval = flash_read16(addr) != flash_read16(addr); |
be60a902 HS |
506 | break; |
507 | case FLASH_CFI_32BIT: | |
fb8c061e | 508 | retval = flash_read32(addr) != flash_read32(addr); |
be60a902 HS |
509 | break; |
510 | case FLASH_CFI_64BIT: | |
b168386b | 511 | retval = ((flash_read32(addr) != flash_read32(addr)) || |
640f4e35 | 512 | (flash_read32(addr + 4) != flash_read32(addr + 4))); |
be60a902 HS |
513 | break; |
514 | default: | |
515 | retval = 0; | |
516 | break; | |
517 | } | |
12d30aa7 HS |
518 | flash_unmap(info, sect, offset, addr); |
519 | ||
be60a902 | 520 | return retval; |
5653fc33 WD |
521 | } |
522 | ||
be60a902 HS |
523 | /* |
524 | * flash_is_busy - check to see if the flash is busy | |
525 | * | |
526 | * This routine checks the status of the chip and returns true if the | |
527 | * chip is busy. | |
7680c140 | 528 | */ |
ca2b07a8 | 529 | static int flash_is_busy(flash_info_t *info, flash_sect_t sect) |
7680c140 | 530 | { |
be60a902 | 531 | int retval; |
7680c140 | 532 | |
be60a902 | 533 | switch (info->vendor) { |
9c048b52 | 534 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
535 | case CFI_CMDSET_INTEL_STANDARD: |
536 | case CFI_CMDSET_INTEL_EXTENDED: | |
188a5565 | 537 | retval = !flash_isset(info, sect, 0, FLASH_STATUS_DONE); |
be60a902 HS |
538 | break; |
539 | case CFI_CMDSET_AMD_STANDARD: | |
540 | case CFI_CMDSET_AMD_EXTENDED: | |
541 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
542 | case CFI_CMDSET_AMD_LEGACY: | |
543 | #endif | |
72443c7f | 544 | if (info->sr_supported) { |
188a5565 | 545 | flash_write_cmd(info, sect, info->addr_unlock1, |
72443c7f | 546 | FLASH_CMD_READ_STATUS); |
188a5565 | 547 | retval = !flash_isset(info, sect, 0, |
72443c7f MV |
548 | FLASH_STATUS_DONE); |
549 | } else { | |
188a5565 | 550 | retval = flash_toggle(info, sect, 0, |
72443c7f MV |
551 | AMD_STATUS_TOGGLE); |
552 | } | |
553 | ||
be60a902 HS |
554 | break; |
555 | default: | |
556 | retval = 0; | |
7680c140 | 557 | } |
38d2831d | 558 | debug("%s: %d\n", __func__, retval); |
be60a902 | 559 | return retval; |
7680c140 WD |
560 | } |
561 | ||
5653fc33 | 562 | /*----------------------------------------------------------------------- |
be60a902 HS |
563 | * wait for XSR.7 to be set. Time out with an error if it does not. |
564 | * This routine does not set the flash to read-array mode. | |
5653fc33 | 565 | */ |
ca2b07a8 | 566 | static int flash_status_check(flash_info_t *info, flash_sect_t sector, |
be60a902 | 567 | ulong tout, char *prompt) |
5653fc33 | 568 | { |
be60a902 | 569 | ulong start; |
5653fc33 | 570 | |
6d0f6bcf | 571 | #if CONFIG_SYS_HZ != 1000 |
c40c94a3 RA |
572 | if ((ulong)CONFIG_SYS_HZ > 100000) |
573 | tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */ | |
574 | else | |
575 | tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); | |
be60a902 | 576 | #endif |
5653fc33 | 577 | |
be60a902 | 578 | /* Wait for command completion */ |
e110c4fe | 579 | #ifdef CONFIG_SYS_LOW_RES_TIMER |
22d6c8fa | 580 | reset_timer(); |
e110c4fe | 581 | #endif |
188a5565 | 582 | start = get_timer(0); |
a9f5faba | 583 | WATCHDOG_RESET(); |
188a5565 MS |
584 | while (flash_is_busy(info, sector)) { |
585 | if (get_timer(start) > tout) { | |
586 | printf("Flash %s timeout at address %lx data %lx\n", | |
be60a902 | 587 | prompt, info->start[sector], |
188a5565 MS |
588 | flash_read_long(info, sector, 0)); |
589 | flash_write_cmd(info, sector, 0, info->cmd_reset); | |
e303be2d | 590 | udelay(1); |
be60a902 | 591 | return ERR_TIMOUT; |
5653fc33 | 592 | } |
188a5565 | 593 | udelay(1); /* also triggers watchdog */ |
5653fc33 | 594 | } |
be60a902 HS |
595 | return ERR_OK; |
596 | } | |
5653fc33 | 597 | |
be60a902 HS |
598 | /*----------------------------------------------------------------------- |
599 | * Wait for XSR.7 to be set, if it times out print an error, otherwise | |
600 | * do a full status check. | |
601 | * | |
602 | * This routine sets the flash to read-array mode. | |
603 | */ | |
ca2b07a8 | 604 | static int flash_full_status_check(flash_info_t *info, flash_sect_t sector, |
be60a902 HS |
605 | ulong tout, char *prompt) |
606 | { | |
607 | int retcode; | |
5653fc33 | 608 | |
188a5565 | 609 | retcode = flash_status_check(info, sector, tout, prompt); |
be60a902 | 610 | switch (info->vendor) { |
9c048b52 | 611 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
612 | case CFI_CMDSET_INTEL_EXTENDED: |
613 | case CFI_CMDSET_INTEL_STANDARD: | |
4f89da49 | 614 | if (retcode == ERR_OK && |
88ecd8bf | 615 | !flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { |
be60a902 | 616 | retcode = ERR_INVAL; |
188a5565 | 617 | printf("Flash %s error at address %lx\n", prompt, |
be60a902 | 618 | info->start[sector]); |
188a5565 | 619 | if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | |
be60a902 | 620 | FLASH_STATUS_PSLBS)) { |
188a5565 MS |
621 | puts("Command Sequence Error.\n"); |
622 | } else if (flash_isset(info, sector, 0, | |
be60a902 | 623 | FLASH_STATUS_ECLBS)) { |
188a5565 | 624 | puts("Block Erase Error.\n"); |
be60a902 | 625 | retcode = ERR_NOT_ERASED; |
188a5565 | 626 | } else if (flash_isset(info, sector, 0, |
be60a902 | 627 | FLASH_STATUS_PSLBS)) { |
188a5565 | 628 | puts("Locking Error\n"); |
5653fc33 | 629 | } |
188a5565 MS |
630 | if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) { |
631 | puts("Block locked.\n"); | |
be60a902 HS |
632 | retcode = ERR_PROTECTED; |
633 | } | |
188a5565 MS |
634 | if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS)) |
635 | puts("Vpp Low Error.\n"); | |
5653fc33 | 636 | } |
188a5565 | 637 | flash_write_cmd(info, sector, 0, info->cmd_reset); |
a90b9575 | 638 | udelay(1); |
be60a902 HS |
639 | break; |
640 | default: | |
641 | break; | |
5653fc33 | 642 | } |
be60a902 | 643 | return retcode; |
5653fc33 WD |
644 | } |
645 | ||
e5720823 TC |
646 | static int use_flash_status_poll(flash_info_t *info) |
647 | { | |
648 | #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL | |
649 | if (info->vendor == CFI_CMDSET_AMD_EXTENDED || | |
650 | info->vendor == CFI_CMDSET_AMD_STANDARD) | |
651 | return 1; | |
652 | #endif | |
653 | return 0; | |
654 | } | |
655 | ||
656 | static int flash_status_poll(flash_info_t *info, void *src, void *dst, | |
657 | ulong tout, char *prompt) | |
658 | { | |
659 | #ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL | |
660 | ulong start; | |
661 | int ready; | |
662 | ||
663 | #if CONFIG_SYS_HZ != 1000 | |
664 | if ((ulong)CONFIG_SYS_HZ > 100000) | |
665 | tout *= (ulong)CONFIG_SYS_HZ / 1000; /* for a big HZ, avoid overflow */ | |
666 | else | |
667 | tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000); | |
668 | #endif | |
669 | ||
670 | /* Wait for command completion */ | |
e110c4fe | 671 | #ifdef CONFIG_SYS_LOW_RES_TIMER |
22d6c8fa | 672 | reset_timer(); |
e110c4fe | 673 | #endif |
e5720823 | 674 | start = get_timer(0); |
a9f5faba | 675 | WATCHDOG_RESET(); |
e5720823 TC |
676 | while (1) { |
677 | switch (info->portwidth) { | |
678 | case FLASH_CFI_8BIT: | |
679 | ready = flash_read8(dst) == flash_read8(src); | |
680 | break; | |
681 | case FLASH_CFI_16BIT: | |
682 | ready = flash_read16(dst) == flash_read16(src); | |
683 | break; | |
684 | case FLASH_CFI_32BIT: | |
685 | ready = flash_read32(dst) == flash_read32(src); | |
686 | break; | |
687 | case FLASH_CFI_64BIT: | |
688 | ready = flash_read64(dst) == flash_read64(src); | |
689 | break; | |
690 | default: | |
691 | ready = 0; | |
692 | break; | |
693 | } | |
694 | if (ready) | |
695 | break; | |
696 | if (get_timer(start) > tout) { | |
697 | printf("Flash %s timeout at address %lx data %lx\n", | |
698 | prompt, (ulong)dst, (ulong)flash_read8(dst)); | |
699 | return ERR_TIMOUT; | |
700 | } | |
701 | udelay(1); /* also triggers watchdog */ | |
702 | } | |
703 | #endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */ | |
704 | return ERR_OK; | |
705 | } | |
706 | ||
5653fc33 WD |
707 | /*----------------------------------------------------------------------- |
708 | */ | |
ca2b07a8 | 709 | static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c) |
5653fc33 | 710 | { |
6d0f6bcf | 711 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
712 | unsigned short w; |
713 | unsigned int l; | |
714 | unsigned long long ll; | |
715 | #endif | |
5653fc33 | 716 | |
be60a902 HS |
717 | switch (info->portwidth) { |
718 | case FLASH_CFI_8BIT: | |
622b9527 | 719 | cword->w8 = c; |
be60a902 HS |
720 | break; |
721 | case FLASH_CFI_16BIT: | |
6d0f6bcf | 722 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
723 | w = c; |
724 | w <<= 8; | |
622b9527 | 725 | cword->w16 = (cword->w16 >> 8) | w; |
be60a902 | 726 | #else |
622b9527 | 727 | cword->w16 = (cword->w16 << 8) | c; |
81b20ccc | 728 | #endif |
be60a902 HS |
729 | break; |
730 | case FLASH_CFI_32BIT: | |
6d0f6bcf | 731 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
732 | l = c; |
733 | l <<= 24; | |
622b9527 | 734 | cword->w32 = (cword->w32 >> 8) | l; |
be60a902 | 735 | #else |
622b9527 | 736 | cword->w32 = (cword->w32 << 8) | c; |
be60a902 HS |
737 | #endif |
738 | break; | |
739 | case FLASH_CFI_64BIT: | |
6d0f6bcf | 740 | #if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA) |
be60a902 HS |
741 | ll = c; |
742 | ll <<= 56; | |
622b9527 | 743 | cword->w64 = (cword->w64 >> 8) | ll; |
be60a902 | 744 | #else |
622b9527 | 745 | cword->w64 = (cword->w64 << 8) | c; |
be60a902 HS |
746 | #endif |
747 | break; | |
260421a2 | 748 | } |
be60a902 | 749 | } |
5653fc33 | 750 | |
0f8e851e JG |
751 | /* |
752 | * Loop through the sector table starting from the previously found sector. | |
753 | * Searches forwards or backwards, dependent on the passed address. | |
be60a902 | 754 | */ |
ca2b07a8 | 755 | static flash_sect_t find_sector(flash_info_t *info, ulong addr) |
be60a902 | 756 | { |
11dc4010 | 757 | static flash_sect_t saved_sector; /* previously found sector */ |
e303be2d | 758 | static flash_info_t *saved_info; /* previously used flash bank */ |
0f8e851e JG |
759 | flash_sect_t sector = saved_sector; |
760 | ||
4f89da49 | 761 | if (info != saved_info || sector >= info->sector_count) |
e303be2d SR |
762 | sector = 0; |
763 | ||
88ecd8bf MS |
764 | while ((info->start[sector] < addr) && |
765 | (sector < info->sector_count - 1)) | |
0f8e851e JG |
766 | sector++; |
767 | while ((info->start[sector] > addr) && (sector > 0)) | |
768 | /* | |
769 | * also decrements the sector in case of an overshot | |
770 | * in the first loop | |
771 | */ | |
772 | sector--; | |
773 | ||
774 | saved_sector = sector; | |
e303be2d | 775 | saved_info = info; |
be60a902 | 776 | return sector; |
5653fc33 WD |
777 | } |
778 | ||
779 | /*----------------------------------------------------------------------- | |
5653fc33 | 780 | */ |
ca2b07a8 | 781 | static int flash_write_cfiword(flash_info_t *info, ulong dest, |
be60a902 | 782 | cfiword_t cword) |
5653fc33 | 783 | { |
09ce9921 | 784 | void *dstaddr = (void *)dest; |
be60a902 | 785 | int flag; |
a7292871 JG |
786 | flash_sect_t sect = 0; |
787 | char sect_found = 0; | |
5653fc33 | 788 | |
be60a902 HS |
789 | /* Check if Flash is (sufficiently) erased */ |
790 | switch (info->portwidth) { | |
791 | case FLASH_CFI_8BIT: | |
622b9527 | 792 | flag = ((flash_read8(dstaddr) & cword.w8) == cword.w8); |
be60a902 HS |
793 | break; |
794 | case FLASH_CFI_16BIT: | |
622b9527 | 795 | flag = ((flash_read16(dstaddr) & cword.w16) == cword.w16); |
be60a902 HS |
796 | break; |
797 | case FLASH_CFI_32BIT: | |
622b9527 | 798 | flag = ((flash_read32(dstaddr) & cword.w32) == cword.w32); |
be60a902 HS |
799 | break; |
800 | case FLASH_CFI_64BIT: | |
622b9527 | 801 | flag = ((flash_read64(dstaddr) & cword.w64) == cword.w64); |
be60a902 HS |
802 | break; |
803 | default: | |
12d30aa7 HS |
804 | flag = 0; |
805 | break; | |
5653fc33 | 806 | } |
09ce9921 | 807 | if (!flag) |
0dc80e27 | 808 | return ERR_NOT_ERASED; |
5653fc33 | 809 | |
be60a902 | 810 | /* Disable interrupts which might cause a timeout here */ |
188a5565 | 811 | flag = disable_interrupts(); |
79b4cda0 | 812 | |
be60a902 | 813 | switch (info->vendor) { |
9c048b52 | 814 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
815 | case CFI_CMDSET_INTEL_EXTENDED: |
816 | case CFI_CMDSET_INTEL_STANDARD: | |
188a5565 MS |
817 | flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS); |
818 | flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE); | |
be60a902 HS |
819 | break; |
820 | case CFI_CMDSET_AMD_EXTENDED: | |
821 | case CFI_CMDSET_AMD_STANDARD: | |
0d01f66d | 822 | sect = find_sector(info, dest); |
188a5565 MS |
823 | flash_unlock_seq(info, sect); |
824 | flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_WRITE); | |
a7292871 | 825 | sect_found = 1; |
be60a902 | 826 | break; |
b4db4a76 PYC |
827 | #ifdef CONFIG_FLASH_CFI_LEGACY |
828 | case CFI_CMDSET_AMD_LEGACY: | |
829 | sect = find_sector(info, dest); | |
188a5565 MS |
830 | flash_unlock_seq(info, 0); |
831 | flash_write_cmd(info, 0, info->addr_unlock1, AMD_CMD_WRITE); | |
b4db4a76 PYC |
832 | sect_found = 1; |
833 | break; | |
834 | #endif | |
5653fc33 WD |
835 | } |
836 | ||
be60a902 HS |
837 | switch (info->portwidth) { |
838 | case FLASH_CFI_8BIT: | |
622b9527 | 839 | flash_write8(cword.w8, dstaddr); |
be60a902 HS |
840 | break; |
841 | case FLASH_CFI_16BIT: | |
622b9527 | 842 | flash_write16(cword.w16, dstaddr); |
be60a902 HS |
843 | break; |
844 | case FLASH_CFI_32BIT: | |
622b9527 | 845 | flash_write32(cword.w32, dstaddr); |
be60a902 HS |
846 | break; |
847 | case FLASH_CFI_64BIT: | |
622b9527 | 848 | flash_write64(cword.w64, dstaddr); |
be60a902 | 849 | break; |
5653fc33 WD |
850 | } |
851 | ||
be60a902 HS |
852 | /* re-enable interrupts if necessary */ |
853 | if (flag) | |
188a5565 | 854 | enable_interrupts(); |
5653fc33 | 855 | |
a7292871 | 856 | if (!sect_found) |
188a5565 | 857 | sect = find_sector(info, dest); |
a7292871 | 858 | |
e5720823 TC |
859 | if (use_flash_status_poll(info)) |
860 | return flash_status_poll(info, &cword, dstaddr, | |
861 | info->write_tout, "write"); | |
862 | else | |
863 | return flash_full_status_check(info, sect, | |
864 | info->write_tout, "write"); | |
5653fc33 WD |
865 | } |
866 | ||
6d0f6bcf | 867 | #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
5653fc33 | 868 | |
ca2b07a8 | 869 | static int flash_write_cfibuffer(flash_info_t *info, ulong dest, uchar *cp, |
be60a902 | 870 | int len) |
5653fc33 | 871 | { |
be60a902 HS |
872 | flash_sect_t sector; |
873 | int cnt; | |
874 | int retcode; | |
5312838d MS |
875 | u8 *src = cp; |
876 | u8 *dst = (u8 *)dest; | |
877 | u8 *dst2 = dst; | |
85c344e5 | 878 | int flag = 1; |
96ef831f GL |
879 | uint offset = 0; |
880 | unsigned int shift; | |
9c048b52 | 881 | uchar write_cmd; |
cdbaefb5 | 882 | |
0dc80e27 SR |
883 | switch (info->portwidth) { |
884 | case FLASH_CFI_8BIT: | |
96ef831f | 885 | shift = 0; |
0dc80e27 SR |
886 | break; |
887 | case FLASH_CFI_16BIT: | |
96ef831f | 888 | shift = 1; |
0dc80e27 SR |
889 | break; |
890 | case FLASH_CFI_32BIT: | |
96ef831f | 891 | shift = 2; |
0dc80e27 SR |
892 | break; |
893 | case FLASH_CFI_64BIT: | |
96ef831f | 894 | shift = 3; |
0dc80e27 SR |
895 | break; |
896 | default: | |
897 | retcode = ERR_INVAL; | |
898 | goto out_unmap; | |
899 | } | |
900 | ||
96ef831f GL |
901 | cnt = len >> shift; |
902 | ||
85c344e5 | 903 | while ((cnt-- > 0) && (flag == 1)) { |
0dc80e27 SR |
904 | switch (info->portwidth) { |
905 | case FLASH_CFI_8BIT: | |
906 | flag = ((flash_read8(dst2) & flash_read8(src)) == | |
907 | flash_read8(src)); | |
908 | src += 1, dst2 += 1; | |
909 | break; | |
910 | case FLASH_CFI_16BIT: | |
911 | flag = ((flash_read16(dst2) & flash_read16(src)) == | |
912 | flash_read16(src)); | |
913 | src += 2, dst2 += 2; | |
914 | break; | |
915 | case FLASH_CFI_32BIT: | |
916 | flag = ((flash_read32(dst2) & flash_read32(src)) == | |
917 | flash_read32(src)); | |
918 | src += 4, dst2 += 4; | |
919 | break; | |
920 | case FLASH_CFI_64BIT: | |
921 | flag = ((flash_read64(dst2) & flash_read64(src)) == | |
922 | flash_read64(src)); | |
923 | src += 8, dst2 += 8; | |
924 | break; | |
925 | } | |
926 | } | |
927 | if (!flag) { | |
928 | retcode = ERR_NOT_ERASED; | |
929 | goto out_unmap; | |
930 | } | |
931 | ||
932 | src = cp; | |
188a5565 | 933 | sector = find_sector(info, dest); |
bf9e3b38 WD |
934 | |
935 | switch (info->vendor) { | |
9c048b52 | 936 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
5653fc33 WD |
937 | case CFI_CMDSET_INTEL_STANDARD: |
938 | case CFI_CMDSET_INTEL_EXTENDED: | |
9c048b52 VL |
939 | write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ? |
940 | FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER; | |
188a5565 MS |
941 | flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); |
942 | flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); | |
943 | flash_write_cmd(info, sector, 0, write_cmd); | |
944 | retcode = flash_status_check(info, sector, | |
be60a902 HS |
945 | info->buffer_write_tout, |
946 | "write to buffer"); | |
947 | if (retcode == ERR_OK) { | |
948 | /* reduce the number of loops by the width of | |
a6d18f27 MS |
949 | * the port |
950 | */ | |
96ef831f | 951 | cnt = len >> shift; |
188a5565 | 952 | flash_write_cmd(info, sector, 0, cnt - 1); |
be60a902 HS |
953 | while (cnt-- > 0) { |
954 | switch (info->portwidth) { | |
955 | case FLASH_CFI_8BIT: | |
cdbaefb5 HS |
956 | flash_write8(flash_read8(src), dst); |
957 | src += 1, dst += 1; | |
be60a902 HS |
958 | break; |
959 | case FLASH_CFI_16BIT: | |
cdbaefb5 HS |
960 | flash_write16(flash_read16(src), dst); |
961 | src += 2, dst += 2; | |
be60a902 HS |
962 | break; |
963 | case FLASH_CFI_32BIT: | |
cdbaefb5 HS |
964 | flash_write32(flash_read32(src), dst); |
965 | src += 4, dst += 4; | |
be60a902 HS |
966 | break; |
967 | case FLASH_CFI_64BIT: | |
cdbaefb5 HS |
968 | flash_write64(flash_read64(src), dst); |
969 | src += 8, dst += 8; | |
be60a902 HS |
970 | break; |
971 | default: | |
12d30aa7 HS |
972 | retcode = ERR_INVAL; |
973 | goto out_unmap; | |
be60a902 HS |
974 | } |
975 | } | |
188a5565 | 976 | flash_write_cmd(info, sector, 0, |
be60a902 | 977 | FLASH_CMD_WRITE_BUFFER_CONFIRM); |
188a5565 | 978 | retcode = flash_full_status_check( |
be60a902 HS |
979 | info, sector, info->buffer_write_tout, |
980 | "buffer write"); | |
981 | } | |
12d30aa7 HS |
982 | |
983 | break; | |
be60a902 | 984 | |
5653fc33 WD |
985 | case CFI_CMDSET_AMD_STANDARD: |
986 | case CFI_CMDSET_AMD_EXTENDED: | |
7570a0cc | 987 | flash_unlock_seq(info, sector); |
96ef831f GL |
988 | |
989 | #ifdef CONFIG_FLASH_SPANSION_S29WS_N | |
990 | offset = ((unsigned long)dst - info->start[sector]) >> shift; | |
991 | #endif | |
992 | flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER); | |
993 | cnt = len >> shift; | |
7dedefdf | 994 | flash_write_cmd(info, sector, offset, cnt - 1); |
be60a902 HS |
995 | |
996 | switch (info->portwidth) { | |
997 | case FLASH_CFI_8BIT: | |
cdbaefb5 HS |
998 | while (cnt-- > 0) { |
999 | flash_write8(flash_read8(src), dst); | |
1000 | src += 1, dst += 1; | |
1001 | } | |
be60a902 HS |
1002 | break; |
1003 | case FLASH_CFI_16BIT: | |
cdbaefb5 HS |
1004 | while (cnt-- > 0) { |
1005 | flash_write16(flash_read16(src), dst); | |
1006 | src += 2, dst += 2; | |
1007 | } | |
be60a902 HS |
1008 | break; |
1009 | case FLASH_CFI_32BIT: | |
cdbaefb5 HS |
1010 | while (cnt-- > 0) { |
1011 | flash_write32(flash_read32(src), dst); | |
1012 | src += 4, dst += 4; | |
1013 | } | |
be60a902 HS |
1014 | break; |
1015 | case FLASH_CFI_64BIT: | |
cdbaefb5 HS |
1016 | while (cnt-- > 0) { |
1017 | flash_write64(flash_read64(src), dst); | |
1018 | src += 8, dst += 8; | |
1019 | } | |
be60a902 HS |
1020 | break; |
1021 | default: | |
12d30aa7 HS |
1022 | retcode = ERR_INVAL; |
1023 | goto out_unmap; | |
be60a902 HS |
1024 | } |
1025 | ||
188a5565 | 1026 | flash_write_cmd(info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); |
e5720823 TC |
1027 | if (use_flash_status_poll(info)) |
1028 | retcode = flash_status_poll(info, src - (1 << shift), | |
1029 | dst - (1 << shift), | |
1030 | info->buffer_write_tout, | |
1031 | "buffer write"); | |
1032 | else | |
1033 | retcode = flash_full_status_check(info, sector, | |
1034 | info->buffer_write_tout, | |
1035 | "buffer write"); | |
12d30aa7 | 1036 | break; |
be60a902 | 1037 | |
5653fc33 | 1038 | default: |
188a5565 | 1039 | debug("Unknown Command Set\n"); |
12d30aa7 HS |
1040 | retcode = ERR_INVAL; |
1041 | break; | |
5653fc33 | 1042 | } |
12d30aa7 HS |
1043 | |
1044 | out_unmap: | |
12d30aa7 | 1045 | return retcode; |
5653fc33 | 1046 | } |
6d0f6bcf | 1047 | #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
be60a902 | 1048 | |
5653fc33 | 1049 | /*----------------------------------------------------------------------- |
5653fc33 | 1050 | */ |
ca2b07a8 | 1051 | int flash_erase(flash_info_t *info, int s_first, int s_last) |
5653fc33 | 1052 | { |
be60a902 HS |
1053 | int rcode = 0; |
1054 | int prot; | |
1055 | flash_sect_t sect; | |
e5720823 | 1056 | int st; |
5653fc33 | 1057 | |
be60a902 | 1058 | if (info->flash_id != FLASH_MAN_CFI) { |
188a5565 | 1059 | puts("Can't erase unknown flash type - aborted\n"); |
be60a902 HS |
1060 | return 1; |
1061 | } | |
4f89da49 | 1062 | if (s_first < 0 || s_first > s_last) { |
188a5565 | 1063 | puts("- no sectors to erase\n"); |
be60a902 HS |
1064 | return 1; |
1065 | } | |
2662b40c | 1066 | |
be60a902 | 1067 | prot = 0; |
0412e903 MS |
1068 | for (sect = s_first; sect <= s_last; ++sect) |
1069 | if (info->protect[sect]) | |
be60a902 | 1070 | prot++; |
be60a902 | 1071 | if (prot) { |
188a5565 | 1072 | printf("- Warning: %d protected sectors will not be erased!\n", |
be60a902 | 1073 | prot); |
6ea808ef | 1074 | } else if (flash_verbose) { |
188a5565 | 1075 | putc('\n'); |
be60a902 | 1076 | } |
bf9e3b38 | 1077 | |
be60a902 | 1078 | for (sect = s_first; sect <= s_last; sect++) { |
de15a06a JH |
1079 | if (ctrlc()) { |
1080 | printf("\n"); | |
1081 | return 1; | |
1082 | } | |
1083 | ||
be60a902 | 1084 | if (info->protect[sect] == 0) { /* not protected */ |
6822a647 JH |
1085 | #ifdef CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE |
1086 | int k; | |
1087 | int size; | |
1088 | int erased; | |
1089 | u32 *flash; | |
1090 | ||
1091 | /* | |
1092 | * Check if whole sector is erased | |
1093 | */ | |
1094 | size = flash_sector_size(info, sect); | |
1095 | erased = 1; | |
1096 | flash = (u32 *)info->start[sect]; | |
1097 | /* divide by 4 for longword access */ | |
1098 | size = size >> 2; | |
1099 | for (k = 0; k < size; k++) { | |
1100 | if (flash_read32(flash++) != 0xffffffff) { | |
1101 | erased = 0; | |
1102 | break; | |
1103 | } | |
1104 | } | |
1105 | if (erased) { | |
1106 | if (flash_verbose) | |
1107 | putc(','); | |
1108 | continue; | |
1109 | } | |
1110 | #endif | |
be60a902 | 1111 | switch (info->vendor) { |
9c048b52 | 1112 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
1113 | case CFI_CMDSET_INTEL_STANDARD: |
1114 | case CFI_CMDSET_INTEL_EXTENDED: | |
188a5565 | 1115 | flash_write_cmd(info, sect, 0, |
be60a902 | 1116 | FLASH_CMD_CLEAR_STATUS); |
188a5565 | 1117 | flash_write_cmd(info, sect, 0, |
be60a902 | 1118 | FLASH_CMD_BLOCK_ERASE); |
188a5565 | 1119 | flash_write_cmd(info, sect, 0, |
be60a902 HS |
1120 | FLASH_CMD_ERASE_CONFIRM); |
1121 | break; | |
1122 | case CFI_CMDSET_AMD_STANDARD: | |
1123 | case CFI_CMDSET_AMD_EXTENDED: | |
188a5565 MS |
1124 | flash_unlock_seq(info, sect); |
1125 | flash_write_cmd(info, sect, | |
be60a902 HS |
1126 | info->addr_unlock1, |
1127 | AMD_CMD_ERASE_START); | |
188a5565 MS |
1128 | flash_unlock_seq(info, sect); |
1129 | flash_write_cmd(info, sect, 0, | |
07b2c5c0 | 1130 | info->cmd_erase_sector); |
be60a902 HS |
1131 | break; |
1132 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
1133 | case CFI_CMDSET_AMD_LEGACY: | |
188a5565 MS |
1134 | flash_unlock_seq(info, 0); |
1135 | flash_write_cmd(info, 0, info->addr_unlock1, | |
be60a902 | 1136 | AMD_CMD_ERASE_START); |
188a5565 MS |
1137 | flash_unlock_seq(info, 0); |
1138 | flash_write_cmd(info, sect, 0, | |
be60a902 HS |
1139 | AMD_CMD_ERASE_SECTOR); |
1140 | break; | |
1141 | #endif | |
1142 | default: | |
9f720216 | 1143 | debug("Unknown flash vendor %d\n", |
be60a902 HS |
1144 | info->vendor); |
1145 | break; | |
bf9e3b38 | 1146 | } |
be60a902 | 1147 | |
e5720823 | 1148 | if (use_flash_status_poll(info)) { |
11dc4010 | 1149 | cfiword_t cword; |
e5720823 | 1150 | void *dest; |
7223a8cb | 1151 | |
622b9527 | 1152 | cword.w64 = 0xffffffffffffffffULL; |
e5720823 TC |
1153 | dest = flash_map(info, sect, 0); |
1154 | st = flash_status_poll(info, &cword, dest, | |
1155 | info->erase_blk_tout, "erase"); | |
1156 | flash_unmap(info, sect, 0, dest); | |
12d7fed9 | 1157 | } else { |
e5720823 TC |
1158 | st = flash_full_status_check(info, sect, |
1159 | info->erase_blk_tout, | |
1160 | "erase"); | |
12d7fed9 MS |
1161 | } |
1162 | ||
e5720823 | 1163 | if (st) |
be60a902 | 1164 | rcode = 1; |
e5720823 | 1165 | else if (flash_verbose) |
188a5565 | 1166 | putc('.'); |
5653fc33 | 1167 | } |
5653fc33 | 1168 | } |
6ea808ef PZ |
1169 | |
1170 | if (flash_verbose) | |
188a5565 | 1171 | puts(" done\n"); |
6ea808ef | 1172 | |
be60a902 | 1173 | return rcode; |
5653fc33 | 1174 | } |
bf9e3b38 | 1175 | |
70084df7 SR |
1176 | #ifdef CONFIG_SYS_FLASH_EMPTY_INFO |
1177 | static int sector_erased(flash_info_t *info, int i) | |
1178 | { | |
1179 | int k; | |
1180 | int size; | |
4d2ca9d6 | 1181 | u32 *flash; |
70084df7 SR |
1182 | |
1183 | /* | |
1184 | * Check if whole sector is erased | |
1185 | */ | |
1186 | size = flash_sector_size(info, i); | |
4d2ca9d6 | 1187 | flash = (u32 *)info->start[i]; |
70084df7 SR |
1188 | /* divide by 4 for longword access */ |
1189 | size = size >> 2; | |
1190 | ||
1191 | for (k = 0; k < size; k++) { | |
4d2ca9d6 | 1192 | if (flash_read32(flash++) != 0xffffffff) |
70084df7 SR |
1193 | return 0; /* not erased */ |
1194 | } | |
1195 | ||
1196 | return 1; /* erased */ | |
1197 | } | |
1198 | #endif /* CONFIG_SYS_FLASH_EMPTY_INFO */ | |
1199 | ||
ca2b07a8 | 1200 | void flash_print_info(flash_info_t *info) |
5653fc33 | 1201 | { |
be60a902 | 1202 | int i; |
4d13cbad | 1203 | |
be60a902 | 1204 | if (info->flash_id != FLASH_MAN_CFI) { |
188a5565 | 1205 | puts("missing or unknown FLASH type\n"); |
be60a902 HS |
1206 | return; |
1207 | } | |
1208 | ||
188a5565 | 1209 | printf("%s flash (%d x %d)", |
be60a902 HS |
1210 | info->name, |
1211 | (info->portwidth << 3), (info->chipwidth << 3)); | |
640f4e35 | 1212 | if (info->size < 1024 * 1024) |
188a5565 | 1213 | printf(" Size: %ld kB in %d Sectors\n", |
be60a902 HS |
1214 | info->size >> 10, info->sector_count); |
1215 | else | |
188a5565 | 1216 | printf(" Size: %ld MB in %d Sectors\n", |
be60a902 | 1217 | info->size >> 20, info->sector_count); |
188a5565 | 1218 | printf(" "); |
be60a902 | 1219 | switch (info->vendor) { |
dde0913b MS |
1220 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
1221 | printf("Intel Prog Regions"); | |
1222 | break; | |
1223 | case CFI_CMDSET_INTEL_STANDARD: | |
1224 | printf("Intel Standard"); | |
1225 | break; | |
1226 | case CFI_CMDSET_INTEL_EXTENDED: | |
1227 | printf("Intel Extended"); | |
1228 | break; | |
1229 | case CFI_CMDSET_AMD_STANDARD: | |
1230 | printf("AMD Standard"); | |
1231 | break; | |
1232 | case CFI_CMDSET_AMD_EXTENDED: | |
1233 | printf("AMD Extended"); | |
1234 | break; | |
be60a902 | 1235 | #ifdef CONFIG_FLASH_CFI_LEGACY |
dde0913b MS |
1236 | case CFI_CMDSET_AMD_LEGACY: |
1237 | printf("AMD Legacy"); | |
1238 | break; | |
4d13cbad | 1239 | #endif |
dde0913b MS |
1240 | default: |
1241 | printf("Unknown (%d)", info->vendor); | |
1242 | break; | |
be60a902 | 1243 | } |
188a5565 | 1244 | printf(" command set, Manufacturer ID: 0x%02X, Device ID: 0x", |
d77c7ac4 | 1245 | info->manufacturer_id); |
188a5565 | 1246 | printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", |
d77c7ac4 | 1247 | info->device_id); |
5b448adb HS |
1248 | if ((info->device_id & 0xff) == 0x7E) { |
1249 | printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X", | |
1250 | info->device_id2); | |
be60a902 | 1251 | } |
4f89da49 | 1252 | if (info->vendor == CFI_CMDSET_AMD_STANDARD && info->legacy_unlock) |
d2af028d | 1253 | printf("\n Advanced Sector Protection (PPB) enabled"); |
188a5565 | 1254 | printf("\n Erase timeout: %ld ms, write timeout: %ld ms\n", |
be60a902 HS |
1255 | info->erase_blk_tout, |
1256 | info->write_tout); | |
1257 | if (info->buffer_size > 1) { | |
188a5565 | 1258 | printf(" Buffer write timeout: %ld ms, " |
be60a902 HS |
1259 | "buffer size: %d bytes\n", |
1260 | info->buffer_write_tout, | |
1261 | info->buffer_size); | |
5653fc33 | 1262 | } |
5653fc33 | 1263 | |
188a5565 | 1264 | puts("\n Sector Start Addresses:"); |
be60a902 | 1265 | for (i = 0; i < info->sector_count; ++i) { |
2e97394a | 1266 | if (ctrlc()) |
70084df7 | 1267 | break; |
be60a902 | 1268 | if ((i % 5) == 0) |
70084df7 | 1269 | putc('\n'); |
6d0f6bcf | 1270 | #ifdef CONFIG_SYS_FLASH_EMPTY_INFO |
be60a902 | 1271 | /* print empty and read-only info */ |
188a5565 | 1272 | printf(" %08lX %c %s ", |
be60a902 | 1273 | info->start[i], |
70084df7 | 1274 | sector_erased(info, i) ? 'E' : ' ', |
be60a902 | 1275 | info->protect[i] ? "RO" : " "); |
6d0f6bcf | 1276 | #else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */ |
188a5565 | 1277 | printf(" %08lX %s ", |
be60a902 HS |
1278 | info->start[i], |
1279 | info->protect[i] ? "RO" : " "); | |
bf9e3b38 | 1280 | #endif |
be60a902 | 1281 | } |
188a5565 | 1282 | putc('\n'); |
5653fc33 WD |
1283 | } |
1284 | ||
9a042e9c JVB |
1285 | /*----------------------------------------------------------------------- |
1286 | * This is used in a few places in write_buf() to show programming | |
1287 | * progress. Making it a function is nasty because it needs to do side | |
1288 | * effect updates to digit and dots. Repeated code is nasty too, so | |
1289 | * we define it once here. | |
1290 | */ | |
f0105727 SR |
1291 | #ifdef CONFIG_FLASH_SHOW_PROGRESS |
1292 | #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \ | |
6ea808ef PZ |
1293 | if (flash_verbose) { \ |
1294 | dots -= dots_sub; \ | |
4f89da49 | 1295 | if (scale > 0 && dots <= 0) { \ |
6ea808ef | 1296 | if ((digit % 5) == 0) \ |
188a5565 | 1297 | printf("%d", digit / 5); \ |
6ea808ef | 1298 | else \ |
188a5565 | 1299 | putc('.'); \ |
6ea808ef PZ |
1300 | digit--; \ |
1301 | dots += scale; \ | |
1302 | } \ | |
9a042e9c | 1303 | } |
f0105727 SR |
1304 | #else |
1305 | #define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) | |
1306 | #endif | |
9a042e9c | 1307 | |
be60a902 HS |
1308 | /*----------------------------------------------------------------------- |
1309 | * Copy memory to flash, returns: | |
1310 | * 0 - OK | |
1311 | * 1 - write timeout | |
1312 | * 2 - Flash not erased | |
5653fc33 | 1313 | */ |
ca2b07a8 | 1314 | int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
5653fc33 | 1315 | { |
be60a902 | 1316 | ulong wp; |
12d30aa7 | 1317 | uchar *p; |
be60a902 | 1318 | int aln; |
5653fc33 | 1319 | cfiword_t cword; |
be60a902 | 1320 | int i, rc; |
6d0f6bcf | 1321 | #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
be60a902 | 1322 | int buffered_size; |
5653fc33 | 1323 | #endif |
9a042e9c JVB |
1324 | #ifdef CONFIG_FLASH_SHOW_PROGRESS |
1325 | int digit = CONFIG_FLASH_SHOW_PROGRESS; | |
1326 | int scale = 0; | |
1327 | int dots = 0; | |
1328 | ||
1329 | /* | |
1330 | * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes. | |
1331 | */ | |
1332 | if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) { | |
1333 | scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) / | |
1334 | CONFIG_FLASH_SHOW_PROGRESS); | |
1335 | } | |
1336 | #endif | |
1337 | ||
be60a902 HS |
1338 | /* get lower aligned address */ |
1339 | wp = (addr & ~(info->portwidth - 1)); | |
3a197b2f | 1340 | |
be60a902 | 1341 | /* handle unaligned start */ |
d3525b6b MS |
1342 | aln = addr - wp; |
1343 | if (aln != 0) { | |
622b9527 | 1344 | cword.w32 = 0; |
09ce9921 | 1345 | p = (uchar *)wp; |
12d30aa7 | 1346 | for (i = 0; i < aln; ++i) |
188a5565 | 1347 | flash_add_byte(info, &cword, flash_read8(p + i)); |
5653fc33 | 1348 | |
be60a902 | 1349 | for (; (i < info->portwidth) && (cnt > 0); i++) { |
188a5565 | 1350 | flash_add_byte(info, &cword, *src++); |
be60a902 | 1351 | cnt--; |
be60a902 | 1352 | } |
12d30aa7 | 1353 | for (; (cnt == 0) && (i < info->portwidth); ++i) |
188a5565 | 1354 | flash_add_byte(info, &cword, flash_read8(p + i)); |
12d30aa7 | 1355 | |
188a5565 | 1356 | rc = flash_write_cfiword(info, wp, cword); |
12d30aa7 | 1357 | if (rc != 0) |
be60a902 | 1358 | return rc; |
12d30aa7 HS |
1359 | |
1360 | wp += i; | |
f0105727 | 1361 | FLASH_SHOW_PROGRESS(scale, dots, digit, i); |
be60a902 HS |
1362 | } |
1363 | ||
1364 | /* handle the aligned part */ | |
6d0f6bcf | 1365 | #ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
be60a902 HS |
1366 | buffered_size = (info->portwidth / info->chipwidth); |
1367 | buffered_size *= info->buffer_size; | |
1368 | while (cnt >= info->portwidth) { | |
1369 | /* prohibit buffer write when buffer_size is 1 */ | |
1370 | if (info->buffer_size == 1) { | |
622b9527 | 1371 | cword.w32 = 0; |
be60a902 | 1372 | for (i = 0; i < info->portwidth; i++) |
188a5565 | 1373 | flash_add_byte(info, &cword, *src++); |
d3525b6b MS |
1374 | rc = flash_write_cfiword(info, wp, cword); |
1375 | if (rc != 0) | |
be60a902 HS |
1376 | return rc; |
1377 | wp += info->portwidth; | |
1378 | cnt -= info->portwidth; | |
1379 | continue; | |
1380 | } | |
1381 | ||
1382 | /* write buffer until next buffered_size aligned boundary */ | |
1383 | i = buffered_size - (wp % buffered_size); | |
1384 | if (i > cnt) | |
1385 | i = cnt; | |
d3525b6b MS |
1386 | rc = flash_write_cfibuffer(info, wp, src, i); |
1387 | if (rc != ERR_OK) | |
be60a902 HS |
1388 | return rc; |
1389 | i -= i & (info->portwidth - 1); | |
1390 | wp += i; | |
1391 | src += i; | |
1392 | cnt -= i; | |
f0105727 | 1393 | FLASH_SHOW_PROGRESS(scale, dots, digit, i); |
de15a06a JH |
1394 | /* Only check every once in a while */ |
1395 | if ((cnt & 0xFFFF) < buffered_size && ctrlc()) | |
1396 | return ERR_ABORTED; | |
be60a902 HS |
1397 | } |
1398 | #else | |
1399 | while (cnt >= info->portwidth) { | |
622b9527 | 1400 | cword.w32 = 0; |
0412e903 | 1401 | for (i = 0; i < info->portwidth; i++) |
188a5565 | 1402 | flash_add_byte(info, &cword, *src++); |
d3525b6b MS |
1403 | rc = flash_write_cfiword(info, wp, cword); |
1404 | if (rc != 0) | |
be60a902 HS |
1405 | return rc; |
1406 | wp += info->portwidth; | |
1407 | cnt -= info->portwidth; | |
f0105727 | 1408 | FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth); |
de15a06a JH |
1409 | /* Only check every once in a while */ |
1410 | if ((cnt & 0xFFFF) < info->portwidth && ctrlc()) | |
1411 | return ERR_ABORTED; | |
be60a902 | 1412 | } |
6d0f6bcf | 1413 | #endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
9a042e9c | 1414 | |
0412e903 | 1415 | if (cnt == 0) |
be60a902 | 1416 | return (0); |
be60a902 HS |
1417 | |
1418 | /* | |
1419 | * handle unaligned tail bytes | |
1420 | */ | |
622b9527 | 1421 | cword.w32 = 0; |
09ce9921 | 1422 | p = (uchar *)wp; |
12d30aa7 | 1423 | for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) { |
188a5565 | 1424 | flash_add_byte(info, &cword, *src++); |
be60a902 HS |
1425 | --cnt; |
1426 | } | |
12d30aa7 | 1427 | for (; i < info->portwidth; ++i) |
188a5565 | 1428 | flash_add_byte(info, &cword, flash_read8(p + i)); |
be60a902 | 1429 | |
188a5565 | 1430 | return flash_write_cfiword(info, wp, cword); |
5653fc33 | 1431 | } |
bf9e3b38 | 1432 | |
20043a4c SR |
1433 | static inline int manufact_match(flash_info_t *info, u32 manu) |
1434 | { | |
1435 | return info->manufacturer_id == ((manu & FLASH_VENDMASK) >> 16); | |
1436 | } | |
1437 | ||
5653fc33 WD |
1438 | /*----------------------------------------------------------------------- |
1439 | */ | |
6d0f6bcf | 1440 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
be60a902 | 1441 | |
81316a90 HB |
1442 | static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot) |
1443 | { | |
88ecd8bf MS |
1444 | if (manufact_match(info, INTEL_MANUFACT) && |
1445 | info->device_id == NUMONYX_256MBIT) { | |
81316a90 HB |
1446 | /* |
1447 | * see errata called | |
1448 | * "Numonyx Axcell P33/P30 Specification Update" :) | |
1449 | */ | |
1450 | flash_write_cmd(info, sector, 0, FLASH_CMD_READ_ID); | |
1451 | if (!flash_isequal(info, sector, FLASH_OFFSET_PROTECT, | |
1452 | prot)) { | |
1453 | /* | |
1454 | * cmd must come before FLASH_CMD_PROTECT + 20us | |
1455 | * Disable interrupts which might cause a timeout here. | |
1456 | */ | |
1457 | int flag = disable_interrupts(); | |
1458 | unsigned short cmd; | |
1459 | ||
1460 | if (prot) | |
1461 | cmd = FLASH_CMD_PROTECT_SET; | |
1462 | else | |
1463 | cmd = FLASH_CMD_PROTECT_CLEAR; | |
58eab328 AP |
1464 | |
1465 | flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); | |
81316a90 HB |
1466 | flash_write_cmd(info, sector, 0, cmd); |
1467 | /* re-enable interrupts if necessary */ | |
1468 | if (flag) | |
1469 | enable_interrupts(); | |
1470 | } | |
1471 | return 1; | |
1472 | } | |
1473 | return 0; | |
1474 | } | |
1475 | ||
ca2b07a8 | 1476 | int flash_real_protect(flash_info_t *info, long sector, int prot) |
5653fc33 | 1477 | { |
be60a902 | 1478 | int retcode = 0; |
5653fc33 | 1479 | |
bc9019e1 | 1480 | switch (info->vendor) { |
dde0913b MS |
1481 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
1482 | case CFI_CMDSET_INTEL_STANDARD: | |
1483 | case CFI_CMDSET_INTEL_EXTENDED: | |
1484 | if (!cfi_protect_bugfix(info, sector, prot)) { | |
1485 | flash_write_cmd(info, sector, 0, | |
1486 | FLASH_CMD_CLEAR_STATUS); | |
1487 | flash_write_cmd(info, sector, 0, | |
1488 | FLASH_CMD_PROTECT); | |
1489 | if (prot) | |
81316a90 | 1490 | flash_write_cmd(info, sector, 0, |
dde0913b MS |
1491 | FLASH_CMD_PROTECT_SET); |
1492 | else | |
81316a90 | 1493 | flash_write_cmd(info, sector, 0, |
dde0913b | 1494 | FLASH_CMD_PROTECT_CLEAR); |
dde0913b MS |
1495 | } |
1496 | break; | |
1497 | case CFI_CMDSET_AMD_EXTENDED: | |
1498 | case CFI_CMDSET_AMD_STANDARD: | |
1499 | /* U-Boot only checks the first byte */ | |
1500 | if (manufact_match(info, ATM_MANUFACT)) { | |
1501 | if (prot) { | |
1502 | flash_unlock_seq(info, 0); | |
1503 | flash_write_cmd(info, 0, | |
1504 | info->addr_unlock1, | |
1505 | ATM_CMD_SOFTLOCK_START); | |
1506 | flash_unlock_seq(info, 0); | |
1507 | flash_write_cmd(info, sector, 0, | |
1508 | ATM_CMD_LOCK_SECT); | |
1509 | } else { | |
1510 | flash_write_cmd(info, 0, | |
1511 | info->addr_unlock1, | |
1512 | AMD_CMD_UNLOCK_START); | |
1513 | if (info->device_id == ATM_ID_BV6416) | |
1514 | flash_write_cmd(info, sector, | |
1515 | 0, ATM_CMD_UNLOCK_SECT); | |
54652991 | 1516 | } |
dde0913b MS |
1517 | } |
1518 | if (info->legacy_unlock) { | |
1519 | int flag = disable_interrupts(); | |
1520 | int lock_flag; | |
1521 | ||
1522 | flash_unlock_seq(info, 0); | |
1523 | flash_write_cmd(info, 0, info->addr_unlock1, | |
1524 | AMD_CMD_SET_PPB_ENTRY); | |
1525 | lock_flag = flash_isset(info, sector, 0, 0x01); | |
1526 | if (prot) { | |
1527 | if (lock_flag) { | |
188a5565 | 1528 | flash_write_cmd(info, sector, 0, |
dde0913b MS |
1529 | AMD_CMD_PPB_LOCK_BC1); |
1530 | flash_write_cmd(info, sector, 0, | |
1531 | AMD_CMD_PPB_LOCK_BC2); | |
bc9019e1 | 1532 | } |
dde0913b MS |
1533 | debug("sector %ld %slocked\n", sector, |
1534 | lock_flag ? "" : "already "); | |
1535 | } else { | |
1536 | if (!lock_flag) { | |
1537 | debug("unlock %ld\n", sector); | |
1538 | flash_write_cmd(info, 0, 0, | |
1539 | AMD_CMD_PPB_UNLOCK_BC1); | |
1540 | flash_write_cmd(info, 0, 0, | |
1541 | AMD_CMD_PPB_UNLOCK_BC2); | |
66863b05 | 1542 | } |
dde0913b MS |
1543 | debug("sector %ld %sunlocked\n", sector, |
1544 | !lock_flag ? "" : "already "); | |
66863b05 | 1545 | } |
dde0913b MS |
1546 | if (flag) |
1547 | enable_interrupts(); | |
1548 | ||
1549 | if (flash_status_check(info, sector, | |
1550 | info->erase_blk_tout, | |
1551 | prot ? "protect" : "unprotect")) | |
1552 | printf("status check error\n"); | |
1553 | ||
1554 | flash_write_cmd(info, 0, 0, | |
1555 | AMD_CMD_SET_PPB_EXIT_BC1); | |
1556 | flash_write_cmd(info, 0, 0, | |
1557 | AMD_CMD_SET_PPB_EXIT_BC2); | |
1558 | } | |
1559 | break; | |
4e00acde | 1560 | #ifdef CONFIG_FLASH_CFI_LEGACY |
dde0913b MS |
1561 | case CFI_CMDSET_AMD_LEGACY: |
1562 | flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS); | |
1563 | flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT); | |
1564 | if (prot) | |
1565 | flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET); | |
1566 | else | |
1567 | flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR); | |
4e00acde | 1568 | #endif |
bc9019e1 | 1569 | }; |
bf9e3b38 | 1570 | |
df4e813b SR |
1571 | /* |
1572 | * Flash needs to be in status register read mode for | |
1573 | * flash_full_status_check() to work correctly | |
1574 | */ | |
1575 | flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS); | |
d3525b6b MS |
1576 | retcode = flash_full_status_check(info, sector, info->erase_blk_tout, |
1577 | prot ? "protect" : "unprotect"); | |
1578 | if (retcode == 0) { | |
be60a902 HS |
1579 | info->protect[sector] = prot; |
1580 | ||
1581 | /* | |
1582 | * On some of Intel's flash chips (marked via legacy_unlock) | |
1583 | * unprotect unprotects all locking. | |
1584 | */ | |
4f89da49 | 1585 | if (prot == 0 && info->legacy_unlock) { |
be60a902 HS |
1586 | flash_sect_t i; |
1587 | ||
1588 | for (i = 0; i < info->sector_count; i++) { | |
1589 | if (info->protect[i]) | |
188a5565 | 1590 | flash_real_protect(info, i, 1); |
be60a902 | 1591 | } |
5653fc33 | 1592 | } |
5653fc33 | 1593 | } |
be60a902 | 1594 | return retcode; |
5653fc33 | 1595 | } |
bf9e3b38 | 1596 | |
5653fc33 | 1597 | /*----------------------------------------------------------------------- |
be60a902 | 1598 | * flash_read_user_serial - read the OneTimeProgramming cells |
5653fc33 | 1599 | */ |
ca2b07a8 | 1600 | void flash_read_user_serial(flash_info_t *info, void *buffer, int offset, |
be60a902 | 1601 | int len) |
5653fc33 | 1602 | { |
be60a902 HS |
1603 | uchar *src; |
1604 | uchar *dst; | |
bf9e3b38 | 1605 | |
be60a902 | 1606 | dst = buffer; |
188a5565 MS |
1607 | src = flash_map(info, 0, FLASH_OFFSET_USER_PROTECTION); |
1608 | flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); | |
1609 | memcpy(dst, src + offset, len); | |
1610 | flash_write_cmd(info, 0, 0, info->cmd_reset); | |
a90b9575 | 1611 | udelay(1); |
12d30aa7 | 1612 | flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src); |
5653fc33 WD |
1613 | } |
1614 | ||
be60a902 HS |
1615 | /* |
1616 | * flash_read_factory_serial - read the device Id from the protection area | |
5653fc33 | 1617 | */ |
ca2b07a8 | 1618 | void flash_read_factory_serial(flash_info_t *info, void *buffer, int offset, |
be60a902 | 1619 | int len) |
5653fc33 | 1620 | { |
be60a902 | 1621 | uchar *src; |
bf9e3b38 | 1622 | |
188a5565 MS |
1623 | src = flash_map(info, 0, FLASH_OFFSET_INTEL_PROTECTION); |
1624 | flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); | |
1625 | memcpy(buffer, src + offset, len); | |
1626 | flash_write_cmd(info, 0, 0, info->cmd_reset); | |
a90b9575 | 1627 | udelay(1); |
12d30aa7 | 1628 | flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src); |
5653fc33 WD |
1629 | } |
1630 | ||
6d0f6bcf | 1631 | #endif /* CONFIG_SYS_FLASH_PROTECTION */ |
be60a902 | 1632 | |
0ddf06dd HS |
1633 | /*----------------------------------------------------------------------- |
1634 | * Reverse the order of the erase regions in the CFI QRY structure. | |
1635 | * This is needed for chips that are either a) correctly detected as | |
1636 | * top-boot, or b) buggy. | |
1637 | */ | |
1638 | static void cfi_reverse_geometry(struct cfi_qry *qry) | |
1639 | { | |
1640 | unsigned int i, j; | |
1641 | u32 tmp; | |
1642 | ||
1643 | for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) { | |
4f89da49 MS |
1644 | tmp = get_unaligned(&qry->erase_region_info[i]); |
1645 | put_unaligned(get_unaligned(&qry->erase_region_info[j]), | |
1646 | &qry->erase_region_info[i]); | |
1647 | put_unaligned(tmp, &qry->erase_region_info[j]); | |
0ddf06dd HS |
1648 | } |
1649 | } | |
be60a902 | 1650 | |
260421a2 SR |
1651 | /*----------------------------------------------------------------------- |
1652 | * read jedec ids from device and set corresponding fields in info struct | |
1653 | * | |
1654 | * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct | |
1655 | * | |
0ddf06dd HS |
1656 | */ |
1657 | static void cmdset_intel_read_jedec_ids(flash_info_t *info) | |
1658 | { | |
1659 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); | |
a90b9575 | 1660 | udelay(1); |
0ddf06dd HS |
1661 | flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID); |
1662 | udelay(1000); /* some flash are slow to respond */ | |
188a5565 | 1663 | info->manufacturer_id = flash_read_uchar(info, |
0ddf06dd | 1664 | FLASH_OFFSET_MANUFACTURER_ID); |
d77c7ac4 | 1665 | info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ? |
188a5565 MS |
1666 | flash_read_word(info, FLASH_OFFSET_DEVICE_ID) : |
1667 | flash_read_uchar(info, FLASH_OFFSET_DEVICE_ID); | |
0ddf06dd HS |
1668 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); |
1669 | } | |
1670 | ||
1671 | static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) | |
1672 | { | |
1673 | info->cmd_reset = FLASH_CMD_RESET; | |
1674 | ||
1675 | cmdset_intel_read_jedec_ids(info); | |
1676 | flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); | |
1677 | ||
6d0f6bcf | 1678 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
0ddf06dd HS |
1679 | /* read legacy lock/unlock bit from intel flash */ |
1680 | if (info->ext_addr) { | |
188a5565 | 1681 | info->legacy_unlock = flash_read_uchar(info, |
0ddf06dd HS |
1682 | info->ext_addr + 5) & 0x08; |
1683 | } | |
1684 | #endif | |
1685 | ||
1686 | return 0; | |
1687 | } | |
1688 | ||
1689 | static void cmdset_amd_read_jedec_ids(flash_info_t *info) | |
1690 | { | |
3a7b2c21 NG |
1691 | ushort bankId = 0; |
1692 | uchar manuId; | |
2544f470 | 1693 | uchar feature; |
3a7b2c21 | 1694 | |
0ddf06dd HS |
1695 | flash_write_cmd(info, 0, 0, AMD_CMD_RESET); |
1696 | flash_unlock_seq(info, 0); | |
1697 | flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); | |
1698 | udelay(1000); /* some flash are slow to respond */ | |
90447ecb | 1699 | |
188a5565 | 1700 | manuId = flash_read_uchar(info, FLASH_OFFSET_MANUFACTURER_ID); |
3a7b2c21 NG |
1701 | /* JEDEC JEP106Z specifies ID codes up to bank 7 */ |
1702 | while (manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) { | |
1703 | bankId += 0x100; | |
188a5565 | 1704 | manuId = flash_read_uchar(info, |
3a7b2c21 NG |
1705 | bankId | FLASH_OFFSET_MANUFACTURER_ID); |
1706 | } | |
1707 | info->manufacturer_id = manuId; | |
90447ecb | 1708 | |
2544f470 YS |
1709 | debug("info->ext_addr = 0x%x, cfi_version = 0x%x\n", |
1710 | info->ext_addr, info->cfi_version); | |
1711 | if (info->ext_addr && info->cfi_version >= 0x3134) { | |
1712 | /* read software feature (at 0x53) */ | |
1713 | feature = flash_read_uchar(info, info->ext_addr + 0x13); | |
1714 | debug("feature = 0x%x\n", feature); | |
1715 | info->sr_supported = feature & 0x1; | |
1716 | } | |
72443c7f | 1717 | |
b168386b | 1718 | switch (info->chipwidth) { |
90447ecb | 1719 | case FLASH_CFI_8BIT: |
188a5565 | 1720 | info->device_id = flash_read_uchar(info, |
90447ecb TK |
1721 | FLASH_OFFSET_DEVICE_ID); |
1722 | if (info->device_id == 0x7E) { | |
1723 | /* AMD 3-byte (expanded) device ids */ | |
188a5565 | 1724 | info->device_id2 = flash_read_uchar(info, |
90447ecb TK |
1725 | FLASH_OFFSET_DEVICE_ID2); |
1726 | info->device_id2 <<= 8; | |
188a5565 | 1727 | info->device_id2 |= flash_read_uchar(info, |
90447ecb TK |
1728 | FLASH_OFFSET_DEVICE_ID3); |
1729 | } | |
1730 | break; | |
1731 | case FLASH_CFI_16BIT: | |
188a5565 | 1732 | info->device_id = flash_read_word(info, |
90447ecb | 1733 | FLASH_OFFSET_DEVICE_ID); |
5b448adb HS |
1734 | if ((info->device_id & 0xff) == 0x7E) { |
1735 | /* AMD 3-byte (expanded) device ids */ | |
188a5565 | 1736 | info->device_id2 = flash_read_uchar(info, |
5b448adb HS |
1737 | FLASH_OFFSET_DEVICE_ID2); |
1738 | info->device_id2 <<= 8; | |
188a5565 | 1739 | info->device_id2 |= flash_read_uchar(info, |
5b448adb HS |
1740 | FLASH_OFFSET_DEVICE_ID3); |
1741 | } | |
90447ecb TK |
1742 | break; |
1743 | default: | |
1744 | break; | |
0ddf06dd HS |
1745 | } |
1746 | flash_write_cmd(info, 0, 0, AMD_CMD_RESET); | |
a90b9575 | 1747 | udelay(1); |
0ddf06dd HS |
1748 | } |
1749 | ||
1750 | static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry) | |
1751 | { | |
1752 | info->cmd_reset = AMD_CMD_RESET; | |
07b2c5c0 | 1753 | info->cmd_erase_sector = AMD_CMD_ERASE_SECTOR; |
0ddf06dd HS |
1754 | |
1755 | cmdset_amd_read_jedec_ids(info); | |
1756 | flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI); | |
1757 | ||
66863b05 | 1758 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
ac6b9115 SR |
1759 | if (info->ext_addr) { |
1760 | /* read sector protect/unprotect scheme (at 0x49) */ | |
1761 | if (flash_read_uchar(info, info->ext_addr + 9) == 0x8) | |
66863b05 AG |
1762 | info->legacy_unlock = 1; |
1763 | } | |
1764 | #endif | |
1765 | ||
0ddf06dd HS |
1766 | return 0; |
1767 | } | |
1768 | ||
1769 | #ifdef CONFIG_FLASH_CFI_LEGACY | |
ca2b07a8 | 1770 | static void flash_read_jedec_ids(flash_info_t *info) |
260421a2 SR |
1771 | { |
1772 | info->manufacturer_id = 0; | |
1773 | info->device_id = 0; | |
1774 | info->device_id2 = 0; | |
1775 | ||
1776 | switch (info->vendor) { | |
9c048b52 | 1777 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
260421a2 SR |
1778 | case CFI_CMDSET_INTEL_STANDARD: |
1779 | case CFI_CMDSET_INTEL_EXTENDED: | |
8225d1e3 | 1780 | cmdset_intel_read_jedec_ids(info); |
260421a2 SR |
1781 | break; |
1782 | case CFI_CMDSET_AMD_STANDARD: | |
1783 | case CFI_CMDSET_AMD_EXTENDED: | |
8225d1e3 | 1784 | cmdset_amd_read_jedec_ids(info); |
260421a2 SR |
1785 | break; |
1786 | default: | |
1787 | break; | |
1788 | } | |
1789 | } | |
1790 | ||
5653fc33 | 1791 | /*----------------------------------------------------------------------- |
be60a902 HS |
1792 | * Call board code to request info about non-CFI flash. |
1793 | * board_flash_get_legacy needs to fill in at least: | |
1794 | * info->portwidth, info->chipwidth and info->interface for Jedec probing. | |
7e5b9b47 | 1795 | */ |
09ce9921 | 1796 | static int flash_detect_legacy(phys_addr_t base, int banknum) |
5653fc33 | 1797 | { |
be60a902 | 1798 | flash_info_t *info = &flash_info[banknum]; |
7e5b9b47 | 1799 | |
be60a902 HS |
1800 | if (board_flash_get_legacy(base, banknum, info)) { |
1801 | /* board code may have filled info completely. If not, we | |
a6d18f27 MS |
1802 | * use JEDEC ID probing. |
1803 | */ | |
be60a902 HS |
1804 | if (!info->vendor) { |
1805 | int modes[] = { | |
1806 | CFI_CMDSET_AMD_STANDARD, | |
1807 | CFI_CMDSET_INTEL_STANDARD | |
1808 | }; | |
1809 | int i; | |
7e5b9b47 | 1810 | |
31bf0f57 | 1811 | for (i = 0; i < ARRAY_SIZE(modes); i++) { |
be60a902 | 1812 | info->vendor = modes[i]; |
09ce9921 BB |
1813 | info->start[0] = |
1814 | (ulong)map_physmem(base, | |
e1fb6d0d | 1815 | info->portwidth, |
09ce9921 | 1816 | MAP_NOCACHE); |
88ecd8bf MS |
1817 | if (info->portwidth == FLASH_CFI_8BIT && |
1818 | info->interface == FLASH_CFI_X8X16) { | |
be60a902 HS |
1819 | info->addr_unlock1 = 0x2AAA; |
1820 | info->addr_unlock2 = 0x5555; | |
1821 | } else { | |
1822 | info->addr_unlock1 = 0x5555; | |
1823 | info->addr_unlock2 = 0x2AAA; | |
1824 | } | |
1825 | flash_read_jedec_ids(info); | |
1826 | debug("JEDEC PROBE: ID %x %x %x\n", | |
1827 | info->manufacturer_id, | |
1828 | info->device_id, | |
1829 | info->device_id2); | |
09ce9921 | 1830 | if (jedec_flash_match(info, info->start[0])) |
be60a902 | 1831 | break; |
9860137f MS |
1832 | |
1833 | unmap_physmem((void *)info->start[0], | |
1834 | info->portwidth); | |
be60a902 HS |
1835 | } |
1836 | } | |
1837 | ||
b168386b | 1838 | switch (info->vendor) { |
9c048b52 | 1839 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
be60a902 HS |
1840 | case CFI_CMDSET_INTEL_STANDARD: |
1841 | case CFI_CMDSET_INTEL_EXTENDED: | |
1842 | info->cmd_reset = FLASH_CMD_RESET; | |
1843 | break; | |
1844 | case CFI_CMDSET_AMD_STANDARD: | |
1845 | case CFI_CMDSET_AMD_EXTENDED: | |
1846 | case CFI_CMDSET_AMD_LEGACY: | |
1847 | info->cmd_reset = AMD_CMD_RESET; | |
1848 | break; | |
1849 | } | |
1850 | info->flash_id = FLASH_MAN_CFI; | |
1851 | return 1; | |
1852 | } | |
1853 | return 0; /* use CFI */ | |
1854 | } | |
1855 | #else | |
09ce9921 | 1856 | static inline int flash_detect_legacy(phys_addr_t base, int banknum) |
be60a902 HS |
1857 | { |
1858 | return 0; /* use CFI */ | |
1859 | } | |
1860 | #endif | |
1861 | ||
1862 | /*----------------------------------------------------------------------- | |
1863 | * detect if flash is compatible with the Common Flash Interface (CFI) | |
1864 | * http://www.jedec.org/download/search/jesd68.pdf | |
1865 | */ | |
188a5565 | 1866 | static void flash_read_cfi(flash_info_t *info, void *buf, |
e23741f4 HS |
1867 | unsigned int start, size_t len) |
1868 | { | |
1869 | u8 *p = buf; | |
1870 | unsigned int i; | |
1871 | ||
1872 | for (i = 0; i < len; i++) | |
e303be2d | 1873 | p[i] = flash_read_uchar(info, start + i); |
e23741f4 HS |
1874 | } |
1875 | ||
11dc4010 | 1876 | static void __flash_cmd_reset(flash_info_t *info) |
fa36ae79 SR |
1877 | { |
1878 | /* | |
1879 | * We do not yet know what kind of commandset to use, so we issue | |
1880 | * the reset command in both Intel and AMD variants, in the hope | |
1881 | * that AMD flash roms ignore the Intel command. | |
1882 | */ | |
1883 | flash_write_cmd(info, 0, 0, AMD_CMD_RESET); | |
a90b9575 | 1884 | udelay(1); |
fa36ae79 SR |
1885 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); |
1886 | } | |
7223a8cb | 1887 | |
fa36ae79 | 1888 | void flash_cmd_reset(flash_info_t *info) |
640f4e35 | 1889 | __attribute__((weak, alias("__flash_cmd_reset"))); |
fa36ae79 | 1890 | |
ca2b07a8 | 1891 | static int __flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry) |
be60a902 HS |
1892 | { |
1893 | int cfi_offset; | |
1894 | ||
e303be2d SR |
1895 | /* Issue FLASH reset command */ |
1896 | flash_cmd_reset(info); | |
1897 | ||
31bf0f57 | 1898 | for (cfi_offset = 0; cfi_offset < ARRAY_SIZE(flash_offset_cfi); |
be60a902 | 1899 | cfi_offset++) { |
188a5565 | 1900 | flash_write_cmd(info, 0, flash_offset_cfi[cfi_offset], |
be60a902 | 1901 | FLASH_CMD_CFI); |
88ecd8bf MS |
1902 | if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && |
1903 | flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') && | |
1904 | flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { | |
e23741f4 HS |
1905 | flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, |
1906 | sizeof(struct cfi_qry)); | |
1907 | info->interface = le16_to_cpu(qry->interface_desc); | |
e303be2d | 1908 | |
be60a902 | 1909 | info->cfi_offset = flash_offset_cfi[cfi_offset]; |
188a5565 | 1910 | debug("device interface is %d\n", |
be60a902 | 1911 | info->interface); |
188a5565 | 1912 | debug("found port %d chip %d ", |
be60a902 | 1913 | info->portwidth, info->chipwidth); |
188a5565 | 1914 | debug("port %d bits chip %d bits\n", |
be60a902 HS |
1915 | info->portwidth << CFI_FLASH_SHIFT_WIDTH, |
1916 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
1917 | ||
1918 | /* calculate command offsets as in the Linux driver */ | |
e303be2d SR |
1919 | info->addr_unlock1 = 0x555; |
1920 | info->addr_unlock2 = 0x2aa; | |
7e5b9b47 HS |
1921 | |
1922 | /* | |
1923 | * modify the unlock address if we are | |
1924 | * in compatibility mode | |
1925 | */ | |
b168386b | 1926 | if (/* x8/x16 in x8 mode */ |
4f89da49 MS |
1927 | (info->chipwidth == FLASH_CFI_BY8 && |
1928 | info->interface == FLASH_CFI_X8X16) || | |
b168386b | 1929 | /* x16/x32 in x16 mode */ |
4f89da49 | 1930 | (info->chipwidth == FLASH_CFI_BY16 && |
0cec0a12 | 1931 | info->interface == FLASH_CFI_X16X32)) { |
7e5b9b47 HS |
1932 | info->addr_unlock1 = 0xaaa; |
1933 | info->addr_unlock2 = 0x555; | |
1934 | } | |
1935 | ||
1936 | info->name = "CFI conformant"; | |
1937 | return 1; | |
1938 | } | |
1939 | } | |
1940 | ||
1941 | return 0; | |
1942 | } | |
1943 | ||
ca2b07a8 | 1944 | static int flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry) |
7e5b9b47 | 1945 | { |
188a5565 | 1946 | debug("flash detect cfi\n"); |
bf9e3b38 | 1947 | |
6d0f6bcf | 1948 | for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH; |
bf9e3b38 WD |
1949 | info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) { |
1950 | for (info->chipwidth = FLASH_CFI_BY8; | |
1951 | info->chipwidth <= info->portwidth; | |
7e5b9b47 | 1952 | info->chipwidth <<= 1) |
e303be2d | 1953 | if (__flash_detect_cfi(info, qry)) |
7e5b9b47 | 1954 | return 1; |
5653fc33 | 1955 | } |
188a5565 | 1956 | debug("not found\n"); |
5653fc33 WD |
1957 | return 0; |
1958 | } | |
bf9e3b38 | 1959 | |
467bcee1 HS |
1960 | /* |
1961 | * Manufacturer-specific quirks. Add workarounds for geometry | |
1962 | * reversal, etc. here. | |
1963 | */ | |
1964 | static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) | |
1965 | { | |
1966 | /* check if flash geometry needs reversal */ | |
1967 | if (qry->num_erase_regions > 1) { | |
1968 | /* reverse geometry if top boot part */ | |
1969 | if (info->cfi_version < 0x3131) { | |
1970 | /* CFI < 1.1, try to guess from device id */ | |
1971 | if ((info->device_id & 0x80) != 0) | |
1972 | cfi_reverse_geometry(qry); | |
e303be2d | 1973 | } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { |
467bcee1 HS |
1974 | /* CFI >= 1.1, deduct from top/bottom flag */ |
1975 | /* note: ext_addr is valid since cfi_version > 0 */ | |
1976 | cfi_reverse_geometry(qry); | |
1977 | } | |
1978 | } | |
1979 | } | |
1980 | ||
1981 | static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry) | |
1982 | { | |
1983 | int reverse_geometry = 0; | |
1984 | ||
1985 | /* Check the "top boot" bit in the PRI */ | |
1986 | if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1)) | |
1987 | reverse_geometry = 1; | |
1988 | ||
1989 | /* AT49BV6416(T) list the erase regions in the wrong order. | |
1990 | * However, the device ID is identical with the non-broken | |
cb82a532 | 1991 | * AT49BV642D they differ in the high byte. |
467bcee1 | 1992 | */ |
467bcee1 HS |
1993 | if (info->device_id == 0xd6 || info->device_id == 0xd2) |
1994 | reverse_geometry = !reverse_geometry; | |
467bcee1 HS |
1995 | |
1996 | if (reverse_geometry) | |
1997 | cfi_reverse_geometry(qry); | |
1998 | } | |
1999 | ||
e8eac437 RR |
2000 | static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry) |
2001 | { | |
2002 | /* check if flash geometry needs reversal */ | |
2003 | if (qry->num_erase_regions > 1) { | |
2004 | /* reverse geometry if top boot part */ | |
2005 | if (info->cfi_version < 0x3131) { | |
6a011ce8 MF |
2006 | /* CFI < 1.1, guess by device id */ |
2007 | if (info->device_id == 0x22CA || /* M29W320DT */ | |
2008 | info->device_id == 0x2256 || /* M29W320ET */ | |
2009 | info->device_id == 0x22D7) { /* M29W800DT */ | |
e8eac437 RR |
2010 | cfi_reverse_geometry(qry); |
2011 | } | |
4c2105cb MF |
2012 | } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { |
2013 | /* CFI >= 1.1, deduct from top/bottom flag */ | |
2014 | /* note: ext_addr is valid since cfi_version > 0 */ | |
2015 | cfi_reverse_geometry(qry); | |
e8eac437 RR |
2016 | } |
2017 | } | |
2018 | } | |
2019 | ||
07b2c5c0 AD |
2020 | static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry) |
2021 | { | |
2022 | /* | |
2023 | * SST, for many recent nor parallel flashes, says they are | |
2024 | * CFI-conformant. This is not true, since qry struct. | |
2025 | * reports a std. AMD command set (0x0002), while SST allows to | |
2026 | * erase two different sector sizes for the same memory. | |
2027 | * 64KB sector (SST call it block) needs 0x30 to be erased. | |
2028 | * 4KB sector (SST call it sector) needs 0x50 to be erased. | |
2029 | * Since CFI query detect the 4KB number of sectors, users expects | |
2030 | * a sector granularity of 4KB, and it is here set. | |
2031 | */ | |
2032 | if (info->device_id == 0x5D23 || /* SST39VF3201B */ | |
2033 | info->device_id == 0x5C23) { /* SST39VF3202B */ | |
2034 | /* set sector granularity to 4KB */ | |
640f4e35 | 2035 | info->cmd_erase_sector = 0x50; |
07b2c5c0 AD |
2036 | } |
2037 | } | |
2038 | ||
c502321c JT |
2039 | static void flash_fixup_num(flash_info_t *info, struct cfi_qry *qry) |
2040 | { | |
2041 | /* | |
2042 | * The M29EW devices seem to report the CFI information wrong | |
2043 | * when it's in 8 bit mode. | |
2044 | * There's an app note from Numonyx on this issue. | |
2045 | * So adjust the buffer size for M29EW while operating in 8-bit mode | |
2046 | */ | |
4f89da49 MS |
2047 | if (qry->max_buf_write_size > 0x8 && |
2048 | info->device_id == 0x7E && | |
c502321c JT |
2049 | (info->device_id2 == 0x2201 || |
2050 | info->device_id2 == 0x2301 || | |
2051 | info->device_id2 == 0x2801 || | |
2052 | info->device_id2 == 0x4801)) { | |
2053 | debug("Adjusted buffer size on Numonyx flash" | |
2054 | " M29EW family in 8 bit mode\n"); | |
2055 | qry->max_buf_write_size = 0x8; | |
2056 | } | |
2057 | } | |
2058 | ||
5653fc33 WD |
2059 | /* |
2060 | * The following code cannot be run from FLASH! | |
2061 | * | |
2062 | */ | |
188a5565 | 2063 | ulong flash_get_size(phys_addr_t base, int banknum) |
5653fc33 | 2064 | { |
bf9e3b38 | 2065 | flash_info_t *info = &flash_info[banknum]; |
5653fc33 WD |
2066 | int i, j; |
2067 | flash_sect_t sect_cnt; | |
09ce9921 | 2068 | phys_addr_t sector; |
5653fc33 WD |
2069 | unsigned long tmp; |
2070 | int size_ratio; | |
2071 | uchar num_erase_regions; | |
bf9e3b38 WD |
2072 | int erase_region_size; |
2073 | int erase_region_count; | |
e23741f4 | 2074 | struct cfi_qry qry; |
34bbb8fb | 2075 | unsigned long max_size; |
260421a2 | 2076 | |
f979690e KG |
2077 | memset(&qry, 0, sizeof(qry)); |
2078 | ||
260421a2 SR |
2079 | info->ext_addr = 0; |
2080 | info->cfi_version = 0; | |
6d0f6bcf | 2081 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
2662b40c SR |
2082 | info->legacy_unlock = 0; |
2083 | #endif | |
5653fc33 | 2084 | |
09ce9921 | 2085 | info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE); |
5653fc33 | 2086 | |
188a5565 | 2087 | if (flash_detect_cfi(info, &qry)) { |
4f89da49 MS |
2088 | info->vendor = le16_to_cpu(get_unaligned(&qry.p_id)); |
2089 | info->ext_addr = le16_to_cpu(get_unaligned(&qry.p_adr)); | |
e23741f4 HS |
2090 | num_erase_regions = qry.num_erase_regions; |
2091 | ||
260421a2 | 2092 | if (info->ext_addr) { |
640f4e35 | 2093 | info->cfi_version = (ushort)flash_read_uchar(info, |
e303be2d | 2094 | info->ext_addr + 3) << 8; |
640f4e35 | 2095 | info->cfi_version |= (ushort)flash_read_uchar(info, |
e303be2d | 2096 | info->ext_addr + 4); |
260421a2 | 2097 | } |
0ddf06dd | 2098 | |
bf9e3b38 | 2099 | #ifdef DEBUG |
188a5565 | 2100 | flash_printqry(&qry); |
bf9e3b38 | 2101 | #endif |
0ddf06dd | 2102 | |
bf9e3b38 | 2103 | switch (info->vendor) { |
9c048b52 | 2104 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
5653fc33 WD |
2105 | case CFI_CMDSET_INTEL_STANDARD: |
2106 | case CFI_CMDSET_INTEL_EXTENDED: | |
0ddf06dd | 2107 | cmdset_intel_init(info, &qry); |
5653fc33 WD |
2108 | break; |
2109 | case CFI_CMDSET_AMD_STANDARD: | |
2110 | case CFI_CMDSET_AMD_EXTENDED: | |
0ddf06dd | 2111 | cmdset_amd_init(info, &qry); |
5653fc33 | 2112 | break; |
0ddf06dd HS |
2113 | default: |
2114 | printf("CFI: Unknown command set 0x%x\n", | |
2115 | info->vendor); | |
2116 | /* | |
2117 | * Unfortunately, this means we don't know how | |
2118 | * to get the chip back to Read mode. Might | |
2119 | * as well try an Intel-style reset... | |
2120 | */ | |
2121 | flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); | |
2122 | return 0; | |
5653fc33 | 2123 | } |
cd37d9e6 | 2124 | |
467bcee1 HS |
2125 | /* Do manufacturer-specific fixups */ |
2126 | switch (info->manufacturer_id) { | |
2c9f48af MS |
2127 | case 0x0001: /* AMD */ |
2128 | case 0x0037: /* AMIC */ | |
467bcee1 HS |
2129 | flash_fixup_amd(info, &qry); |
2130 | break; | |
2131 | case 0x001f: | |
2132 | flash_fixup_atmel(info, &qry); | |
2133 | break; | |
e8eac437 RR |
2134 | case 0x0020: |
2135 | flash_fixup_stm(info, &qry); | |
2136 | break; | |
07b2c5c0 AD |
2137 | case 0x00bf: /* SST */ |
2138 | flash_fixup_sst(info, &qry); | |
2139 | break; | |
c502321c JT |
2140 | case 0x0089: /* Numonyx */ |
2141 | flash_fixup_num(info, &qry); | |
2142 | break; | |
467bcee1 HS |
2143 | } |
2144 | ||
188a5565 MS |
2145 | debug("manufacturer is %d\n", info->vendor); |
2146 | debug("manufacturer id is 0x%x\n", info->manufacturer_id); | |
2147 | debug("device id is 0x%x\n", info->device_id); | |
2148 | debug("device id2 is 0x%x\n", info->device_id2); | |
2149 | debug("cfi version is 0x%04x\n", info->cfi_version); | |
260421a2 | 2150 | |
5653fc33 | 2151 | size_ratio = info->portwidth / info->chipwidth; |
bf9e3b38 | 2152 | /* if the chip is x8/x16 reduce the ratio by half */ |
4f89da49 MS |
2153 | if (info->interface == FLASH_CFI_X8X16 && |
2154 | info->chipwidth == FLASH_CFI_BY8) { | |
bf9e3b38 WD |
2155 | size_ratio >>= 1; |
2156 | } | |
188a5565 | 2157 | debug("size_ratio %d port %d bits chip %d bits\n", |
bf9e3b38 WD |
2158 | size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH, |
2159 | info->chipwidth << CFI_FLASH_SHIFT_WIDTH); | |
ec50a8e3 IY |
2160 | info->size = 1 << qry.dev_size; |
2161 | /* multiply the size by the number of chips */ | |
2162 | info->size *= size_ratio; | |
34bbb8fb | 2163 | max_size = cfi_flash_bank_size(banknum); |
4f89da49 | 2164 | if (max_size && info->size > max_size) { |
ec50a8e3 IY |
2165 | debug("[truncated from %ldMiB]", info->size >> 20); |
2166 | info->size = max_size; | |
2167 | } | |
188a5565 | 2168 | debug("found %d erase regions\n", num_erase_regions); |
5653fc33 WD |
2169 | sect_cnt = 0; |
2170 | sector = base; | |
bf9e3b38 WD |
2171 | for (i = 0; i < num_erase_regions; i++) { |
2172 | if (i > NUM_ERASE_REGIONS) { | |
188a5565 | 2173 | printf("%d erase regions found, only %d used\n", |
028ab6b5 | 2174 | num_erase_regions, NUM_ERASE_REGIONS); |
5653fc33 WD |
2175 | break; |
2176 | } | |
e23741f4 | 2177 | |
aedadf10 | 2178 | tmp = le32_to_cpu(get_unaligned( |
4f89da49 | 2179 | &qry.erase_region_info[i])); |
0ddf06dd | 2180 | debug("erase region %u: 0x%08lx\n", i, tmp); |
e23741f4 HS |
2181 | |
2182 | erase_region_count = (tmp & 0xffff) + 1; | |
2183 | tmp >>= 16; | |
bf9e3b38 WD |
2184 | erase_region_size = |
2185 | (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128; | |
188a5565 | 2186 | debug("erase_region_count = %d erase_region_size = %d\n", |
028ab6b5 | 2187 | erase_region_count, erase_region_size); |
bf9e3b38 | 2188 | for (j = 0; j < erase_region_count; j++) { |
ec50a8e3 IY |
2189 | if (sector - base >= info->size) |
2190 | break; | |
6d0f6bcf | 2191 | if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) { |
81b20ccc MS |
2192 | printf("ERROR: too many flash sectors\n"); |
2193 | break; | |
2194 | } | |
09ce9921 BB |
2195 | info->start[sect_cnt] = |
2196 | (ulong)map_physmem(sector, | |
2197 | info->portwidth, | |
2198 | MAP_NOCACHE); | |
5653fc33 | 2199 | sector += (erase_region_size * size_ratio); |
a1191902 WD |
2200 | |
2201 | /* | |
7e5b9b47 HS |
2202 | * Only read protection status from |
2203 | * supported devices (intel...) | |
a1191902 WD |
2204 | */ |
2205 | switch (info->vendor) { | |
9c048b52 | 2206 | case CFI_CMDSET_INTEL_PROG_REGIONS: |
a1191902 WD |
2207 | case CFI_CMDSET_INTEL_EXTENDED: |
2208 | case CFI_CMDSET_INTEL_STANDARD: | |
df4e813b SR |
2209 | /* |
2210 | * Set flash to read-id mode. Otherwise | |
2211 | * reading protected status is not | |
2212 | * guaranteed. | |
2213 | */ | |
2214 | flash_write_cmd(info, sect_cnt, 0, | |
2215 | FLASH_CMD_READ_ID); | |
a1191902 | 2216 | info->protect[sect_cnt] = |
188a5565 | 2217 | flash_isset(info, sect_cnt, |
a1191902 WD |
2218 | FLASH_OFFSET_PROTECT, |
2219 | FLASH_STATUS_PROTECT); | |
edc498c6 VK |
2220 | flash_write_cmd(info, sect_cnt, 0, |
2221 | FLASH_CMD_RESET); | |
a1191902 | 2222 | break; |
03deff43 SR |
2223 | case CFI_CMDSET_AMD_EXTENDED: |
2224 | case CFI_CMDSET_AMD_STANDARD: | |
ac6b9115 | 2225 | if (!info->legacy_unlock) { |
03deff43 SR |
2226 | /* default: not protected */ |
2227 | info->protect[sect_cnt] = 0; | |
2228 | break; | |
2229 | } | |
2230 | ||
2231 | /* Read protection (PPB) from sector */ | |
2232 | flash_write_cmd(info, 0, 0, | |
2233 | info->cmd_reset); | |
2234 | flash_unlock_seq(info, 0); | |
2235 | flash_write_cmd(info, 0, | |
2236 | info->addr_unlock1, | |
2237 | FLASH_CMD_READ_ID); | |
2238 | info->protect[sect_cnt] = | |
2239 | flash_isset( | |
2240 | info, sect_cnt, | |
2241 | FLASH_OFFSET_PROTECT, | |
2242 | FLASH_STATUS_PROTECT); | |
2243 | break; | |
a1191902 | 2244 | default: |
7e5b9b47 HS |
2245 | /* default: not protected */ |
2246 | info->protect[sect_cnt] = 0; | |
a1191902 WD |
2247 | } |
2248 | ||
5653fc33 WD |
2249 | sect_cnt++; |
2250 | } | |
2251 | } | |
2252 | ||
2253 | info->sector_count = sect_cnt; | |
e23741f4 HS |
2254 | info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size); |
2255 | tmp = 1 << qry.block_erase_timeout_typ; | |
7e5b9b47 | 2256 | info->erase_blk_tout = tmp * |
e23741f4 HS |
2257 | (1 << qry.block_erase_timeout_max); |
2258 | tmp = (1 << qry.buf_write_timeout_typ) * | |
2259 | (1 << qry.buf_write_timeout_max); | |
2260 | ||
7e5b9b47 | 2261 | /* round up when converting to ms */ |
e23741f4 HS |
2262 | info->buffer_write_tout = (tmp + 999) / 1000; |
2263 | tmp = (1 << qry.word_write_timeout_typ) * | |
2264 | (1 << qry.word_write_timeout_max); | |
7e5b9b47 | 2265 | /* round up when converting to ms */ |
e23741f4 | 2266 | info->write_tout = (tmp + 999) / 1000; |
5653fc33 | 2267 | info->flash_id = FLASH_MAN_CFI; |
4f89da49 MS |
2268 | if (info->interface == FLASH_CFI_X8X16 && |
2269 | info->chipwidth == FLASH_CFI_BY8) { | |
7e5b9b47 HS |
2270 | /* XXX - Need to test on x8/x16 in parallel. */ |
2271 | info->portwidth >>= 1; | |
855a496f | 2272 | } |
2215987e | 2273 | |
188a5565 | 2274 | flash_write_cmd(info, 0, 0, info->cmd_reset); |
5653fc33 WD |
2275 | } |
2276 | ||
bf9e3b38 | 2277 | return (info->size); |
5653fc33 WD |
2278 | } |
2279 | ||
4ffeab2c | 2280 | #ifdef CONFIG_FLASH_CFI_MTD |
6ea808ef PZ |
2281 | void flash_set_verbose(uint v) |
2282 | { | |
2283 | flash_verbose = v; | |
2284 | } | |
4ffeab2c | 2285 | #endif |
6ea808ef | 2286 | |
6f726f95 SR |
2287 | static void cfi_flash_set_config_reg(u32 base, u16 val) |
2288 | { | |
2289 | #ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS | |
2290 | /* | |
2291 | * Only set this config register if really defined | |
2292 | * to a valid value (0xffff is invalid) | |
2293 | */ | |
2294 | if (val == 0xffff) | |
2295 | return; | |
2296 | ||
2297 | /* | |
2298 | * Set configuration register. Data is "encrypted" in the 16 lower | |
2299 | * address bits. | |
2300 | */ | |
2301 | flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1))); | |
2302 | flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1))); | |
2303 | ||
2304 | /* | |
2305 | * Finally issue reset-command to bring device back to | |
2306 | * read-array mode | |
2307 | */ | |
2308 | flash_write16(FLASH_CMD_RESET, (void *)base); | |
2309 | #endif | |
2310 | } | |
2311 | ||
5653fc33 WD |
2312 | /*----------------------------------------------------------------------- |
2313 | */ | |
6ee1416e | 2314 | |
236c49a1 | 2315 | static void flash_protect_default(void) |
6ee1416e | 2316 | { |
2c51983b PT |
2317 | #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) |
2318 | int i; | |
2319 | struct apl_s { | |
2320 | ulong start; | |
2321 | ulong size; | |
2322 | } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST; | |
2323 | #endif | |
2324 | ||
6ee1416e HS |
2325 | /* Monitor protection ON by default */ |
2326 | #if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ | |
2327 | (!defined(CONFIG_MONITOR_IS_IN_RAM)) | |
2328 | flash_protect(FLAG_PROTECT_SET, | |
2329 | CONFIG_SYS_MONITOR_BASE, | |
2330 | CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, | |
2331 | flash_get_info(CONFIG_SYS_MONITOR_BASE)); | |
2332 | #endif | |
2333 | ||
2334 | /* Environment protection ON by default */ | |
2335 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
2336 | flash_protect(FLAG_PROTECT_SET, | |
2337 | CONFIG_ENV_ADDR, | |
2338 | CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, | |
2339 | flash_get_info(CONFIG_ENV_ADDR)); | |
2340 | #endif | |
2341 | ||
2342 | /* Redundant environment protection ON by default */ | |
2343 | #ifdef CONFIG_ENV_ADDR_REDUND | |
2344 | flash_protect(FLAG_PROTECT_SET, | |
2345 | CONFIG_ENV_ADDR_REDUND, | |
2346 | CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, | |
2347 | flash_get_info(CONFIG_ENV_ADDR_REDUND)); | |
2348 | #endif | |
2349 | ||
2350 | #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) | |
31bf0f57 | 2351 | for (i = 0; i < ARRAY_SIZE(apl); i++) { |
31d34143 | 2352 | debug("autoprotecting from %08lx to %08lx\n", |
6ee1416e HS |
2353 | apl[i].start, apl[i].start + apl[i].size - 1); |
2354 | flash_protect(FLAG_PROTECT_SET, | |
2355 | apl[i].start, | |
2356 | apl[i].start + apl[i].size - 1, | |
2357 | flash_get_info(apl[i].start)); | |
2358 | } | |
2359 | #endif | |
2360 | } | |
2361 | ||
188a5565 | 2362 | unsigned long flash_init(void) |
5653fc33 | 2363 | { |
be60a902 HS |
2364 | unsigned long size = 0; |
2365 | int i; | |
5653fc33 | 2366 | |
6d0f6bcf | 2367 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
3a3baf3e ES |
2368 | /* read environment from EEPROM */ |
2369 | char s[64]; | |
7223a8cb | 2370 | |
00caae6d | 2371 | env_get_f("unlock", s, sizeof(s)); |
81b20ccc | 2372 | #endif |
5653fc33 | 2373 | |
f1056910 TC |
2374 | #ifdef CONFIG_CFI_FLASH /* for driver model */ |
2375 | cfi_flash_init_dm(); | |
2376 | #endif | |
2377 | ||
be60a902 | 2378 | /* Init: no FLASHes known */ |
6d0f6bcf | 2379 | for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { |
be60a902 | 2380 | flash_info[i].flash_id = FLASH_UNKNOWN; |
5653fc33 | 2381 | |
6f726f95 SR |
2382 | /* Optionally write flash configuration register */ |
2383 | cfi_flash_set_config_reg(cfi_flash_bank_addr(i), | |
2384 | cfi_flash_config_reg(i)); | |
2385 | ||
b00e19cc | 2386 | if (!flash_detect_legacy(cfi_flash_bank_addr(i), i)) |
34bbb8fb | 2387 | flash_get_size(cfi_flash_bank_addr(i), i); |
be60a902 HS |
2388 | size += flash_info[i].size; |
2389 | if (flash_info[i].flash_id == FLASH_UNKNOWN) { | |
6d0f6bcf | 2390 | #ifndef CONFIG_SYS_FLASH_QUIET_TEST |
188a5565 | 2391 | printf("## Unknown flash on Bank %d " |
be60a902 | 2392 | "- Size = 0x%08lx = %ld MB\n", |
640f4e35 | 2393 | i + 1, flash_info[i].size, |
0e3fa01a | 2394 | flash_info[i].size >> 20); |
6d0f6bcf | 2395 | #endif /* CONFIG_SYS_FLASH_QUIET_TEST */ |
be60a902 | 2396 | } |
6d0f6bcf | 2397 | #ifdef CONFIG_SYS_FLASH_PROTECTION |
c15df21f | 2398 | else if (strcmp(s, "yes") == 0) { |
be60a902 HS |
2399 | /* |
2400 | * Only the U-Boot image and it's environment | |
2401 | * is protected, all other sectors are | |
2402 | * unprotected (unlocked) if flash hardware | |
6d0f6bcf | 2403 | * protection is used (CONFIG_SYS_FLASH_PROTECTION) |
be60a902 HS |
2404 | * and the environment variable "unlock" is |
2405 | * set to "yes". | |
2406 | */ | |
2407 | if (flash_info[i].legacy_unlock) { | |
2408 | int k; | |
5653fc33 | 2409 | |
be60a902 HS |
2410 | /* |
2411 | * Disable legacy_unlock temporarily, | |
2412 | * since flash_real_protect would | |
2413 | * relock all other sectors again | |
2414 | * otherwise. | |
2415 | */ | |
2416 | flash_info[i].legacy_unlock = 0; | |
5653fc33 | 2417 | |
be60a902 HS |
2418 | /* |
2419 | * Legacy unlocking (e.g. Intel J3) -> | |
2420 | * unlock only one sector. This will | |
2421 | * unlock all sectors. | |
2422 | */ | |
188a5565 | 2423 | flash_real_protect(&flash_info[i], 0, 0); |
5653fc33 | 2424 | |
be60a902 | 2425 | flash_info[i].legacy_unlock = 1; |
5653fc33 | 2426 | |
be60a902 HS |
2427 | /* |
2428 | * Manually mark other sectors as | |
2429 | * unlocked (unprotected) | |
2430 | */ | |
2431 | for (k = 1; k < flash_info[i].sector_count; k++) | |
2432 | flash_info[i].protect[k] = 0; | |
2433 | } else { | |
2434 | /* | |
2435 | * No legancy unlocking -> unlock all sectors | |
2436 | */ | |
188a5565 | 2437 | flash_protect(FLAG_PROTECT_CLEAR, |
be60a902 HS |
2438 | flash_info[i].start[0], |
2439 | flash_info[i].start[0] | |
2440 | + flash_info[i].size - 1, | |
2441 | &flash_info[i]); | |
79b4cda0 | 2442 | } |
79b4cda0 | 2443 | } |
6d0f6bcf | 2444 | #endif /* CONFIG_SYS_FLASH_PROTECTION */ |
be60a902 | 2445 | } |
79b4cda0 | 2446 | |
6ee1416e | 2447 | flash_protect_default(); |
91809ed5 PZ |
2448 | #ifdef CONFIG_FLASH_CFI_MTD |
2449 | cfi_mtd_init(); | |
2450 | #endif | |
2451 | ||
be60a902 | 2452 | return (size); |
5653fc33 | 2453 | } |
f1056910 TC |
2454 | |
2455 | #ifdef CONFIG_CFI_FLASH /* for driver model */ | |
2456 | static int cfi_flash_probe(struct udevice *dev) | |
2457 | { | |
2458 | void *blob = (void *)gd->fdt_blob; | |
e160f7d4 | 2459 | int node = dev_of_offset(dev); |
f1056910 TC |
2460 | const fdt32_t *cell; |
2461 | phys_addr_t addr; | |
2462 | int parent, addrc, sizec; | |
2463 | int len, idx; | |
2464 | ||
2465 | parent = fdt_parent_offset(blob, node); | |
eed36609 | 2466 | fdt_support_default_count_cells(blob, parent, &addrc, &sizec); |
f1056910 TC |
2467 | /* decode regs, there may be multiple reg tuples. */ |
2468 | cell = fdt_getprop(blob, node, "reg", &len); | |
2469 | if (!cell) | |
2470 | return -ENOENT; | |
2471 | idx = 0; | |
2472 | len /= sizeof(fdt32_t); | |
2473 | while (idx < len) { | |
2474 | addr = fdt_translate_address((void *)blob, | |
2475 | node, cell + idx); | |
1ec0a37e MV |
2476 | flash_info[cfi_flash_num_flash_banks].dev = dev; |
2477 | flash_info[cfi_flash_num_flash_banks].base = addr; | |
2478 | cfi_flash_num_flash_banks++; | |
f1056910 TC |
2479 | idx += addrc + sizec; |
2480 | } | |
1ec0a37e | 2481 | gd->bd->bi_flashstart = flash_info[0].base; |
f1056910 TC |
2482 | |
2483 | return 0; | |
2484 | } | |
2485 | ||
2486 | static const struct udevice_id cfi_flash_ids[] = { | |
2487 | { .compatible = "cfi-flash" }, | |
2488 | { .compatible = "jedec-flash" }, | |
2489 | {} | |
2490 | }; | |
2491 | ||
2492 | U_BOOT_DRIVER(cfi_flash) = { | |
2493 | .name = "cfi_flash", | |
2494 | .id = UCLASS_MTD, | |
2495 | .of_match = cfi_flash_ids, | |
2496 | .probe = cfi_flash_probe, | |
2497 | }; | |
2498 | #endif /* CONFIG_CFI_FLASH */ |