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5653fc33 1/*
bf9e3b38 2 * (C) Copyright 2002-2004
5653fc33
WD
3 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
4 *
5 * Copyright (C) 2003 Arabella Software Ltd.
6 * Yuli Barcohen <yuli@arabellasw.com>
5653fc33 7 *
bf9e3b38
WD
8 * Copyright (C) 2004
9 * Ed Okerson
260421a2
SR
10 *
11 * Copyright (C) 2006
12 * Tolunay Orkun <listmember@orkun.us>
bf9e3b38 13 *
5653fc33
WD
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 *
5653fc33
WD
32 */
33
34/* The DEBUG define must be before common to enable debugging */
2d1a537d
WD
35/* #define DEBUG */
36
5653fc33
WD
37#include <common.h>
38#include <asm/processor.h>
3a197b2f 39#include <asm/io.h>
4c0d4c3b 40#include <asm/byteorder.h>
2a8af187 41#include <environment.h>
bf9e3b38 42#ifdef CFG_FLASH_CFI_DRIVER
028ab6b5 43
5653fc33 44/*
7e5b9b47
HS
45 * This file implements a Common Flash Interface (CFI) driver for
46 * U-Boot.
47 *
48 * The width of the port and the width of the chips are determined at
49 * initialization. These widths are used to calculate the address for
50 * access CFI data structures.
5653fc33
WD
51 *
52 * References
53 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
54 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
55 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
56 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
260421a2
SR
57 * AMD CFI Specification, Release 2.0 December 1, 2001
58 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte
59 * Device IDs, Publication Number 25538 Revision A, November 8, 2001
5653fc33 60 *
7e5b9b47 61 * Define CFG_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
d0b6e140 62 * reading and writing ... (yes there is such a Hardware).
5653fc33
WD
63 */
64
bf9e3b38
WD
65#ifndef CFG_FLASH_BANKS_LIST
66#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
67#endif
68
5653fc33
WD
69#define FLASH_CMD_CFI 0x98
70#define FLASH_CMD_READ_ID 0x90
71#define FLASH_CMD_RESET 0xff
72#define FLASH_CMD_BLOCK_ERASE 0x20
73#define FLASH_CMD_ERASE_CONFIRM 0xD0
74#define FLASH_CMD_WRITE 0x40
75#define FLASH_CMD_PROTECT 0x60
76#define FLASH_CMD_PROTECT_SET 0x01
77#define FLASH_CMD_PROTECT_CLEAR 0xD0
78#define FLASH_CMD_CLEAR_STATUS 0x50
bf9e3b38
WD
79#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
80#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
5653fc33
WD
81
82#define FLASH_STATUS_DONE 0x80
83#define FLASH_STATUS_ESS 0x40
84#define FLASH_STATUS_ECLBS 0x20
85#define FLASH_STATUS_PSLBS 0x10
86#define FLASH_STATUS_VPENS 0x08
87#define FLASH_STATUS_PSS 0x04
88#define FLASH_STATUS_DPS 0x02
89#define FLASH_STATUS_R 0x01
90#define FLASH_STATUS_PROTECT 0x01
91
92#define AMD_CMD_RESET 0xF0
93#define AMD_CMD_WRITE 0xA0
94#define AMD_CMD_ERASE_START 0x80
95#define AMD_CMD_ERASE_SECTOR 0x30
855a496f
WD
96#define AMD_CMD_UNLOCK_START 0xAA
97#define AMD_CMD_UNLOCK_ACK 0x55
79b4cda0
SR
98#define AMD_CMD_WRITE_TO_BUFFER 0x25
99#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29
5653fc33
WD
100
101#define AMD_STATUS_TOGGLE 0x40
102#define AMD_STATUS_ERROR 0x20
79b4cda0 103
260421a2
SR
104#define FLASH_OFFSET_MANUFACTURER_ID 0x00
105#define FLASH_OFFSET_DEVICE_ID 0x01
106#define FLASH_OFFSET_DEVICE_ID2 0x0E
107#define FLASH_OFFSET_DEVICE_ID3 0x0F
5653fc33 108#define FLASH_OFFSET_CFI 0x55
92eb729b 109#define FLASH_OFFSET_CFI_ALT 0x555
5653fc33 110#define FLASH_OFFSET_CFI_RESP 0x10
bf9e3b38 111#define FLASH_OFFSET_PRIMARY_VENDOR 0x13
7e5b9b47
HS
112/* extended query table primary address */
113#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15
5653fc33 114#define FLASH_OFFSET_WTOUT 0x1F
bf9e3b38 115#define FLASH_OFFSET_WBTOUT 0x20
5653fc33 116#define FLASH_OFFSET_ETOUT 0x21
bf9e3b38 117#define FLASH_OFFSET_CETOUT 0x22
5653fc33 118#define FLASH_OFFSET_WMAX_TOUT 0x23
bf9e3b38 119#define FLASH_OFFSET_WBMAX_TOUT 0x24
5653fc33 120#define FLASH_OFFSET_EMAX_TOUT 0x25
bf9e3b38 121#define FLASH_OFFSET_CEMAX_TOUT 0x26
5653fc33 122#define FLASH_OFFSET_SIZE 0x27
bf9e3b38
WD
123#define FLASH_OFFSET_INTERFACE 0x28
124#define FLASH_OFFSET_BUFFER_SIZE 0x2A
5653fc33
WD
125#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
126#define FLASH_OFFSET_ERASE_REGIONS 0x2D
127#define FLASH_OFFSET_PROTECT 0x02
bf9e3b38
WD
128#define FLASH_OFFSET_USER_PROTECTION 0x85
129#define FLASH_OFFSET_INTEL_PROTECTION 0x81
5653fc33 130
260421a2
SR
131#define CFI_CMDSET_NONE 0
132#define CFI_CMDSET_INTEL_EXTENDED 1
133#define CFI_CMDSET_AMD_STANDARD 2
134#define CFI_CMDSET_INTEL_STANDARD 3
135#define CFI_CMDSET_AMD_EXTENDED 4
136#define CFI_CMDSET_MITSU_STANDARD 256
137#define CFI_CMDSET_MITSU_EXTENDED 257
138#define CFI_CMDSET_SST 258
5653fc33 139
f7d1572b
WD
140#ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
141# undef FLASH_CMD_RESET
260421a2 142# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
f7d1572b
WD
143#endif
144
5653fc33
WD
145typedef union {
146 unsigned char c;
147 unsigned short w;
148 unsigned long l;
149 unsigned long long ll;
150} cfiword_t;
151
260421a2 152#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */
5653fc33 153
7e5b9b47 154static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
92eb729b 155
e6f2e902
MB
156/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
157#ifdef CFG_MAX_FLASH_BANKS_DETECT
158static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST;
159flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
160#else
5653fc33 161static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
e6f2e902
MB
162flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */
163#endif
5653fc33 164
79b4cda0
SR
165/*
166 * Check if chip width is defined. If not, start detecting with 8bit.
167 */
168#ifndef CFG_FLASH_CFI_WIDTH
169#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
170#endif
171
be60a902 172typedef unsigned long flash_sect_t;
5653fc33 173
e23741f4
HS
174/* CFI standard query structure */
175struct cfi_qry {
176 u8 qry[3];
177 u16 p_id;
178 u16 p_adr;
179 u16 a_id;
180 u16 a_adr;
181 u8 vcc_min;
182 u8 vcc_max;
183 u8 vpp_min;
184 u8 vpp_max;
185 u8 word_write_timeout_typ;
186 u8 buf_write_timeout_typ;
187 u8 block_erase_timeout_typ;
188 u8 chip_erase_timeout_typ;
189 u8 word_write_timeout_max;
190 u8 buf_write_timeout_max;
191 u8 block_erase_timeout_max;
192 u8 chip_erase_timeout_max;
193 u8 dev_size;
194 u16 interface_desc;
195 u16 max_buf_write_size;
196 u8 num_erase_regions;
197 u32 erase_region_info[NUM_ERASE_REGIONS];
198} __attribute__((packed));
199
200struct cfi_pri_hdr {
201 u8 pri[3];
202 u8 major_version;
203 u8 minor_version;
204} __attribute__((packed));
205
cdbaefb5
HS
206static void flash_write8(u8 value, void *addr)
207{
208 __raw_writeb(value, addr);
209}
210
211static void flash_write16(u16 value, void *addr)
212{
213 __raw_writew(value, addr);
214}
215
216static void flash_write32(u32 value, void *addr)
217{
218 __raw_writel(value, addr);
219}
220
221static void flash_write64(u64 value, void *addr)
222{
223 /* No architectures currently implement __raw_writeq() */
224 *(volatile u64 *)addr = value;
225}
226
227static u8 flash_read8(void *addr)
228{
229 return __raw_readb(addr);
230}
231
232static u16 flash_read16(void *addr)
233{
234 return __raw_readw(addr);
235}
236
237static u32 flash_read32(void *addr)
238{
239 return __raw_readl(addr);
240}
241
97bf85d7 242static u64 __flash_read64(void *addr)
cdbaefb5
HS
243{
244 /* No architectures currently implement __raw_readq() */
245 return *(volatile u64 *)addr;
246}
247
97bf85d7
DH
248u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64")));
249
5653fc33 250/*-----------------------------------------------------------------------
5653fc33 251 */
be60a902
HS
252#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
253static flash_info_t *flash_get_info(ulong base)
254{
255 int i;
256 flash_info_t * info = 0;
5653fc33 257
be60a902
HS
258 for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
259 info = & flash_info[i];
260 if (info->size && info->start[0] <= base &&
261 base <= info->start[0] + info->size - 1)
262 break;
263 }
5653fc33 264
be60a902
HS
265 return i == CFG_MAX_FLASH_BANKS ? 0 : info;
266}
5653fc33
WD
267#endif
268
12d30aa7
HS
269unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect)
270{
271 if (sect != (info->sector_count - 1))
272 return info->start[sect + 1] - info->start[sect];
273 else
274 return info->start[0] + info->size - info->start[sect];
275}
276
bf9e3b38
WD
277/*-----------------------------------------------------------------------
278 * create an address based on the offset and the port width
279 */
12d30aa7
HS
280static inline void *
281flash_map (flash_info_t * info, flash_sect_t sect, uint offset)
bf9e3b38 282{
12d30aa7
HS
283 unsigned int byte_offset = offset * info->portwidth;
284
285 return map_physmem(info->start[sect] + byte_offset,
286 flash_sector_size(info, sect) - byte_offset,
287 MAP_NOCACHE);
288}
289
290static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
291 unsigned int offset, void *addr)
292{
293 unsigned int byte_offset = offset * info->portwidth;
294
295 unmap_physmem(addr, flash_sector_size(info, sect) - byte_offset);
bf9e3b38
WD
296}
297
be60a902
HS
298/*-----------------------------------------------------------------------
299 * make a proper sized command based on the port and chip widths
300 */
301static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
302{
303 int i;
304 uchar *cp = (uchar *) cmdbuf;
305
306#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
307 for (i = info->portwidth; i > 0; i--)
308#else
309 for (i = 1; i <= info->portwidth; i++)
310#endif
311 *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd;
312}
313
5653fc33 314#ifdef DEBUG
bf9e3b38
WD
315/*-----------------------------------------------------------------------
316 * Debug support
317 */
3055793b 318static void print_longlong (char *str, unsigned long long data)
5653fc33
WD
319{
320 int i;
321 char *cp;
bf9e3b38
WD
322
323 cp = (unsigned char *) &data;
324 for (i = 0; i < 8; i++)
325 sprintf (&str[i * 2], "%2.2x", *cp++);
326}
be60a902 327
e23741f4 328static void flash_printqry (struct cfi_qry *qry)
bf9e3b38 329{
e23741f4 330 u8 *p = (u8 *)qry;
bf9e3b38
WD
331 int x, y;
332
e23741f4
HS
333 for (x = 0; x < sizeof(struct cfi_qry); x += 16) {
334 debug("%02x : ", x);
335 for (y = 0; y < 16; y++)
336 debug("%2.2x ", p[x + y]);
337 debug(" ");
bf9e3b38 338 for (y = 0; y < 16; y++) {
e23741f4
HS
339 unsigned char c = p[x + y];
340 if (c >= 0x20 && c <= 0x7e)
341 debug("%c", c);
342 else
343 debug(".");
bf9e3b38 344 }
e23741f4 345 debug("\n");
bf9e3b38 346 }
5653fc33
WD
347}
348#endif
349
350
5653fc33
WD
351/*-----------------------------------------------------------------------
352 * read a character at a port width address
353 */
3055793b 354static inline uchar flash_read_uchar (flash_info_t * info, uint offset)
5653fc33
WD
355{
356 uchar *cp;
12d30aa7 357 uchar retval;
bf9e3b38 358
12d30aa7 359 cp = flash_map (info, 0, offset);
d0b6e140 360#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
12d30aa7 361 retval = flash_read8(cp);
bf9e3b38 362#else
12d30aa7 363 retval = flash_read8(cp + info->portwidth - 1);
bf9e3b38 364#endif
12d30aa7
HS
365 flash_unmap (info, 0, offset, cp);
366 return retval;
5653fc33
WD
367}
368
90447ecb
TK
369/*-----------------------------------------------------------------------
370 * read a word at a port width address, assume 16bit bus
371 */
372static inline ushort flash_read_word (flash_info_t * info, uint offset)
373{
374 ushort *addr, retval;
375
376 addr = flash_map (info, 0, offset);
377 retval = flash_read16 (addr);
378 flash_unmap (info, 0, offset, addr);
379 return retval;
380}
381
382
5653fc33 383/*-----------------------------------------------------------------------
260421a2 384 * read a long word by picking the least significant byte of each maximum
5653fc33
WD
385 * port size word. Swap for ppc format.
386 */
3055793b
HS
387static ulong flash_read_long (flash_info_t * info, flash_sect_t sect,
388 uint offset)
5653fc33 389{
bf9e3b38
WD
390 uchar *addr;
391 ulong retval;
392
393#ifdef DEBUG
394 int x;
395#endif
12d30aa7 396 addr = flash_map (info, sect, offset);
5653fc33 397
bf9e3b38
WD
398#ifdef DEBUG
399 debug ("long addr is at %p info->portwidth = %d\n", addr,
400 info->portwidth);
401 for (x = 0; x < 4 * info->portwidth; x++) {
12d30aa7 402 debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
bf9e3b38
WD
403 }
404#endif
d0b6e140 405#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
12d30aa7
HS
406 retval = ((flash_read8(addr) << 16) |
407 (flash_read8(addr + info->portwidth) << 24) |
408 (flash_read8(addr + 2 * info->portwidth)) |
409 (flash_read8(addr + 3 * info->portwidth) << 8));
bf9e3b38 410#else
12d30aa7
HS
411 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) |
412 (flash_read8(addr + info->portwidth - 1) << 16) |
413 (flash_read8(addr + 4 * info->portwidth - 1) << 8) |
414 (flash_read8(addr + 3 * info->portwidth - 1)));
bf9e3b38 415#endif
12d30aa7
HS
416 flash_unmap(info, sect, offset, addr);
417
bf9e3b38 418 return retval;
5653fc33
WD
419}
420
be60a902
HS
421/*
422 * Write a proper sized command to the correct address
81b20ccc 423 */
be60a902
HS
424static void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
425 uint offset, uchar cmd)
81b20ccc 426{
7e5b9b47 427
cdbaefb5 428 void *addr;
be60a902 429 cfiword_t cword;
81b20ccc 430
12d30aa7 431 addr = flash_map (info, sect, offset);
be60a902
HS
432 flash_make_cmd (info, cmd, &cword);
433 switch (info->portwidth) {
434 case FLASH_CFI_8BIT:
cdbaefb5 435 debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd,
be60a902 436 cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 437 flash_write8(cword.c, addr);
be60a902
HS
438 break;
439 case FLASH_CFI_16BIT:
cdbaefb5 440 debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr,
be60a902
HS
441 cmd, cword.w,
442 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 443 flash_write16(cword.w, addr);
be60a902
HS
444 break;
445 case FLASH_CFI_32BIT:
cdbaefb5 446 debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr,
be60a902
HS
447 cmd, cword.l,
448 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 449 flash_write32(cword.l, addr);
be60a902
HS
450 break;
451 case FLASH_CFI_64BIT:
452#ifdef DEBUG
453 {
454 char str[20];
7e5b9b47 455
be60a902
HS
456 print_longlong (str, cword.ll);
457
458 debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
cdbaefb5 459 addr, cmd, str,
be60a902 460 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
81b20ccc 461 }
be60a902 462#endif
cdbaefb5 463 flash_write64(cword.ll, addr);
be60a902 464 break;
81b20ccc 465 }
be60a902
HS
466
467 /* Ensure all the instructions are fully finished */
468 sync();
12d30aa7
HS
469
470 flash_unmap(info, sect, offset, addr);
81b20ccc 471}
be60a902
HS
472
473static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
81b20ccc 474{
be60a902
HS
475 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START);
476 flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK);
81b20ccc 477}
81b20ccc 478
5653fc33
WD
479/*-----------------------------------------------------------------------
480 */
be60a902
HS
481static int flash_isequal (flash_info_t * info, flash_sect_t sect,
482 uint offset, uchar cmd)
5653fc33 483{
cdbaefb5 484 void *addr;
be60a902
HS
485 cfiword_t cword;
486 int retval;
5653fc33 487
12d30aa7 488 addr = flash_map (info, sect, offset);
be60a902 489 flash_make_cmd (info, cmd, &cword);
2662b40c 490
cdbaefb5 491 debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr);
be60a902
HS
492 switch (info->portwidth) {
493 case FLASH_CFI_8BIT:
cdbaefb5
HS
494 debug ("is= %x %x\n", flash_read8(addr), cword.c);
495 retval = (flash_read8(addr) == cword.c);
be60a902
HS
496 break;
497 case FLASH_CFI_16BIT:
cdbaefb5
HS
498 debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w);
499 retval = (flash_read16(addr) == cword.w);
be60a902
HS
500 break;
501 case FLASH_CFI_32BIT:
cdbaefb5
HS
502 debug ("is= %8.8lx %8.8lx\n", flash_read32(addr), cword.l);
503 retval = (flash_read32(addr) == cword.l);
be60a902
HS
504 break;
505 case FLASH_CFI_64BIT:
506#ifdef DEBUG
507 {
508 char str1[20];
509 char str2[20];
81b20ccc 510
cdbaefb5 511 print_longlong (str1, flash_read64(addr));
be60a902
HS
512 print_longlong (str2, cword.ll);
513 debug ("is= %s %s\n", str1, str2);
5653fc33 514 }
be60a902 515#endif
cdbaefb5 516 retval = (flash_read64(addr) == cword.ll);
be60a902
HS
517 break;
518 default:
519 retval = 0;
520 break;
521 }
12d30aa7
HS
522 flash_unmap(info, sect, offset, addr);
523
be60a902
HS
524 return retval;
525}
79b4cda0 526
be60a902
HS
527/*-----------------------------------------------------------------------
528 */
529static int flash_isset (flash_info_t * info, flash_sect_t sect,
530 uint offset, uchar cmd)
531{
cdbaefb5 532 void *addr;
be60a902
HS
533 cfiword_t cword;
534 int retval;
2662b40c 535
12d30aa7 536 addr = flash_map (info, sect, offset);
be60a902
HS
537 flash_make_cmd (info, cmd, &cword);
538 switch (info->portwidth) {
539 case FLASH_CFI_8BIT:
cdbaefb5 540 retval = ((flash_read8(addr) & cword.c) == cword.c);
be60a902
HS
541 break;
542 case FLASH_CFI_16BIT:
cdbaefb5 543 retval = ((flash_read16(addr) & cword.w) == cword.w);
be60a902
HS
544 break;
545 case FLASH_CFI_32BIT:
47cc23cb 546 retval = ((flash_read32(addr) & cword.l) == cword.l);
be60a902
HS
547 break;
548 case FLASH_CFI_64BIT:
cdbaefb5 549 retval = ((flash_read64(addr) & cword.ll) == cword.ll);
be60a902
HS
550 break;
551 default:
552 retval = 0;
553 break;
554 }
12d30aa7
HS
555 flash_unmap(info, sect, offset, addr);
556
be60a902
HS
557 return retval;
558}
2662b40c 559
be60a902
HS
560/*-----------------------------------------------------------------------
561 */
562static int flash_toggle (flash_info_t * info, flash_sect_t sect,
563 uint offset, uchar cmd)
564{
cdbaefb5 565 void *addr;
be60a902
HS
566 cfiword_t cword;
567 int retval;
656658dd 568
12d30aa7 569 addr = flash_map (info, sect, offset);
be60a902
HS
570 flash_make_cmd (info, cmd, &cword);
571 switch (info->portwidth) {
572 case FLASH_CFI_8BIT:
cdbaefb5
HS
573 retval = ((flash_read8(addr) & cword.c) !=
574 (flash_read8(addr) & cword.c));
be60a902
HS
575 break;
576 case FLASH_CFI_16BIT:
cdbaefb5
HS
577 retval = ((flash_read16(addr) & cword.w) !=
578 (flash_read16(addr) & cword.w));
be60a902
HS
579 break;
580 case FLASH_CFI_32BIT:
cdbaefb5
HS
581 retval = ((flash_read32(addr) & cword.l) !=
582 (flash_read32(addr) & cword.l));
be60a902
HS
583 break;
584 case FLASH_CFI_64BIT:
cdbaefb5
HS
585 retval = ((flash_read64(addr) & cword.ll) !=
586 (flash_read64(addr) & cword.ll));
be60a902
HS
587 break;
588 default:
589 retval = 0;
590 break;
591 }
12d30aa7
HS
592 flash_unmap(info, sect, offset, addr);
593
be60a902 594 return retval;
5653fc33
WD
595}
596
be60a902
HS
597/*
598 * flash_is_busy - check to see if the flash is busy
599 *
600 * This routine checks the status of the chip and returns true if the
601 * chip is busy.
7680c140 602 */
be60a902 603static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
7680c140 604{
be60a902 605 int retval;
7680c140 606
be60a902
HS
607 switch (info->vendor) {
608 case CFI_CMDSET_INTEL_STANDARD:
609 case CFI_CMDSET_INTEL_EXTENDED:
610 retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
611 break;
612 case CFI_CMDSET_AMD_STANDARD:
613 case CFI_CMDSET_AMD_EXTENDED:
614#ifdef CONFIG_FLASH_CFI_LEGACY
615 case CFI_CMDSET_AMD_LEGACY:
616#endif
617 retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
618 break;
619 default:
620 retval = 0;
7680c140 621 }
be60a902
HS
622 debug ("flash_is_busy: %d\n", retval);
623 return retval;
7680c140
WD
624}
625
5653fc33 626/*-----------------------------------------------------------------------
be60a902
HS
627 * wait for XSR.7 to be set. Time out with an error if it does not.
628 * This routine does not set the flash to read-array mode.
5653fc33 629 */
be60a902
HS
630static int flash_status_check (flash_info_t * info, flash_sect_t sector,
631 ulong tout, char *prompt)
5653fc33 632{
be60a902 633 ulong start;
5653fc33 634
be60a902
HS
635#if CFG_HZ != 1000
636 tout *= CFG_HZ/1000;
637#endif
5653fc33 638
be60a902
HS
639 /* Wait for command completion */
640 start = get_timer (0);
641 while (flash_is_busy (info, sector)) {
642 if (get_timer (start) > tout) {
643 printf ("Flash %s timeout at address %lx data %lx\n",
644 prompt, info->start[sector],
645 flash_read_long (info, sector, 0));
646 flash_write_cmd (info, sector, 0, info->cmd_reset);
647 return ERR_TIMOUT;
5653fc33 648 }
be60a902 649 udelay (1); /* also triggers watchdog */
5653fc33 650 }
be60a902
HS
651 return ERR_OK;
652}
5653fc33 653
be60a902
HS
654/*-----------------------------------------------------------------------
655 * Wait for XSR.7 to be set, if it times out print an error, otherwise
656 * do a full status check.
657 *
658 * This routine sets the flash to read-array mode.
659 */
660static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
661 ulong tout, char *prompt)
662{
663 int retcode;
5653fc33 664
be60a902
HS
665 retcode = flash_status_check (info, sector, tout, prompt);
666 switch (info->vendor) {
667 case CFI_CMDSET_INTEL_EXTENDED:
668 case CFI_CMDSET_INTEL_STANDARD:
669 if ((retcode == ERR_OK)
670 && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
671 retcode = ERR_INVAL;
672 printf ("Flash %s error at address %lx\n", prompt,
673 info->start[sector]);
674 if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS |
675 FLASH_STATUS_PSLBS)) {
676 puts ("Command Sequence Error.\n");
677 } else if (flash_isset (info, sector, 0,
678 FLASH_STATUS_ECLBS)) {
679 puts ("Block Erase Error.\n");
680 retcode = ERR_NOT_ERASED;
681 } else if (flash_isset (info, sector, 0,
682 FLASH_STATUS_PSLBS)) {
683 puts ("Locking Error\n");
5653fc33 684 }
be60a902
HS
685 if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
686 puts ("Block locked.\n");
687 retcode = ERR_PROTECTED;
688 }
689 if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
690 puts ("Vpp Low Error.\n");
5653fc33 691 }
be60a902
HS
692 flash_write_cmd (info, sector, 0, info->cmd_reset);
693 break;
694 default:
695 break;
5653fc33 696 }
be60a902 697 return retcode;
5653fc33
WD
698}
699
700/*-----------------------------------------------------------------------
701 */
be60a902 702static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
5653fc33 703{
be60a902
HS
704#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
705 unsigned short w;
706 unsigned int l;
707 unsigned long long ll;
708#endif
5653fc33 709
be60a902
HS
710 switch (info->portwidth) {
711 case FLASH_CFI_8BIT:
712 cword->c = c;
713 break;
714 case FLASH_CFI_16BIT:
715#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
716 w = c;
717 w <<= 8;
718 cword->w = (cword->w >> 8) | w;
719#else
720 cword->w = (cword->w << 8) | c;
81b20ccc 721#endif
be60a902
HS
722 break;
723 case FLASH_CFI_32BIT:
724#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
725 l = c;
726 l <<= 24;
727 cword->l = (cword->l >> 8) | l;
728#else
729 cword->l = (cword->l << 8) | c;
730#endif
731 break;
732 case FLASH_CFI_64BIT:
733#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
734 ll = c;
735 ll <<= 56;
736 cword->ll = (cword->ll >> 8) | ll;
737#else
738 cword->ll = (cword->ll << 8) | c;
739#endif
740 break;
260421a2 741 }
be60a902 742}
5653fc33 743
be60a902
HS
744/* loop through the sectors from the highest address when the passed
745 * address is greater or equal to the sector address we have a match
746 */
747static flash_sect_t find_sector (flash_info_t * info, ulong addr)
748{
749 flash_sect_t sector;
5653fc33 750
be60a902
HS
751 for (sector = info->sector_count - 1; sector >= 0; sector--) {
752 if (addr >= info->start[sector])
753 break;
5653fc33 754 }
be60a902 755 return sector;
5653fc33
WD
756}
757
758/*-----------------------------------------------------------------------
5653fc33 759 */
be60a902
HS
760static int flash_write_cfiword (flash_info_t * info, ulong dest,
761 cfiword_t cword)
5653fc33 762{
cdbaefb5 763 void *dstaddr;
be60a902 764 int flag;
5653fc33 765
12d30aa7 766 dstaddr = map_physmem(dest, info->portwidth, MAP_NOCACHE);
5653fc33 767
be60a902
HS
768 /* Check if Flash is (sufficiently) erased */
769 switch (info->portwidth) {
770 case FLASH_CFI_8BIT:
cdbaefb5 771 flag = ((flash_read8(dstaddr) & cword.c) == cword.c);
be60a902
HS
772 break;
773 case FLASH_CFI_16BIT:
cdbaefb5 774 flag = ((flash_read16(dstaddr) & cword.w) == cword.w);
be60a902
HS
775 break;
776 case FLASH_CFI_32BIT:
cdbaefb5 777 flag = ((flash_read32(dstaddr) & cword.l) == cword.l);
be60a902
HS
778 break;
779 case FLASH_CFI_64BIT:
cdbaefb5 780 flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll);
be60a902
HS
781 break;
782 default:
12d30aa7
HS
783 flag = 0;
784 break;
5653fc33 785 }
12d30aa7
HS
786 if (!flag) {
787 unmap_physmem(dstaddr, info->portwidth);
0dc80e27 788 return ERR_NOT_ERASED;
12d30aa7 789 }
5653fc33 790
be60a902
HS
791 /* Disable interrupts which might cause a timeout here */
792 flag = disable_interrupts ();
79b4cda0 793
be60a902
HS
794 switch (info->vendor) {
795 case CFI_CMDSET_INTEL_EXTENDED:
796 case CFI_CMDSET_INTEL_STANDARD:
797 flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
798 flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
799 break;
800 case CFI_CMDSET_AMD_EXTENDED:
801 case CFI_CMDSET_AMD_STANDARD:
802#ifdef CONFIG_FLASH_CFI_LEGACY
803 case CFI_CMDSET_AMD_LEGACY:
804#endif
805 flash_unlock_seq (info, 0);
806 flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE);
807 break;
5653fc33
WD
808 }
809
be60a902
HS
810 switch (info->portwidth) {
811 case FLASH_CFI_8BIT:
cdbaefb5 812 flash_write8(cword.c, dstaddr);
be60a902
HS
813 break;
814 case FLASH_CFI_16BIT:
cdbaefb5 815 flash_write16(cword.w, dstaddr);
be60a902
HS
816 break;
817 case FLASH_CFI_32BIT:
cdbaefb5 818 flash_write32(cword.l, dstaddr);
be60a902
HS
819 break;
820 case FLASH_CFI_64BIT:
cdbaefb5 821 flash_write64(cword.ll, dstaddr);
be60a902 822 break;
5653fc33
WD
823 }
824
be60a902
HS
825 /* re-enable interrupts if necessary */
826 if (flag)
827 enable_interrupts ();
5653fc33 828
12d30aa7
HS
829 unmap_physmem(dstaddr, info->portwidth);
830
be60a902
HS
831 return flash_full_status_check (info, find_sector (info, dest),
832 info->write_tout, "write");
5653fc33
WD
833}
834
be60a902 835#ifdef CFG_FLASH_USE_BUFFER_WRITE
5653fc33 836
be60a902
HS
837static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
838 int len)
5653fc33 839{
be60a902
HS
840 flash_sect_t sector;
841 int cnt;
842 int retcode;
cdbaefb5 843 void *src = cp;
12d30aa7 844 void *dst = map_physmem(dest, len, MAP_NOCACHE);
0dc80e27
SR
845 void *dst2 = dst;
846 int flag = 0;
96ef831f
GL
847 uint offset = 0;
848 unsigned int shift;
cdbaefb5 849
0dc80e27
SR
850 switch (info->portwidth) {
851 case FLASH_CFI_8BIT:
96ef831f 852 shift = 0;
0dc80e27
SR
853 break;
854 case FLASH_CFI_16BIT:
96ef831f 855 shift = 1;
0dc80e27
SR
856 break;
857 case FLASH_CFI_32BIT:
96ef831f 858 shift = 2;
0dc80e27
SR
859 break;
860 case FLASH_CFI_64BIT:
96ef831f 861 shift = 3;
0dc80e27
SR
862 break;
863 default:
864 retcode = ERR_INVAL;
865 goto out_unmap;
866 }
867
96ef831f
GL
868 cnt = len >> shift;
869
0dc80e27
SR
870 while ((cnt-- > 0) && (flag == 0)) {
871 switch (info->portwidth) {
872 case FLASH_CFI_8BIT:
873 flag = ((flash_read8(dst2) & flash_read8(src)) ==
874 flash_read8(src));
875 src += 1, dst2 += 1;
876 break;
877 case FLASH_CFI_16BIT:
878 flag = ((flash_read16(dst2) & flash_read16(src)) ==
879 flash_read16(src));
880 src += 2, dst2 += 2;
881 break;
882 case FLASH_CFI_32BIT:
883 flag = ((flash_read32(dst2) & flash_read32(src)) ==
884 flash_read32(src));
885 src += 4, dst2 += 4;
886 break;
887 case FLASH_CFI_64BIT:
888 flag = ((flash_read64(dst2) & flash_read64(src)) ==
889 flash_read64(src));
890 src += 8, dst2 += 8;
891 break;
892 }
893 }
894 if (!flag) {
895 retcode = ERR_NOT_ERASED;
896 goto out_unmap;
897 }
898
899 src = cp;
cdbaefb5 900 sector = find_sector (info, dest);
bf9e3b38
WD
901
902 switch (info->vendor) {
5653fc33
WD
903 case CFI_CMDSET_INTEL_STANDARD:
904 case CFI_CMDSET_INTEL_EXTENDED:
be60a902
HS
905 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
906 flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
907 retcode = flash_status_check (info, sector,
908 info->buffer_write_tout,
909 "write to buffer");
910 if (retcode == ERR_OK) {
911 /* reduce the number of loops by the width of
912 * the port */
96ef831f 913 cnt = len >> shift;
be60a902
HS
914 flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
915 while (cnt-- > 0) {
916 switch (info->portwidth) {
917 case FLASH_CFI_8BIT:
cdbaefb5
HS
918 flash_write8(flash_read8(src), dst);
919 src += 1, dst += 1;
be60a902
HS
920 break;
921 case FLASH_CFI_16BIT:
cdbaefb5
HS
922 flash_write16(flash_read16(src), dst);
923 src += 2, dst += 2;
be60a902
HS
924 break;
925 case FLASH_CFI_32BIT:
cdbaefb5
HS
926 flash_write32(flash_read32(src), dst);
927 src += 4, dst += 4;
be60a902
HS
928 break;
929 case FLASH_CFI_64BIT:
cdbaefb5
HS
930 flash_write64(flash_read64(src), dst);
931 src += 8, dst += 8;
be60a902
HS
932 break;
933 default:
12d30aa7
HS
934 retcode = ERR_INVAL;
935 goto out_unmap;
be60a902
HS
936 }
937 }
938 flash_write_cmd (info, sector, 0,
939 FLASH_CMD_WRITE_BUFFER_CONFIRM);
940 retcode = flash_full_status_check (
941 info, sector, info->buffer_write_tout,
942 "buffer write");
943 }
12d30aa7
HS
944
945 break;
be60a902 946
5653fc33
WD
947 case CFI_CMDSET_AMD_STANDARD:
948 case CFI_CMDSET_AMD_EXTENDED:
be60a902 949 flash_unlock_seq(info,0);
96ef831f
GL
950
951#ifdef CONFIG_FLASH_SPANSION_S29WS_N
952 offset = ((unsigned long)dst - info->start[sector]) >> shift;
953#endif
954 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER);
955 cnt = len >> shift;
956 flash_write_cmd(info, sector, offset, (uchar)cnt - 1);
be60a902
HS
957
958 switch (info->portwidth) {
959 case FLASH_CFI_8BIT:
cdbaefb5
HS
960 while (cnt-- > 0) {
961 flash_write8(flash_read8(src), dst);
962 src += 1, dst += 1;
963 }
be60a902
HS
964 break;
965 case FLASH_CFI_16BIT:
cdbaefb5
HS
966 while (cnt-- > 0) {
967 flash_write16(flash_read16(src), dst);
968 src += 2, dst += 2;
969 }
be60a902
HS
970 break;
971 case FLASH_CFI_32BIT:
cdbaefb5
HS
972 while (cnt-- > 0) {
973 flash_write32(flash_read32(src), dst);
974 src += 4, dst += 4;
975 }
be60a902
HS
976 break;
977 case FLASH_CFI_64BIT:
cdbaefb5
HS
978 while (cnt-- > 0) {
979 flash_write64(flash_read64(src), dst);
980 src += 8, dst += 8;
981 }
be60a902
HS
982 break;
983 default:
12d30aa7
HS
984 retcode = ERR_INVAL;
985 goto out_unmap;
be60a902
HS
986 }
987
988 flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
989 retcode = flash_full_status_check (info, sector,
990 info->buffer_write_tout,
991 "buffer write");
12d30aa7 992 break;
be60a902 993
5653fc33 994 default:
be60a902 995 debug ("Unknown Command Set\n");
12d30aa7
HS
996 retcode = ERR_INVAL;
997 break;
5653fc33 998 }
12d30aa7
HS
999
1000out_unmap:
1001 unmap_physmem(dst, len);
1002 return retcode;
5653fc33 1003}
be60a902
HS
1004#endif /* CFG_FLASH_USE_BUFFER_WRITE */
1005
bf9e3b38 1006
5653fc33 1007/*-----------------------------------------------------------------------
5653fc33 1008 */
be60a902 1009int flash_erase (flash_info_t * info, int s_first, int s_last)
5653fc33 1010{
be60a902
HS
1011 int rcode = 0;
1012 int prot;
1013 flash_sect_t sect;
5653fc33 1014
be60a902
HS
1015 if (info->flash_id != FLASH_MAN_CFI) {
1016 puts ("Can't erase unknown flash type - aborted\n");
1017 return 1;
1018 }
1019 if ((s_first < 0) || (s_first > s_last)) {
1020 puts ("- no sectors to erase\n");
1021 return 1;
1022 }
2662b40c 1023
be60a902
HS
1024 prot = 0;
1025 for (sect = s_first; sect <= s_last; ++sect) {
1026 if (info->protect[sect]) {
1027 prot++;
5653fc33
WD
1028 }
1029 }
be60a902
HS
1030 if (prot) {
1031 printf ("- Warning: %d protected sectors will not be erased!\n",
1032 prot);
1033 } else {
1034 putc ('\n');
1035 }
bf9e3b38 1036
bf9e3b38 1037
be60a902
HS
1038 for (sect = s_first; sect <= s_last; sect++) {
1039 if (info->protect[sect] == 0) { /* not protected */
1040 switch (info->vendor) {
1041 case CFI_CMDSET_INTEL_STANDARD:
1042 case CFI_CMDSET_INTEL_EXTENDED:
1043 flash_write_cmd (info, sect, 0,
1044 FLASH_CMD_CLEAR_STATUS);
1045 flash_write_cmd (info, sect, 0,
1046 FLASH_CMD_BLOCK_ERASE);
1047 flash_write_cmd (info, sect, 0,
1048 FLASH_CMD_ERASE_CONFIRM);
1049 break;
1050 case CFI_CMDSET_AMD_STANDARD:
1051 case CFI_CMDSET_AMD_EXTENDED:
1052 flash_unlock_seq (info, sect);
1053 flash_write_cmd (info, sect,
1054 info->addr_unlock1,
1055 AMD_CMD_ERASE_START);
1056 flash_unlock_seq (info, sect);
1057 flash_write_cmd (info, sect, 0,
1058 AMD_CMD_ERASE_SECTOR);
1059 break;
1060#ifdef CONFIG_FLASH_CFI_LEGACY
1061 case CFI_CMDSET_AMD_LEGACY:
1062 flash_unlock_seq (info, 0);
1063 flash_write_cmd (info, 0, info->addr_unlock1,
1064 AMD_CMD_ERASE_START);
1065 flash_unlock_seq (info, 0);
1066 flash_write_cmd (info, sect, 0,
1067 AMD_CMD_ERASE_SECTOR);
1068 break;
1069#endif
1070 default:
1071 debug ("Unkown flash vendor %d\n",
1072 info->vendor);
1073 break;
bf9e3b38 1074 }
be60a902
HS
1075
1076 if (flash_full_status_check
1077 (info, sect, info->erase_blk_tout, "erase")) {
1078 rcode = 1;
1079 } else
1080 putc ('.');
5653fc33 1081 }
5653fc33 1082 }
be60a902
HS
1083 puts (" done\n");
1084 return rcode;
5653fc33 1085}
bf9e3b38 1086
5653fc33
WD
1087/*-----------------------------------------------------------------------
1088 */
be60a902 1089void flash_print_info (flash_info_t * info)
5653fc33 1090{
be60a902 1091 int i;
4d13cbad 1092
be60a902
HS
1093 if (info->flash_id != FLASH_MAN_CFI) {
1094 puts ("missing or unknown FLASH type\n");
1095 return;
1096 }
1097
1098 printf ("%s FLASH (%d x %d)",
1099 info->name,
1100 (info->portwidth << 3), (info->chipwidth << 3));
1101 if (info->size < 1024*1024)
1102 printf (" Size: %ld kB in %d Sectors\n",
1103 info->size >> 10, info->sector_count);
1104 else
1105 printf (" Size: %ld MB in %d Sectors\n",
1106 info->size >> 20, info->sector_count);
1107 printf (" ");
1108 switch (info->vendor) {
1109 case CFI_CMDSET_INTEL_STANDARD:
1110 printf ("Intel Standard");
1111 break;
1112 case CFI_CMDSET_INTEL_EXTENDED:
1113 printf ("Intel Extended");
1114 break;
1115 case CFI_CMDSET_AMD_STANDARD:
1116 printf ("AMD Standard");
1117 break;
1118 case CFI_CMDSET_AMD_EXTENDED:
1119 printf ("AMD Extended");
1120 break;
1121#ifdef CONFIG_FLASH_CFI_LEGACY
1122 case CFI_CMDSET_AMD_LEGACY:
1123 printf ("AMD Legacy");
1124 break;
4d13cbad 1125#endif
be60a902
HS
1126 default:
1127 printf ("Unknown (%d)", info->vendor);
1128 break;
1129 }
1130 printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x%02X",
1131 info->manufacturer_id, info->device_id);
1132 if (info->device_id == 0x7E) {
1133 printf("%04X", info->device_id2);
1134 }
1135 printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
1136 info->erase_blk_tout,
1137 info->write_tout);
1138 if (info->buffer_size > 1) {
1139 printf (" Buffer write timeout: %ld ms, "
1140 "buffer size: %d bytes\n",
1141 info->buffer_write_tout,
1142 info->buffer_size);
5653fc33 1143 }
5653fc33 1144
be60a902
HS
1145 puts ("\n Sector Start Addresses:");
1146 for (i = 0; i < info->sector_count; ++i) {
1147 if ((i % 5) == 0)
1148 printf ("\n");
1149#ifdef CFG_FLASH_EMPTY_INFO
1150 int k;
1151 int size;
1152 int erased;
1153 volatile unsigned long *flash;
5653fc33 1154
be60a902
HS
1155 /*
1156 * Check if whole sector is erased
1157 */
12d30aa7 1158 size = flash_sector_size(info, i);
be60a902
HS
1159 erased = 1;
1160 flash = (volatile unsigned long *) info->start[i];
1161 size = size >> 2; /* divide by 4 for longword access */
1162 for (k = 0; k < size; k++) {
1163 if (*flash++ != 0xffffffff) {
1164 erased = 0;
1165 break;
1166 }
1167 }
bf9e3b38 1168
be60a902
HS
1169 /* print empty and read-only info */
1170 printf (" %08lX %c %s ",
1171 info->start[i],
1172 erased ? 'E' : ' ',
1173 info->protect[i] ? "RO" : " ");
1174#else /* ! CFG_FLASH_EMPTY_INFO */
1175 printf (" %08lX %s ",
1176 info->start[i],
1177 info->protect[i] ? "RO" : " ");
bf9e3b38 1178#endif
be60a902
HS
1179 }
1180 putc ('\n');
1181 return;
5653fc33
WD
1182}
1183
9a042e9c
JVB
1184/*-----------------------------------------------------------------------
1185 * This is used in a few places in write_buf() to show programming
1186 * progress. Making it a function is nasty because it needs to do side
1187 * effect updates to digit and dots. Repeated code is nasty too, so
1188 * we define it once here.
1189 */
f0105727
SR
1190#ifdef CONFIG_FLASH_SHOW_PROGRESS
1191#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \
1192 dots -= dots_sub; \
9a042e9c
JVB
1193 if ((scale > 0) && (dots <= 0)) { \
1194 if ((digit % 5) == 0) \
1195 printf ("%d", digit / 5); \
1196 else \
1197 putc ('.'); \
1198 digit--; \
1199 dots += scale; \
1200 }
f0105727
SR
1201#else
1202#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub)
1203#endif
9a042e9c 1204
be60a902
HS
1205/*-----------------------------------------------------------------------
1206 * Copy memory to flash, returns:
1207 * 0 - OK
1208 * 1 - write timeout
1209 * 2 - Flash not erased
5653fc33 1210 */
be60a902 1211int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
5653fc33 1212{
be60a902 1213 ulong wp;
12d30aa7 1214 uchar *p;
be60a902 1215 int aln;
5653fc33 1216 cfiword_t cword;
be60a902 1217 int i, rc;
be60a902
HS
1218#ifdef CFG_FLASH_USE_BUFFER_WRITE
1219 int buffered_size;
5653fc33 1220#endif
9a042e9c
JVB
1221#ifdef CONFIG_FLASH_SHOW_PROGRESS
1222 int digit = CONFIG_FLASH_SHOW_PROGRESS;
1223 int scale = 0;
1224 int dots = 0;
1225
1226 /*
1227 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes.
1228 */
1229 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) {
1230 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) /
1231 CONFIG_FLASH_SHOW_PROGRESS);
1232 }
1233#endif
1234
be60a902
HS
1235 /* get lower aligned address */
1236 wp = (addr & ~(info->portwidth - 1));
3a197b2f 1237
be60a902
HS
1238 /* handle unaligned start */
1239 if ((aln = addr - wp) != 0) {
1240 cword.l = 0;
12d30aa7
HS
1241 p = map_physmem(wp, info->portwidth, MAP_NOCACHE);
1242 for (i = 0; i < aln; ++i)
1243 flash_add_byte (info, &cword, flash_read8(p + i));
5653fc33 1244
be60a902
HS
1245 for (; (i < info->portwidth) && (cnt > 0); i++) {
1246 flash_add_byte (info, &cword, *src++);
1247 cnt--;
be60a902 1248 }
12d30aa7
HS
1249 for (; (cnt == 0) && (i < info->portwidth); ++i)
1250 flash_add_byte (info, &cword, flash_read8(p + i));
1251
1252 rc = flash_write_cfiword (info, wp, cword);
1253 unmap_physmem(p, info->portwidth);
1254 if (rc != 0)
be60a902 1255 return rc;
12d30aa7
HS
1256
1257 wp += i;
f0105727 1258 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
be60a902
HS
1259 }
1260
1261 /* handle the aligned part */
1262#ifdef CFG_FLASH_USE_BUFFER_WRITE
1263 buffered_size = (info->portwidth / info->chipwidth);
1264 buffered_size *= info->buffer_size;
1265 while (cnt >= info->portwidth) {
1266 /* prohibit buffer write when buffer_size is 1 */
1267 if (info->buffer_size == 1) {
1268 cword.l = 0;
1269 for (i = 0; i < info->portwidth; i++)
1270 flash_add_byte (info, &cword, *src++);
1271 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
1272 return rc;
1273 wp += info->portwidth;
1274 cnt -= info->portwidth;
1275 continue;
1276 }
1277
1278 /* write buffer until next buffered_size aligned boundary */
1279 i = buffered_size - (wp % buffered_size);
1280 if (i > cnt)
1281 i = cnt;
1282 if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
1283 return rc;
1284 i -= i & (info->portwidth - 1);
1285 wp += i;
1286 src += i;
1287 cnt -= i;
f0105727 1288 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
be60a902
HS
1289 }
1290#else
1291 while (cnt >= info->portwidth) {
1292 cword.l = 0;
1293 for (i = 0; i < info->portwidth; i++) {
1294 flash_add_byte (info, &cword, *src++);
1295 }
1296 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
1297 return rc;
1298 wp += info->portwidth;
1299 cnt -= info->portwidth;
f0105727 1300 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth);
be60a902
HS
1301 }
1302#endif /* CFG_FLASH_USE_BUFFER_WRITE */
9a042e9c 1303
be60a902
HS
1304 if (cnt == 0) {
1305 return (0);
1306 }
1307
1308 /*
1309 * handle unaligned tail bytes
1310 */
1311 cword.l = 0;
12d30aa7
HS
1312 p = map_physmem(wp, info->portwidth, MAP_NOCACHE);
1313 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) {
be60a902
HS
1314 flash_add_byte (info, &cword, *src++);
1315 --cnt;
1316 }
12d30aa7
HS
1317 for (; i < info->portwidth; ++i)
1318 flash_add_byte (info, &cword, flash_read8(p + i));
1319 unmap_physmem(p, info->portwidth);
be60a902
HS
1320
1321 return flash_write_cfiword (info, wp, cword);
5653fc33 1322}
bf9e3b38 1323
5653fc33
WD
1324/*-----------------------------------------------------------------------
1325 */
be60a902
HS
1326#ifdef CFG_FLASH_PROTECTION
1327
1328int flash_real_protect (flash_info_t * info, long sector, int prot)
5653fc33 1329{
be60a902 1330 int retcode = 0;
5653fc33 1331
be60a902
HS
1332 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1333 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
1334 if (prot)
1335 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
1336 else
1337 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
bf9e3b38 1338
be60a902
HS
1339 if ((retcode =
1340 flash_full_status_check (info, sector, info->erase_blk_tout,
1341 prot ? "protect" : "unprotect")) == 0) {
bf9e3b38 1342
be60a902
HS
1343 info->protect[sector] = prot;
1344
1345 /*
1346 * On some of Intel's flash chips (marked via legacy_unlock)
1347 * unprotect unprotects all locking.
1348 */
1349 if ((prot == 0) && (info->legacy_unlock)) {
1350 flash_sect_t i;
1351
1352 for (i = 0; i < info->sector_count; i++) {
1353 if (info->protect[i])
1354 flash_real_protect (info, i, 1);
1355 }
5653fc33 1356 }
5653fc33 1357 }
be60a902 1358 return retcode;
5653fc33 1359}
bf9e3b38 1360
5653fc33 1361/*-----------------------------------------------------------------------
be60a902 1362 * flash_read_user_serial - read the OneTimeProgramming cells
5653fc33 1363 */
be60a902
HS
1364void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
1365 int len)
5653fc33 1366{
be60a902
HS
1367 uchar *src;
1368 uchar *dst;
bf9e3b38 1369
be60a902 1370 dst = buffer;
12d30aa7 1371 src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION);
be60a902
HS
1372 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
1373 memcpy (dst, src + offset, len);
1374 flash_write_cmd (info, 0, 0, info->cmd_reset);
12d30aa7 1375 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src);
5653fc33
WD
1376}
1377
be60a902
HS
1378/*
1379 * flash_read_factory_serial - read the device Id from the protection area
5653fc33 1380 */
be60a902
HS
1381void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
1382 int len)
5653fc33 1383{
be60a902 1384 uchar *src;
bf9e3b38 1385
12d30aa7 1386 src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
be60a902
HS
1387 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
1388 memcpy (buffer, src + offset, len);
1389 flash_write_cmd (info, 0, 0, info->cmd_reset);
12d30aa7 1390 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src);
5653fc33
WD
1391}
1392
be60a902
HS
1393#endif /* CFG_FLASH_PROTECTION */
1394
0ddf06dd
HS
1395/*-----------------------------------------------------------------------
1396 * Reverse the order of the erase regions in the CFI QRY structure.
1397 * This is needed for chips that are either a) correctly detected as
1398 * top-boot, or b) buggy.
1399 */
1400static void cfi_reverse_geometry(struct cfi_qry *qry)
1401{
1402 unsigned int i, j;
1403 u32 tmp;
1404
1405 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) {
1406 tmp = qry->erase_region_info[i];
1407 qry->erase_region_info[i] = qry->erase_region_info[j];
1408 qry->erase_region_info[j] = tmp;
1409 }
1410}
be60a902 1411
260421a2
SR
1412/*-----------------------------------------------------------------------
1413 * read jedec ids from device and set corresponding fields in info struct
1414 *
1415 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct
1416 *
0ddf06dd
HS
1417 */
1418static void cmdset_intel_read_jedec_ids(flash_info_t *info)
1419{
1420 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1421 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1422 udelay(1000); /* some flash are slow to respond */
1423 info->manufacturer_id = flash_read_uchar (info,
1424 FLASH_OFFSET_MANUFACTURER_ID);
1425 info->device_id = flash_read_uchar (info,
1426 FLASH_OFFSET_DEVICE_ID);
1427 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1428}
1429
1430static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry)
1431{
1432 info->cmd_reset = FLASH_CMD_RESET;
1433
1434 cmdset_intel_read_jedec_ids(info);
1435 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1436
1437#ifdef CFG_FLASH_PROTECTION
1438 /* read legacy lock/unlock bit from intel flash */
1439 if (info->ext_addr) {
1440 info->legacy_unlock = flash_read_uchar (info,
1441 info->ext_addr + 5) & 0x08;
1442 }
1443#endif
1444
1445 return 0;
1446}
1447
1448static void cmdset_amd_read_jedec_ids(flash_info_t *info)
1449{
1450 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1451 flash_unlock_seq(info, 0);
1452 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID);
1453 udelay(1000); /* some flash are slow to respond */
90447ecb 1454
0ddf06dd
HS
1455 info->manufacturer_id = flash_read_uchar (info,
1456 FLASH_OFFSET_MANUFACTURER_ID);
90447ecb
TK
1457
1458 switch (info->chipwidth){
1459 case FLASH_CFI_8BIT:
1460 info->device_id = flash_read_uchar (info,
1461 FLASH_OFFSET_DEVICE_ID);
1462 if (info->device_id == 0x7E) {
1463 /* AMD 3-byte (expanded) device ids */
1464 info->device_id2 = flash_read_uchar (info,
1465 FLASH_OFFSET_DEVICE_ID2);
1466 info->device_id2 <<= 8;
1467 info->device_id2 |= flash_read_uchar (info,
1468 FLASH_OFFSET_DEVICE_ID3);
1469 }
1470 break;
1471 case FLASH_CFI_16BIT:
1472 info->device_id = flash_read_word (info,
1473 FLASH_OFFSET_DEVICE_ID);
1474 break;
1475 default:
1476 break;
0ddf06dd
HS
1477 }
1478 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1479}
1480
1481static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
1482{
1483 info->cmd_reset = AMD_CMD_RESET;
1484
1485 cmdset_amd_read_jedec_ids(info);
1486 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1487
0ddf06dd
HS
1488 return 0;
1489}
1490
1491#ifdef CONFIG_FLASH_CFI_LEGACY
260421a2
SR
1492static void flash_read_jedec_ids (flash_info_t * info)
1493{
1494 info->manufacturer_id = 0;
1495 info->device_id = 0;
1496 info->device_id2 = 0;
1497
1498 switch (info->vendor) {
1499 case CFI_CMDSET_INTEL_STANDARD:
1500 case CFI_CMDSET_INTEL_EXTENDED:
8225d1e3 1501 cmdset_intel_read_jedec_ids(info);
260421a2
SR
1502 break;
1503 case CFI_CMDSET_AMD_STANDARD:
1504 case CFI_CMDSET_AMD_EXTENDED:
8225d1e3 1505 cmdset_amd_read_jedec_ids(info);
260421a2
SR
1506 break;
1507 default:
1508 break;
1509 }
1510}
1511
5653fc33 1512/*-----------------------------------------------------------------------
be60a902
HS
1513 * Call board code to request info about non-CFI flash.
1514 * board_flash_get_legacy needs to fill in at least:
1515 * info->portwidth, info->chipwidth and info->interface for Jedec probing.
7e5b9b47 1516 */
be60a902 1517static int flash_detect_legacy(ulong base, int banknum)
5653fc33 1518{
be60a902 1519 flash_info_t *info = &flash_info[banknum];
7e5b9b47 1520
be60a902
HS
1521 if (board_flash_get_legacy(base, banknum, info)) {
1522 /* board code may have filled info completely. If not, we
1523 use JEDEC ID probing. */
1524 if (!info->vendor) {
1525 int modes[] = {
1526 CFI_CMDSET_AMD_STANDARD,
1527 CFI_CMDSET_INTEL_STANDARD
1528 };
1529 int i;
7e5b9b47 1530
be60a902
HS
1531 for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) {
1532 info->vendor = modes[i];
1533 info->start[0] = base;
1534 if (info->portwidth == FLASH_CFI_8BIT
1535 && info->interface == FLASH_CFI_X8X16) {
1536 info->addr_unlock1 = 0x2AAA;
1537 info->addr_unlock2 = 0x5555;
1538 } else {
1539 info->addr_unlock1 = 0x5555;
1540 info->addr_unlock2 = 0x2AAA;
1541 }
1542 flash_read_jedec_ids(info);
1543 debug("JEDEC PROBE: ID %x %x %x\n",
1544 info->manufacturer_id,
1545 info->device_id,
1546 info->device_id2);
1547 if (jedec_flash_match(info, base))
1548 break;
1549 }
1550 }
1551
1552 switch(info->vendor) {
1553 case CFI_CMDSET_INTEL_STANDARD:
1554 case CFI_CMDSET_INTEL_EXTENDED:
1555 info->cmd_reset = FLASH_CMD_RESET;
1556 break;
1557 case CFI_CMDSET_AMD_STANDARD:
1558 case CFI_CMDSET_AMD_EXTENDED:
1559 case CFI_CMDSET_AMD_LEGACY:
1560 info->cmd_reset = AMD_CMD_RESET;
1561 break;
1562 }
1563 info->flash_id = FLASH_MAN_CFI;
1564 return 1;
1565 }
1566 return 0; /* use CFI */
1567}
1568#else
1569static inline int flash_detect_legacy(ulong base, int banknum)
1570{
1571 return 0; /* use CFI */
1572}
1573#endif
1574
1575/*-----------------------------------------------------------------------
1576 * detect if flash is compatible with the Common Flash Interface (CFI)
1577 * http://www.jedec.org/download/search/jesd68.pdf
1578 */
e23741f4
HS
1579static void flash_read_cfi (flash_info_t *info, void *buf,
1580 unsigned int start, size_t len)
1581{
1582 u8 *p = buf;
1583 unsigned int i;
1584
1585 for (i = 0; i < len; i++)
1586 p[i] = flash_read_uchar(info, start + i);
1587}
1588
1589static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
be60a902
HS
1590{
1591 int cfi_offset;
1592
1ba639da
MS
1593 /* We do not yet know what kind of commandset to use, so we issue
1594 the reset command in both Intel and AMD variants, in the hope
1595 that AMD flash roms ignore the Intel command. */
1596 flash_write_cmd (info, 0, 0, AMD_CMD_RESET);
1597 flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
1598
be60a902
HS
1599 for (cfi_offset=0;
1600 cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint);
1601 cfi_offset++) {
1602 flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset],
1603 FLASH_CMD_CFI);
1604 if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
1605 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
1606 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
e23741f4
HS
1607 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP,
1608 sizeof(struct cfi_qry));
1609 info->interface = le16_to_cpu(qry->interface_desc);
1610
be60a902
HS
1611 info->cfi_offset = flash_offset_cfi[cfi_offset];
1612 debug ("device interface is %d\n",
1613 info->interface);
1614 debug ("found port %d chip %d ",
1615 info->portwidth, info->chipwidth);
1616 debug ("port %d bits chip %d bits\n",
1617 info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1618 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1619
1620 /* calculate command offsets as in the Linux driver */
1621 info->addr_unlock1 = 0x555;
7e5b9b47
HS
1622 info->addr_unlock2 = 0x2aa;
1623
1624 /*
1625 * modify the unlock address if we are
1626 * in compatibility mode
1627 */
1628 if ( /* x8/x16 in x8 mode */
1629 ((info->chipwidth == FLASH_CFI_BY8) &&
1630 (info->interface == FLASH_CFI_X8X16)) ||
1631 /* x16/x32 in x16 mode */
1632 ((info->chipwidth == FLASH_CFI_BY16) &&
1633 (info->interface == FLASH_CFI_X16X32)))
1634 {
1635 info->addr_unlock1 = 0xaaa;
1636 info->addr_unlock2 = 0x555;
1637 }
1638
1639 info->name = "CFI conformant";
1640 return 1;
1641 }
1642 }
1643
1644 return 0;
1645}
1646
e23741f4 1647static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
7e5b9b47 1648{
bf9e3b38
WD
1649 debug ("flash detect cfi\n");
1650
79b4cda0 1651 for (info->portwidth = CFG_FLASH_CFI_WIDTH;
bf9e3b38
WD
1652 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
1653 for (info->chipwidth = FLASH_CFI_BY8;
1654 info->chipwidth <= info->portwidth;
7e5b9b47 1655 info->chipwidth <<= 1)
e23741f4 1656 if (__flash_detect_cfi(info, qry))
7e5b9b47 1657 return 1;
5653fc33 1658 }
bf9e3b38 1659 debug ("not found\n");
5653fc33
WD
1660 return 0;
1661}
bf9e3b38 1662
467bcee1
HS
1663/*
1664 * Manufacturer-specific quirks. Add workarounds for geometry
1665 * reversal, etc. here.
1666 */
1667static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry)
1668{
1669 /* check if flash geometry needs reversal */
1670 if (qry->num_erase_regions > 1) {
1671 /* reverse geometry if top boot part */
1672 if (info->cfi_version < 0x3131) {
1673 /* CFI < 1.1, try to guess from device id */
1674 if ((info->device_id & 0x80) != 0)
1675 cfi_reverse_geometry(qry);
1676 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
1677 /* CFI >= 1.1, deduct from top/bottom flag */
1678 /* note: ext_addr is valid since cfi_version > 0 */
1679 cfi_reverse_geometry(qry);
1680 }
1681 }
1682}
1683
1684static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry)
1685{
1686 int reverse_geometry = 0;
1687
1688 /* Check the "top boot" bit in the PRI */
1689 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1))
1690 reverse_geometry = 1;
1691
1692 /* AT49BV6416(T) list the erase regions in the wrong order.
1693 * However, the device ID is identical with the non-broken
1694 * AT49BV642D since u-boot only reads the low byte (they
1695 * differ in the high byte.) So leave out this fixup for now.
1696 */
1697#if 0
1698 if (info->device_id == 0xd6 || info->device_id == 0xd2)
1699 reverse_geometry = !reverse_geometry;
1700#endif
1701
1702 if (reverse_geometry)
1703 cfi_reverse_geometry(qry);
1704}
1705
5653fc33
WD
1706/*
1707 * The following code cannot be run from FLASH!
1708 *
1709 */
e6f2e902 1710ulong flash_get_size (ulong base, int banknum)
5653fc33 1711{
bf9e3b38 1712 flash_info_t *info = &flash_info[banknum];
5653fc33
WD
1713 int i, j;
1714 flash_sect_t sect_cnt;
1715 unsigned long sector;
1716 unsigned long tmp;
1717 int size_ratio;
1718 uchar num_erase_regions;
bf9e3b38
WD
1719 int erase_region_size;
1720 int erase_region_count;
e23741f4 1721 struct cfi_qry qry;
260421a2
SR
1722
1723 info->ext_addr = 0;
1724 info->cfi_version = 0;
2662b40c 1725#ifdef CFG_FLASH_PROTECTION
2662b40c
SR
1726 info->legacy_unlock = 0;
1727#endif
5653fc33
WD
1728
1729 info->start[0] = base;
1730
e23741f4
HS
1731 if (flash_detect_cfi (info, &qry)) {
1732 info->vendor = le16_to_cpu(qry.p_id);
1733 info->ext_addr = le16_to_cpu(qry.p_adr);
1734 num_erase_regions = qry.num_erase_regions;
1735
260421a2
SR
1736 if (info->ext_addr) {
1737 info->cfi_version = (ushort) flash_read_uchar (info,
1738 info->ext_addr + 3) << 8;
1739 info->cfi_version |= (ushort) flash_read_uchar (info,
1740 info->ext_addr + 4);
1741 }
0ddf06dd 1742
bf9e3b38 1743#ifdef DEBUG
e23741f4 1744 flash_printqry (&qry);
bf9e3b38 1745#endif
0ddf06dd 1746
bf9e3b38 1747 switch (info->vendor) {
5653fc33
WD
1748 case CFI_CMDSET_INTEL_STANDARD:
1749 case CFI_CMDSET_INTEL_EXTENDED:
0ddf06dd 1750 cmdset_intel_init(info, &qry);
5653fc33
WD
1751 break;
1752 case CFI_CMDSET_AMD_STANDARD:
1753 case CFI_CMDSET_AMD_EXTENDED:
0ddf06dd 1754 cmdset_amd_init(info, &qry);
5653fc33 1755 break;
0ddf06dd
HS
1756 default:
1757 printf("CFI: Unknown command set 0x%x\n",
1758 info->vendor);
1759 /*
1760 * Unfortunately, this means we don't know how
1761 * to get the chip back to Read mode. Might
1762 * as well try an Intel-style reset...
1763 */
1764 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1765 return 0;
5653fc33 1766 }
cd37d9e6 1767
467bcee1
HS
1768 /* Do manufacturer-specific fixups */
1769 switch (info->manufacturer_id) {
1770 case 0x0001:
1771 flash_fixup_amd(info, &qry);
1772 break;
1773 case 0x001f:
1774 flash_fixup_atmel(info, &qry);
1775 break;
1776 }
1777
bf9e3b38 1778 debug ("manufacturer is %d\n", info->vendor);
260421a2
SR
1779 debug ("manufacturer id is 0x%x\n", info->manufacturer_id);
1780 debug ("device id is 0x%x\n", info->device_id);
1781 debug ("device id2 is 0x%x\n", info->device_id2);
1782 debug ("cfi version is 0x%04x\n", info->cfi_version);
1783
5653fc33 1784 size_ratio = info->portwidth / info->chipwidth;
bf9e3b38
WD
1785 /* if the chip is x8/x16 reduce the ratio by half */
1786 if ((info->interface == FLASH_CFI_X8X16)
1787 && (info->chipwidth == FLASH_CFI_BY8)) {
1788 size_ratio >>= 1;
1789 }
bf9e3b38
WD
1790 debug ("size_ratio %d port %d bits chip %d bits\n",
1791 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1792 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1793 debug ("found %d erase regions\n", num_erase_regions);
5653fc33
WD
1794 sect_cnt = 0;
1795 sector = base;
bf9e3b38
WD
1796 for (i = 0; i < num_erase_regions; i++) {
1797 if (i > NUM_ERASE_REGIONS) {
028ab6b5
WD
1798 printf ("%d erase regions found, only %d used\n",
1799 num_erase_regions, NUM_ERASE_REGIONS);
5653fc33
WD
1800 break;
1801 }
e23741f4 1802
0ddf06dd
HS
1803 tmp = le32_to_cpu(qry.erase_region_info[i]);
1804 debug("erase region %u: 0x%08lx\n", i, tmp);
e23741f4
HS
1805
1806 erase_region_count = (tmp & 0xffff) + 1;
1807 tmp >>= 16;
bf9e3b38
WD
1808 erase_region_size =
1809 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
4c0d4c3b 1810 debug ("erase_region_count = %d erase_region_size = %d\n",
028ab6b5 1811 erase_region_count, erase_region_size);
bf9e3b38 1812 for (j = 0; j < erase_region_count; j++) {
81b20ccc
MS
1813 if (sect_cnt >= CFG_MAX_FLASH_SECT) {
1814 printf("ERROR: too many flash sectors\n");
1815 break;
1816 }
5653fc33
WD
1817 info->start[sect_cnt] = sector;
1818 sector += (erase_region_size * size_ratio);
a1191902
WD
1819
1820 /*
7e5b9b47
HS
1821 * Only read protection status from
1822 * supported devices (intel...)
a1191902
WD
1823 */
1824 switch (info->vendor) {
1825 case CFI_CMDSET_INTEL_EXTENDED:
1826 case CFI_CMDSET_INTEL_STANDARD:
1827 info->protect[sect_cnt] =
1828 flash_isset (info, sect_cnt,
1829 FLASH_OFFSET_PROTECT,
1830 FLASH_STATUS_PROTECT);
1831 break;
1832 default:
7e5b9b47
HS
1833 /* default: not protected */
1834 info->protect[sect_cnt] = 0;
a1191902
WD
1835 }
1836
5653fc33
WD
1837 sect_cnt++;
1838 }
1839 }
1840
1841 info->sector_count = sect_cnt;
e23741f4 1842 info->size = 1 << qry.dev_size;
5653fc33 1843 /* multiply the size by the number of chips */
7e5b9b47 1844 info->size *= size_ratio;
e23741f4
HS
1845 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size);
1846 tmp = 1 << qry.block_erase_timeout_typ;
7e5b9b47 1847 info->erase_blk_tout = tmp *
e23741f4
HS
1848 (1 << qry.block_erase_timeout_max);
1849 tmp = (1 << qry.buf_write_timeout_typ) *
1850 (1 << qry.buf_write_timeout_max);
1851
7e5b9b47 1852 /* round up when converting to ms */
e23741f4
HS
1853 info->buffer_write_tout = (tmp + 999) / 1000;
1854 tmp = (1 << qry.word_write_timeout_typ) *
1855 (1 << qry.word_write_timeout_max);
7e5b9b47 1856 /* round up when converting to ms */
e23741f4 1857 info->write_tout = (tmp + 999) / 1000;
5653fc33 1858 info->flash_id = FLASH_MAN_CFI;
7e5b9b47
HS
1859 if ((info->interface == FLASH_CFI_X8X16) &&
1860 (info->chipwidth == FLASH_CFI_BY8)) {
1861 /* XXX - Need to test on x8/x16 in parallel. */
1862 info->portwidth >>= 1;
855a496f 1863 }
5653fc33
WD
1864 }
1865
db421e64 1866 flash_write_cmd (info, 0, 0, info->cmd_reset);
bf9e3b38 1867 return (info->size);
5653fc33
WD
1868}
1869
5653fc33
WD
1870/*-----------------------------------------------------------------------
1871 */
be60a902 1872unsigned long flash_init (void)
5653fc33 1873{
be60a902
HS
1874 unsigned long size = 0;
1875 int i;
5653fc33 1876
be60a902
HS
1877#ifdef CFG_FLASH_PROTECTION
1878 char *s = getenv("unlock");
81b20ccc 1879#endif
5653fc33 1880
be60a902
HS
1881 /* Init: no FLASHes known */
1882 for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
1883 flash_info[i].flash_id = FLASH_UNKNOWN;
5653fc33 1884
be60a902
HS
1885 if (!flash_detect_legacy (bank_base[i], i))
1886 flash_get_size (bank_base[i], i);
1887 size += flash_info[i].size;
1888 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
1889#ifndef CFG_FLASH_QUIET_TEST
1890 printf ("## Unknown FLASH on Bank %d "
1891 "- Size = 0x%08lx = %ld MB\n",
1892 i+1, flash_info[i].size,
1893 flash_info[i].size << 20);
1894#endif /* CFG_FLASH_QUIET_TEST */
1895 }
1896#ifdef CFG_FLASH_PROTECTION
1897 else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
1898 /*
1899 * Only the U-Boot image and it's environment
1900 * is protected, all other sectors are
1901 * unprotected (unlocked) if flash hardware
1902 * protection is used (CFG_FLASH_PROTECTION)
1903 * and the environment variable "unlock" is
1904 * set to "yes".
1905 */
1906 if (flash_info[i].legacy_unlock) {
1907 int k;
5653fc33 1908
be60a902
HS
1909 /*
1910 * Disable legacy_unlock temporarily,
1911 * since flash_real_protect would
1912 * relock all other sectors again
1913 * otherwise.
1914 */
1915 flash_info[i].legacy_unlock = 0;
5653fc33 1916
be60a902
HS
1917 /*
1918 * Legacy unlocking (e.g. Intel J3) ->
1919 * unlock only one sector. This will
1920 * unlock all sectors.
1921 */
1922 flash_real_protect (&flash_info[i], 0, 0);
5653fc33 1923
be60a902 1924 flash_info[i].legacy_unlock = 1;
5653fc33 1925
be60a902
HS
1926 /*
1927 * Manually mark other sectors as
1928 * unlocked (unprotected)
1929 */
1930 for (k = 1; k < flash_info[i].sector_count; k++)
1931 flash_info[i].protect[k] = 0;
1932 } else {
1933 /*
1934 * No legancy unlocking -> unlock all sectors
1935 */
1936 flash_protect (FLAG_PROTECT_CLEAR,
1937 flash_info[i].start[0],
1938 flash_info[i].start[0]
1939 + flash_info[i].size - 1,
1940 &flash_info[i]);
79b4cda0 1941 }
79b4cda0 1942 }
be60a902
HS
1943#endif /* CFG_FLASH_PROTECTION */
1944 }
79b4cda0 1945
be60a902
HS
1946 /* Monitor protection ON by default */
1947#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
1948 flash_protect (FLAG_PROTECT_SET,
1949 CFG_MONITOR_BASE,
1950 CFG_MONITOR_BASE + monitor_flash_len - 1,
1951 flash_get_info(CFG_MONITOR_BASE));
1952#endif
79b4cda0 1953
be60a902
HS
1954 /* Environment protection ON by default */
1955#ifdef CFG_ENV_IS_IN_FLASH
1956 flash_protect (FLAG_PROTECT_SET,
1957 CFG_ENV_ADDR,
1958 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
1959 flash_get_info(CFG_ENV_ADDR));
1960#endif
79b4cda0 1961
be60a902
HS
1962 /* Redundant environment protection ON by default */
1963#ifdef CFG_ENV_ADDR_REDUND
1964 flash_protect (FLAG_PROTECT_SET,
1965 CFG_ENV_ADDR_REDUND,
1966 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
1967 flash_get_info(CFG_ENV_ADDR_REDUND));
1968#endif
1969 return (size);
5653fc33 1970}
ca43ba18 1971
5653fc33 1972#endif /* CFG_FLASH_CFI */