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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / drivers / mtd / cfi_flash.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
5653fc33 2/*
bf9e3b38 3 * (C) Copyright 2002-2004
5653fc33
WD		 4 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
5 *
6 * Copyright (C) 2003 Arabella Software Ltd.
7 * Yuli Barcohen <yuli@arabellasw.com>
5653fc33 8 *
bf9e3b38
WD		 9 * Copyright (C) 2004
10 * Ed Okerson
260421a2
SR		 11 *
12 * Copyright (C) 2006
13 * Tolunay Orkun <listmember@orkun.us>
5653fc33
WD		 14 */
15
16/* The DEBUG define must be before common to enable debugging */
2d1a537d
WD		 17/* #define DEBUG */
18
d678a59d 19#include <common.h>
24b852a7 20#include <console.h>
f1056910 21#include <dm.h>
3a7d5571 22#include <env.h>
f1056910
TC		 23#include <errno.h>
24#include <fdt_support.h>
b79fdc76 25#include <flash.h>
691d719d 26#include <init.h>
c30b7adb 27#include <irq_func.h>
f7ae49fc 28#include <log.h>
401d1c4f 29#include <asm/global_data.h>
5653fc33 30#include <asm/processor.h>
3a197b2f 31#include <asm/io.h>
4c0d4c3b 32#include <asm/byteorder.h>
aedadf10 33#include <asm/unaligned.h>
f3998fdc 34#include <env_internal.h>
c05ed00a 35#include <linux/delay.h>
fa36ae79 36#include <mtd/cfi_flash.h>
a9f5faba 37#include <watchdog.h>
028ab6b5 38
5653fc33 39/*
7e5b9b47
HS		 40 * This file implements a Common Flash Interface (CFI) driver for
41 * U-Boot.
42 *
43 * The width of the port and the width of the chips are determined at
44 * initialization. These widths are used to calculate the address for
45 * access CFI data structures.
5653fc33
WD		 46 *
47 * References
48 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
49 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
50 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
51 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
260421a2
SR		 52 * AMD CFI Specification, Release 2.0 December 1, 2001
53 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte
54 * Device IDs, Publication Number 25538 Revision A, November 8, 2001
5653fc33 55 *
65cc0e2a 56 * Define CFG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
d0b6e140 57 * reading and writing ... (yes there is such a Hardware).
5653fc33
WD		 58 */
59
f1056910
TC		 60DECLARE_GLOBAL_DATA_PTR;
61
7e5b9b47 62static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
4ffeab2c 63#ifdef CONFIG_FLASH_CFI_MTD
6ea808ef 64static uint flash_verbose = 1;
4ffeab2c
MF		 65#else
66#define flash_verbose 1
67#endif
92eb729b 68
2a112b23
WD		 69flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */
70
00dcb07c
JH		 71#ifdef CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
72#define __maybe_weak __weak
73#else
74#define __maybe_weak static
75#endif
76
6f726f95
SR		 77/*
78 * 0xffff is an undefined value for the configuration register. When
79 * this value is returned, the configuration register shall not be
80 * written at all (default mode).
81 */
82static u16 cfi_flash_config_reg(int i)
83{
84#ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS
85 return ((u16 [])CONFIG_SYS_CFI_FLASH_CONFIG_REGS)[i];
86#else
87 return 0xffff;
88#endif
89}
90
ca5def3f 91#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
144fef87 92int cfi_flash_num_flash_banks = CFI_MAX_FLASH_BANKS;
d9a35697
MS		 93#else
94int cfi_flash_num_flash_banks;
ca5def3f
SR		 95#endif
96
f1056910
TC		 97#ifdef CONFIG_CFI_FLASH /* for driver model */
98static void cfi_flash_init_dm(void)
99{
100 struct udevice *dev;
101
102 cfi_flash_num_flash_banks = 0;
103 /*
104 * The uclass_first_device() will probe the first device and
105 * uclass_next_device() will probe the rest if they exist. So
106 * that cfi_flash_probe() will get called assigning the base
107 * addresses that are available.
108 */
109 for (uclass_first_device(UCLASS_MTD, &dev);
110 dev;
111 uclass_next_device(&dev)) {
112 }
113}
114
f1056910
TC		 115phys_addr_t cfi_flash_bank_addr(int i)
116{
1ec0a37e 117 return flash_info[i].base;
f1056910
TC		 118}
119#else
00dcb07c 120__weak phys_addr_t cfi_flash_bank_addr(int i)
b00e19cc 121{
65cc0e2a 122 return ((phys_addr_t [])CFG_SYS_FLASH_BANKS_LIST)[i];
b00e19cc 123}
f1056910 124#endif
b00e19cc 125
00dcb07c 126__weak unsigned long cfi_flash_bank_size(int i)
ec50a8e3 127{
65cc0e2a
TR		 128#ifdef CFG_SYS_FLASH_BANKS_SIZES
129 return ((unsigned long [])CFG_SYS_FLASH_BANKS_SIZES)[i];
ec50a8e3
IY		 130#else
131 return 0;
132#endif
133}
ec50a8e3 134
00dcb07c 135__maybe_weak void flash_write8(u8 value, void *addr)
cdbaefb5
HS		 136{
137 __raw_writeb(value, addr);
138}
139
00dcb07c 140__maybe_weak void flash_write16(u16 value, void *addr)
cdbaefb5
HS		 141{
142 __raw_writew(value, addr);
143}
144
00dcb07c 145__maybe_weak void flash_write32(u32 value, void *addr)
cdbaefb5
HS		 146{
147 __raw_writel(value, addr);
148}
149
00dcb07c 150__maybe_weak void flash_write64(u64 value, void *addr)
cdbaefb5
HS		 151{
152 /* No architectures currently implement __raw_writeq() */
153 *(volatile u64 *)addr = value;
154}
155
00dcb07c 156__maybe_weak u8 flash_read8(void *addr)
cdbaefb5
HS		 157{
158 return __raw_readb(addr);
159}
160
00dcb07c 161__maybe_weak u16 flash_read16(void *addr)
cdbaefb5
HS		 162{
163 return __raw_readw(addr);
164}
165
00dcb07c 166__maybe_weak u32 flash_read32(void *addr)
cdbaefb5
HS		 167{
168 return __raw_readl(addr);
169}
170
00dcb07c 171__maybe_weak u64 flash_read64(void *addr)
cdbaefb5
HS		 172{
173 /* No architectures currently implement __raw_readq() */
174 return *(volatile u64 *)addr;
175}
176
5653fc33 177/*-----------------------------------------------------------------------
5653fc33 178 */
ddcf0540 179#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || \
d75eacf9 180 (defined(CONFIG_SYS_MONITOR_BASE) && \
65cc0e2a 181 (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE))
236c49a1 182static flash_info_t *flash_get_info(ulong base)
be60a902
HS		 183{
184 int i;
24c185cf 185 flash_info_t *info;
5653fc33 186
98150e7e 187 for (i = 0; i < CFI_FLASH_BANKS; i++) {
e2e273a3 188 info = &flash_info[i];
be60a902
HS		 189 if (info->size && info->start[0] <= base &&
190 base <= info->start[0] + info->size - 1)
24c185cf 191 return info;
be60a902 192 }
5653fc33 193
24c185cf 194 return NULL;
be60a902 195}
5653fc33
WD		 196#endif
197
12d30aa7
HS		 198unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect)
199{
200 if (sect != (info->sector_count - 1))
201 return info->start[sect + 1] - info->start[sect];
202 else
203 return info->start[0] + info->size - info->start[sect];
204}
205
bf9e3b38
WD		 206/*-----------------------------------------------------------------------
207 * create an address based on the offset and the port width
208 */
12d30aa7 209static inline void *
ca2b07a8 210flash_map(flash_info_t *info, flash_sect_t sect, uint offset)
bf9e3b38 211{
e303be2d 212 unsigned int byte_offset = offset * info->portwidth;
12d30aa7 213
53879b17 214 return (void *)(info->start[sect] + (byte_offset << info->chip_lsb));
12d30aa7
HS		 215}
216
217static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
c0350fbf 218 unsigned int offset, void *addr)
12d30aa7 219{
bf9e3b38
WD		 220}
221
be60a902
HS		 222/*-----------------------------------------------------------------------
223 * make a proper sized command based on the port and chip widths
224 */
7288f972 225static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf)
be60a902
HS		 226{
227 int i;
93c56f21
VL		 228 int cword_offset;
229 int cp_offset;
65cc0e2a 230#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
340ccb26
SS		 231 u32 cmd_le = cpu_to_le32(cmd);
232#endif
93c56f21 233 uchar val;
be60a902
HS		 234 uchar *cp = (uchar *) cmdbuf;
235
b168386b 236 for (i = info->portwidth; i > 0; i--) {
640f4e35 237 cword_offset = (info->portwidth - i) % info->chipwidth;
65cc0e2a 238#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
93c56f21 239 cp_offset = info->portwidth - i;
db91bb24 240 val = *((uchar *)&cmd_le + cword_offset);
be60a902 241#else
93c56f21 242 cp_offset = i - 1;
db91bb24 243 val = *((uchar *)&cmd + sizeof(u32) - cword_offset - 1);
be60a902 244#endif
7288f972 245 cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val;
93c56f21 246 }
be60a902
HS		 247}
248
5653fc33 249#ifdef DEBUG
bf9e3b38
WD		 250/*-----------------------------------------------------------------------
251 * Debug support
252 */
188a5565 253static void print_longlong(char *str, unsigned long long data)
5653fc33
WD		 254{
255 int i;
256 char *cp;
bf9e3b38 257
640f4e35 258 cp = (char *)&data;
bf9e3b38 259 for (i = 0; i < 8; i++)
188a5565 260 sprintf(&str[i * 2], "%2.2x", *cp++);
bf9e3b38 261}
be60a902 262
188a5565 263static void flash_printqry(struct cfi_qry *qry)
bf9e3b38 264{
e23741f4 265 u8 *p = (u8 *)qry;
bf9e3b38
WD		 266 int x, y;
267
e23741f4
HS		 268 for (x = 0; x < sizeof(struct cfi_qry); x += 16) {
269 debug("%02x : ", x);
270 for (y = 0; y < 16; y++)
271 debug("%2.2x ", p[x + y]);
272 debug(" ");
bf9e3b38 273 for (y = 0; y < 16; y++) {
e23741f4 274 unsigned char c = p[x + y];
7223a8cb 275
e23741f4
HS		 276 if (c >= 0x20 && c <= 0x7e)
277 debug("%c", c);
278 else
279 debug(".");
bf9e3b38 280 }
e23741f4 281 debug("\n");
bf9e3b38 282 }
5653fc33
WD		 283}
284#endif
285
5653fc33
WD		 286/*-----------------------------------------------------------------------
287 * read a character at a port width address
288 */
ca2b07a8 289static inline uchar flash_read_uchar(flash_info_t *info, uint offset)
5653fc33
WD		 290{
291 uchar *cp;
12d30aa7 292 uchar retval;
bf9e3b38 293
188a5565 294 cp = flash_map(info, 0, offset);
65cc0e2a 295#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
12d30aa7 296 retval = flash_read8(cp);
bf9e3b38 297#else
12d30aa7 298 retval = flash_read8(cp + info->portwidth - 1);
bf9e3b38 299#endif
188a5565 300 flash_unmap(info, 0, offset, cp);
12d30aa7 301 return retval;
5653fc33
WD		 302}
303
90447ecb
TK		 304/*-----------------------------------------------------------------------
305 * read a word at a port width address, assume 16bit bus
306 */
ca2b07a8 307static inline ushort flash_read_word(flash_info_t *info, uint offset)
90447ecb
TK		 308{
309 ushort *addr, retval;
310
188a5565
MS		 311 addr = flash_map(info, 0, offset);
312 retval = flash_read16(addr);
313 flash_unmap(info, 0, offset, addr);
90447ecb
TK		 314 return retval;
315}
316
5653fc33 317/*-----------------------------------------------------------------------
260421a2 318 * read a long word by picking the least significant byte of each maximum
5653fc33
WD		 319 * port size word. Swap for ppc format.
320 */
ca2b07a8 321static ulong flash_read_long (flash_info_t *info, flash_sect_t sect,
3055793b 322 uint offset)
5653fc33 323{
bf9e3b38
WD		 324 uchar *addr;
325 ulong retval;
326
327#ifdef DEBUG
328 int x;
329#endif
188a5565 330 addr = flash_map(info, sect, offset);
5653fc33 331
bf9e3b38 332#ifdef DEBUG
188a5565 333 debug("long addr is at %p info->portwidth = %d\n", addr,
c0350fbf 334 info->portwidth);
0412e903 335 for (x = 0; x < 4 * info->portwidth; x++)
188a5565 336 debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
bf9e3b38 337#endif
65cc0e2a 338#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
12d30aa7
HS		 339 retval = ((flash_read8(addr) << 16) |
340 (flash_read8(addr + info->portwidth) << 24) |
341 (flash_read8(addr + 2 * info->portwidth)) |
342 (flash_read8(addr + 3 * info->portwidth) << 8));
bf9e3b38 343#else
12d30aa7
HS		 344 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) |
345 (flash_read8(addr + info->portwidth - 1) << 16) |
346 (flash_read8(addr + 4 * info->portwidth - 1) << 8) |
347 (flash_read8(addr + 3 * info->portwidth - 1)));
bf9e3b38 348#endif
12d30aa7
HS		 349 flash_unmap(info, sect, offset, addr);
350
bf9e3b38 351 return retval;
5653fc33
WD		 352}
353
be60a902
HS		 354/*
355 * Write a proper sized command to the correct address
81b20ccc 356 */
236c49a1
MV		 357static void flash_write_cmd(flash_info_t *info, flash_sect_t sect,
358 uint offset, u32 cmd)
81b20ccc 359{
cdbaefb5 360 void *addr;
be60a902 361 cfiword_t cword;
81b20ccc 362
188a5565
MS		 363 addr = flash_map(info, sect, offset);
364 flash_make_cmd(info, cmd, &cword);
be60a902
HS		 365 switch (info->portwidth) {
366 case FLASH_CFI_8BIT:
188a5565 367 debug("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd,
c0350fbf 368 cword.w8, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
622b9527 369 flash_write8(cword.w8, addr);
be60a902
HS		 370 break;
371 case FLASH_CFI_16BIT:
188a5565 372 debug("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr,
c0350fbf
MS		 373 cmd, cword.w16,
374 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
622b9527 375 flash_write16(cword.w16, addr);
be60a902
HS		 376 break;
377 case FLASH_CFI_32BIT:
188a5565 378 debug("fwc addr %p cmd %x %8.8x 32bit x %d bit\n", addr,
c0350fbf
MS		 379 cmd, cword.w32,
380 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
622b9527 381 flash_write32(cword.w32, addr);
be60a902
HS		 382 break;
383 case FLASH_CFI_64BIT:
384#ifdef DEBUG
385 {
386 char str[20];
7e5b9b47 387
188a5565 388 print_longlong(str, cword.w64);
be60a902 389
188a5565 390 debug("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
c0350fbf
MS		 391 addr, cmd, str,
392 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
81b20ccc 393 }
be60a902 394#endif
622b9527 395 flash_write64(cword.w64, addr);
be60a902 396 break;
81b20ccc 397 }
be60a902
HS		 398
399 /* Ensure all the instructions are fully finished */
400 sync();
12d30aa7
HS		 401
402 flash_unmap(info, sect, offset, addr);
81b20ccc 403}
be60a902 404
ca2b07a8 405static void flash_unlock_seq(flash_info_t *info, flash_sect_t sect)
81b20ccc 406{
188a5565
MS		 407 flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START);
408 flash_write_cmd(info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK);
81b20ccc 409}
81b20ccc 410
5653fc33
WD		 411/*-----------------------------------------------------------------------
412 */
c0350fbf
MS		 413static int flash_isequal(flash_info_t *info, flash_sect_t sect, uint offset,
414 uchar cmd)
5653fc33 415{
cdbaefb5 416 void *addr;
be60a902
HS		 417 cfiword_t cword;
418 int retval;
5653fc33 419
188a5565
MS		 420 addr = flash_map(info, sect, offset);
421 flash_make_cmd(info, cmd, &cword);
2662b40c 422
188a5565 423 debug("is= cmd %x(%c) addr %p ", cmd, cmd, addr);
be60a902
HS		 424 switch (info->portwidth) {
425 case FLASH_CFI_8BIT:
188a5565 426 debug("is= %x %x\n", flash_read8(addr), cword.w8);
622b9527 427 retval = (flash_read8(addr) == cword.w8);
be60a902
HS		 428 break;
429 case FLASH_CFI_16BIT:
188a5565 430 debug("is= %4.4x %4.4x\n", flash_read16(addr), cword.w16);
622b9527 431 retval = (flash_read16(addr) == cword.w16);
be60a902
HS		 432 break;
433 case FLASH_CFI_32BIT:
188a5565 434 debug("is= %8.8x %8.8x\n", flash_read32(addr), cword.w32);
622b9527 435 retval = (flash_read32(addr) == cword.w32);
be60a902
HS		 436 break;
437 case FLASH_CFI_64BIT:
438#ifdef DEBUG
439 {
440 char str1[20];
441 char str2[20];
81b20ccc 442
188a5565
MS		 443 print_longlong(str1, flash_read64(addr));
444 print_longlong(str2, cword.w64);
445 debug("is= %s %s\n", str1, str2);
5653fc33 446 }
be60a902 447#endif
622b9527 448 retval = (flash_read64(addr) == cword.w64);
be60a902
HS		 449 break;
450 default:
451 retval = 0;
452 break;
453 }
12d30aa7
HS		 454 flash_unmap(info, sect, offset, addr);
455
be60a902
HS		 456 return retval;
457}
79b4cda0 458
be60a902
HS		 459/*-----------------------------------------------------------------------
460 */
c0350fbf
MS		 461static int flash_isset(flash_info_t *info, flash_sect_t sect, uint offset,
462 uchar cmd)
be60a902 463{
cdbaefb5 464 void *addr;
be60a902
HS		 465 cfiword_t cword;
466 int retval;
2662b40c 467
188a5565
MS		 468 addr = flash_map(info, sect, offset);
469 flash_make_cmd(info, cmd, &cword);
be60a902
HS		 470 switch (info->portwidth) {
471 case FLASH_CFI_8BIT:
622b9527 472 retval = ((flash_read8(addr) & cword.w8) == cword.w8);
be60a902
HS		 473 break;
474 case FLASH_CFI_16BIT:
622b9527 475 retval = ((flash_read16(addr) & cword.w16) == cword.w16);
be60a902
HS		 476 break;
477 case FLASH_CFI_32BIT:
622b9527 478 retval = ((flash_read32(addr) & cword.w32) == cword.w32);
be60a902
HS		 479 break;
480 case FLASH_CFI_64BIT:
622b9527 481 retval = ((flash_read64(addr) & cword.w64) == cword.w64);
be60a902
HS		 482 break;
483 default:
484 retval = 0;
485 break;
486 }
12d30aa7
HS		 487 flash_unmap(info, sect, offset, addr);
488
be60a902
HS		 489 return retval;
490}
2662b40c 491
be60a902
HS		 492/*-----------------------------------------------------------------------
493 */
c0350fbf
MS		 494static int flash_toggle(flash_info_t *info, flash_sect_t sect, uint offset,
495 uchar cmd)
be60a902 496{
5312838d 497 u8 *addr;
be60a902
HS		 498 cfiword_t cword;
499 int retval;
656658dd 500
188a5565
MS		 501 addr = flash_map(info, sect, offset);
502 flash_make_cmd(info, cmd, &cword);
be60a902
HS		 503 switch (info->portwidth) {
504 case FLASH_CFI_8BIT:
fb8c061e 505 retval = flash_read8(addr) != flash_read8(addr);
be60a902
HS		 506 break;
507 case FLASH_CFI_16BIT:
fb8c061e 508 retval = flash_read16(addr) != flash_read16(addr);
be60a902
HS		 509 break;
510 case FLASH_CFI_32BIT:
fb8c061e 511 retval = flash_read32(addr) != flash_read32(addr);
be60a902
HS		 512 break;
513 case FLASH_CFI_64BIT:
b168386b 514 retval = ((flash_read32(addr) != flash_read32(addr)) ||
640f4e35 515 (flash_read32(addr + 4) != flash_read32(addr + 4)));
be60a902
HS		 516 break;
517 default:
518 retval = 0;
519 break;
520 }
12d30aa7
HS		 521 flash_unmap(info, sect, offset, addr);
522
be60a902 523 return retval;
5653fc33
WD		 524}
525
be60a902
HS		 526/*
527 * flash_is_busy - check to see if the flash is busy
528 *
529 * This routine checks the status of the chip and returns true if the
530 * chip is busy.
7680c140 531 */
ca2b07a8 532static int flash_is_busy(flash_info_t *info, flash_sect_t sect)
7680c140 533{
be60a902 534 int retval;
7680c140 535
be60a902 536 switch (info->vendor) {
9c048b52 537 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 538 case CFI_CMDSET_INTEL_STANDARD:
539 case CFI_CMDSET_INTEL_EXTENDED:
188a5565 540 retval = !flash_isset(info, sect, 0, FLASH_STATUS_DONE);
be60a902
HS		 541 break;
542 case CFI_CMDSET_AMD_STANDARD:
543 case CFI_CMDSET_AMD_EXTENDED:
544#ifdef CONFIG_FLASH_CFI_LEGACY
545 case CFI_CMDSET_AMD_LEGACY:
546#endif
72443c7f 547 if (info->sr_supported) {
188a5565 548 flash_write_cmd(info, sect, info->addr_unlock1,
c0350fbf 549 FLASH_CMD_READ_STATUS);
188a5565 550 retval = !flash_isset(info, sect, 0,
c0350fbf 551 FLASH_STATUS_DONE);
72443c7f 552 } else {
188a5565 553 retval = flash_toggle(info, sect, 0,
c0350fbf 554 AMD_STATUS_TOGGLE);
72443c7f
MV		 555 }
556
be60a902
HS		 557 break;
558 default:
559 retval = 0;
7680c140 560 }
38d2831d 561 debug("%s: %d\n", __func__, retval);
be60a902 562 return retval;
7680c140
WD		 563}
564
5653fc33 565/*-----------------------------------------------------------------------
be60a902
HS		 566 * wait for XSR.7 to be set. Time out with an error if it does not.
567 * This routine does not set the flash to read-array mode.
5653fc33 568 */
ca2b07a8 569static int flash_status_check(flash_info_t *info, flash_sect_t sector,
c0350fbf 570 ulong tout, char *prompt)
5653fc33 571{
be60a902 572 ulong start;
5653fc33 573
6d0f6bcf 574#if CONFIG_SYS_HZ != 1000
ddcf0540 575 /* Avoid overflow for large HZ */
c40c94a3 576 if ((ulong)CONFIG_SYS_HZ > 100000)
ddcf0540 577 tout *= (ulong)CONFIG_SYS_HZ / 1000;
c40c94a3
RA		 578 else
579 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
be60a902 580#endif
5653fc33 581
be60a902 582 /* Wait for command completion */
65cc0e2a 583#ifdef CFG_SYS_LOW_RES_TIMER
22d6c8fa 584 reset_timer();
e110c4fe 585#endif
188a5565 586 start = get_timer(0);
29caf930 587 schedule();
188a5565
MS		 588 while (flash_is_busy(info, sector)) {
589 if (get_timer(start) > tout) {
590 printf("Flash %s timeout at address %lx data %lx\n",
c0350fbf
MS		 591 prompt, info->start[sector],
592 flash_read_long(info, sector, 0));
188a5565 593 flash_write_cmd(info, sector, 0, info->cmd_reset);
e303be2d 594 udelay(1);
9dbaebcf 595 return ERR_TIMEOUT;
5653fc33 596 }
188a5565 597 udelay(1); /* also triggers watchdog */
5653fc33 598 }
be60a902
HS		 599 return ERR_OK;
600}
5653fc33 601
be60a902
HS		 602/*-----------------------------------------------------------------------
603 * Wait for XSR.7 to be set, if it times out print an error, otherwise
604 * do a full status check.
605 *
606 * This routine sets the flash to read-array mode.
607 */
ca2b07a8 608static int flash_full_status_check(flash_info_t *info, flash_sect_t sector,
c0350fbf 609 ulong tout, char *prompt)
be60a902
HS		 610{
611 int retcode;
5653fc33 612
188a5565 613 retcode = flash_status_check(info, sector, tout, prompt);
be60a902 614 switch (info->vendor) {
9c048b52 615 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 616 case CFI_CMDSET_INTEL_EXTENDED:
617 case CFI_CMDSET_INTEL_STANDARD:
4f89da49 618 if (retcode == ERR_OK &&
c0350fbf 619 !flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
be60a902 620 retcode = ERR_INVAL;
188a5565 621 printf("Flash %s error at address %lx\n", prompt,
c0350fbf 622 info->start[sector]);
188a5565 623 if (flash_isset(info, sector, 0, FLASH_STATUS_ECLBS |
be60a902 624 FLASH_STATUS_PSLBS)) {
188a5565
MS		 625 puts("Command Sequence Error.\n");
626 } else if (flash_isset(info, sector, 0,
be60a902 627 FLASH_STATUS_ECLBS)) {
188a5565 628 puts("Block Erase Error.\n");
be60a902 629 retcode = ERR_NOT_ERASED;
188a5565 630 } else if (flash_isset(info, sector, 0,
be60a902 631 FLASH_STATUS_PSLBS)) {
188a5565 632 puts("Locking Error\n");
5653fc33 633 }
188a5565
MS		 634 if (flash_isset(info, sector, 0, FLASH_STATUS_DPS)) {
635 puts("Block locked.\n");
be60a902
HS		 636 retcode = ERR_PROTECTED;
637 }
188a5565
MS		 638 if (flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
639 puts("Vpp Low Error.\n");
5653fc33 640 }
188a5565 641 flash_write_cmd(info, sector, 0, info->cmd_reset);
a90b9575 642 udelay(1);
be60a902
HS		 643 break;
644 default:
645 break;
5653fc33 646 }
be60a902 647 return retcode;
5653fc33
WD		 648}
649
e5720823
TC		 650static int use_flash_status_poll(flash_info_t *info)
651{
652#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
653 if (info->vendor == CFI_CMDSET_AMD_EXTENDED ||
654 info->vendor == CFI_CMDSET_AMD_STANDARD)
655 return 1;
656#endif
657 return 0;
658}
659
660static int flash_status_poll(flash_info_t *info, void *src, void *dst,
661 ulong tout, char *prompt)
662{
663#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL
664 ulong start;
665 int ready;
666
667#if CONFIG_SYS_HZ != 1000
ddcf0540 668 /* Avoid overflow for large HZ */
e5720823 669 if ((ulong)CONFIG_SYS_HZ > 100000)
ddcf0540 670 tout *= (ulong)CONFIG_SYS_HZ / 1000;
e5720823
TC		 671 else
672 tout = DIV_ROUND_UP(tout * (ulong)CONFIG_SYS_HZ, 1000);
673#endif
674
675 /* Wait for command completion */
65cc0e2a 676#ifdef CFG_SYS_LOW_RES_TIMER
22d6c8fa 677 reset_timer();
e110c4fe 678#endif
e5720823 679 start = get_timer(0);
29caf930 680 schedule();
e5720823
TC		 681 while (1) {
682 switch (info->portwidth) {
683 case FLASH_CFI_8BIT:
684 ready = flash_read8(dst) == flash_read8(src);
685 break;
686 case FLASH_CFI_16BIT:
687 ready = flash_read16(dst) == flash_read16(src);
688 break;
689 case FLASH_CFI_32BIT:
690 ready = flash_read32(dst) == flash_read32(src);
691 break;
692 case FLASH_CFI_64BIT:
693 ready = flash_read64(dst) == flash_read64(src);
694 break;
695 default:
696 ready = 0;
697 break;
698 }
699 if (ready)
700 break;
701 if (get_timer(start) > tout) {
702 printf("Flash %s timeout at address %lx data %lx\n",
703 prompt, (ulong)dst, (ulong)flash_read8(dst));
9dbaebcf 704 return ERR_TIMEOUT;
e5720823
TC		 705 }
706 udelay(1); /* also triggers watchdog */
707 }
708#endif /* CONFIG_SYS_CFI_FLASH_STATUS_POLL */
709 return ERR_OK;
710}
711
5653fc33
WD		 712/*-----------------------------------------------------------------------
713 */
ca2b07a8 714static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c)
5653fc33 715{
65cc0e2a 716#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 717 unsigned short w;
718 unsigned int l;
719 unsigned long long ll;
720#endif
5653fc33 721
be60a902
HS		 722 switch (info->portwidth) {
723 case FLASH_CFI_8BIT:
622b9527 724 cword->w8 = c;
be60a902
HS		 725 break;
726 case FLASH_CFI_16BIT:
65cc0e2a 727#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 728 w = c;
729 w <<= 8;
622b9527 730 cword->w16 = (cword->w16 >> 8) | w;
be60a902 731#else
622b9527 732 cword->w16 = (cword->w16 << 8) | c;
81b20ccc 733#endif
be60a902
HS		 734 break;
735 case FLASH_CFI_32BIT:
65cc0e2a 736#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 737 l = c;
738 l <<= 24;
622b9527 739 cword->w32 = (cword->w32 >> 8) | l;
be60a902 740#else
622b9527 741 cword->w32 = (cword->w32 << 8) | c;
be60a902
HS		 742#endif
743 break;
744 case FLASH_CFI_64BIT:
65cc0e2a 745#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 746 ll = c;
747 ll <<= 56;
622b9527 748 cword->w64 = (cword->w64 >> 8) | ll;
be60a902 749#else
622b9527 750 cword->w64 = (cword->w64 << 8) | c;
be60a902
HS		 751#endif
752 break;
260421a2 753 }
be60a902 754}
5653fc33 755
0f8e851e
JG		 756/*
757 * Loop through the sector table starting from the previously found sector.
758 * Searches forwards or backwards, dependent on the passed address.
be60a902 759 */
ca2b07a8 760static flash_sect_t find_sector(flash_info_t *info, ulong addr)
be60a902 761{
11dc4010 762 static flash_sect_t saved_sector; /* previously found sector */
e303be2d 763 static flash_info_t *saved_info; /* previously used flash bank */
0f8e851e
JG		 764 flash_sect_t sector = saved_sector;
765
4f89da49 766 if (info != saved_info || sector >= info->sector_count)
e303be2d
SR		 767 sector = 0;
768
5701ba82 769 while ((sector < info->sector_count - 1) &&
c0350fbf 770 (info->start[sector] < addr))
0f8e851e
JG		 771 sector++;
772 while ((info->start[sector] > addr) && (sector > 0))
773 /*
774 * also decrements the sector in case of an overshot
775 * in the first loop
776 */
777 sector--;
778
779 saved_sector = sector;
e303be2d 780 saved_info = info;
be60a902 781 return sector;
5653fc33
WD		 782}
783
784/*-----------------------------------------------------------------------
5653fc33 785 */
c0350fbf 786static int flash_write_cfiword(flash_info_t *info, ulong dest, cfiword_t cword)
5653fc33 787{
09ce9921 788 void *dstaddr = (void *)dest;
be60a902 789 int flag;
a7292871
JG		 790 flash_sect_t sect = 0;
791 char sect_found = 0;
5653fc33 792
be60a902
HS		 793 /* Check if Flash is (sufficiently) erased */
794 switch (info->portwidth) {
795 case FLASH_CFI_8BIT:
622b9527 796 flag = ((flash_read8(dstaddr) & cword.w8) == cword.w8);
be60a902
HS		 797 break;
798 case FLASH_CFI_16BIT:
622b9527 799 flag = ((flash_read16(dstaddr) & cword.w16) == cword.w16);
be60a902
HS		 800 break;
801 case FLASH_CFI_32BIT:
622b9527 802 flag = ((flash_read32(dstaddr) & cword.w32) == cword.w32);
be60a902
HS		 803 break;
804 case FLASH_CFI_64BIT:
622b9527 805 flag = ((flash_read64(dstaddr) & cword.w64) == cword.w64);
be60a902
HS		 806 break;
807 default:
12d30aa7
HS		 808 flag = 0;
809 break;
5653fc33 810 }
09ce9921 811 if (!flag)
0dc80e27 812 return ERR_NOT_ERASED;
5653fc33 813
be60a902 814 /* Disable interrupts which might cause a timeout here */
188a5565 815 flag = disable_interrupts();
79b4cda0 816
be60a902 817 switch (info->vendor) {
9c048b52 818 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 819 case CFI_CMDSET_INTEL_EXTENDED:
820 case CFI_CMDSET_INTEL_STANDARD:
188a5565
MS		 821 flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
822 flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
be60a902
HS		 823 break;
824 case CFI_CMDSET_AMD_EXTENDED:
825 case CFI_CMDSET_AMD_STANDARD:
0d01f66d 826 sect = find_sector(info, dest);
188a5565
MS		 827 flash_unlock_seq(info, sect);
828 flash_write_cmd(info, sect, info->addr_unlock1, AMD_CMD_WRITE);
a7292871 829 sect_found = 1;
be60a902 830 break;
b4db4a76
PYC		 831#ifdef CONFIG_FLASH_CFI_LEGACY
832 case CFI_CMDSET_AMD_LEGACY:
833 sect = find_sector(info, dest);
188a5565
MS		 834 flash_unlock_seq(info, 0);
835 flash_write_cmd(info, 0, info->addr_unlock1, AMD_CMD_WRITE);
b4db4a76
PYC		 836 sect_found = 1;
837 break;
838#endif
5653fc33
WD		 839 }
840
be60a902
HS		 841 switch (info->portwidth) {
842 case FLASH_CFI_8BIT:
622b9527 843 flash_write8(cword.w8, dstaddr);
be60a902
HS		 844 break;
845 case FLASH_CFI_16BIT:
622b9527 846 flash_write16(cword.w16, dstaddr);
be60a902
HS		 847 break;
848 case FLASH_CFI_32BIT:
622b9527 849 flash_write32(cword.w32, dstaddr);
be60a902
HS		 850 break;
851 case FLASH_CFI_64BIT:
622b9527 852 flash_write64(cword.w64, dstaddr);
be60a902 853 break;
5653fc33
WD		 854 }
855
be60a902
HS		 856 /* re-enable interrupts if necessary */
857 if (flag)
188a5565 858 enable_interrupts();
5653fc33 859
a7292871 860 if (!sect_found)
188a5565 861 sect = find_sector(info, dest);
a7292871 862
e5720823
TC		 863 if (use_flash_status_poll(info))
864 return flash_status_poll(info, &cword, dstaddr,
865 info->write_tout, "write");
866 else
867 return flash_full_status_check(info, sect,
868 info->write_tout, "write");
5653fc33
WD		 869}
870
6d0f6bcf 871#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
5653fc33 872
ca2b07a8 873static int flash_write_cfibuffer(flash_info_t *info, ulong dest, uchar *cp,
c0350fbf 874 int len)
5653fc33 875{
be60a902
HS		 876 flash_sect_t sector;
877 int cnt;
878 int retcode;
5312838d
MS		 879 u8 *src = cp;
880 u8 *dst = (u8 *)dest;
881 u8 *dst2 = dst;
85c344e5 882 int flag = 1;
96ef831f
GL		 883 uint offset = 0;
884 unsigned int shift;
9c048b52 885 uchar write_cmd;
cdbaefb5 886
0dc80e27
SR		 887 switch (info->portwidth) {
888 case FLASH_CFI_8BIT:
96ef831f 889 shift = 0;
0dc80e27
SR		 890 break;
891 case FLASH_CFI_16BIT:
96ef831f 892 shift = 1;
0dc80e27
SR		 893 break;
894 case FLASH_CFI_32BIT:
96ef831f 895 shift = 2;
0dc80e27
SR		 896 break;
897 case FLASH_CFI_64BIT:
96ef831f 898 shift = 3;
0dc80e27
SR		 899 break;
900 default:
901 retcode = ERR_INVAL;
902 goto out_unmap;
903 }
904
96ef831f
GL		 905 cnt = len >> shift;
906
85c344e5 907 while ((cnt-- > 0) && (flag == 1)) {
0dc80e27
SR		 908 switch (info->portwidth) {
909 case FLASH_CFI_8BIT:
910 flag = ((flash_read8(dst2) & flash_read8(src)) ==
911 flash_read8(src));
912 src += 1, dst2 += 1;
913 break;
914 case FLASH_CFI_16BIT:
915 flag = ((flash_read16(dst2) & flash_read16(src)) ==
916 flash_read16(src));
917 src += 2, dst2 += 2;
918 break;
919 case FLASH_CFI_32BIT:
920 flag = ((flash_read32(dst2) & flash_read32(src)) ==
921 flash_read32(src));
922 src += 4, dst2 += 4;
923 break;
924 case FLASH_CFI_64BIT:
925 flag = ((flash_read64(dst2) & flash_read64(src)) ==
926 flash_read64(src));
927 src += 8, dst2 += 8;
928 break;
929 }
930 }
931 if (!flag) {
932 retcode = ERR_NOT_ERASED;
933 goto out_unmap;
934 }
935
936 src = cp;
188a5565 937 sector = find_sector(info, dest);
bf9e3b38
WD		 938
939 switch (info->vendor) {
9c048b52 940 case CFI_CMDSET_INTEL_PROG_REGIONS:
5653fc33
WD		 941 case CFI_CMDSET_INTEL_STANDARD:
942 case CFI_CMDSET_INTEL_EXTENDED:
9c048b52 943 write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ?
ddcf0540
MS		 944 FLASH_CMD_WRITE_BUFFER_PROG :
945 FLASH_CMD_WRITE_TO_BUFFER;
188a5565
MS		 946 flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
947 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS);
948 flash_write_cmd(info, sector, 0, write_cmd);
949 retcode = flash_status_check(info, sector,
c0350fbf
MS		 950 info->buffer_write_tout,
951 "write to buffer");
be60a902
HS		 952 if (retcode == ERR_OK) {
953 /* reduce the number of loops by the width of
a6d18f27
MS		 954 * the port
955 */
96ef831f 956 cnt = len >> shift;
188a5565 957 flash_write_cmd(info, sector, 0, cnt - 1);
be60a902
HS		 958 while (cnt-- > 0) {
959 switch (info->portwidth) {
960 case FLASH_CFI_8BIT:
cdbaefb5
HS		 961 flash_write8(flash_read8(src), dst);
962 src += 1, dst += 1;
be60a902
HS		 963 break;
964 case FLASH_CFI_16BIT:
cdbaefb5
HS		 965 flash_write16(flash_read16(src), dst);
966 src += 2, dst += 2;
be60a902
HS		 967 break;
968 case FLASH_CFI_32BIT:
cdbaefb5
HS		 969 flash_write32(flash_read32(src), dst);
970 src += 4, dst += 4;
be60a902
HS		 971 break;
972 case FLASH_CFI_64BIT:
cdbaefb5
HS		 973 flash_write64(flash_read64(src), dst);
974 src += 8, dst += 8;
be60a902
HS		 975 break;
976 default:
12d30aa7
HS		 977 retcode = ERR_INVAL;
978 goto out_unmap;
be60a902
HS		 979 }
980 }
188a5565 981 flash_write_cmd(info, sector, 0,
c0350fbf 982 FLASH_CMD_WRITE_BUFFER_CONFIRM);
188a5565 983 retcode = flash_full_status_check(
be60a902
HS		 984 info, sector, info->buffer_write_tout,
985 "buffer write");
986 }
12d30aa7
HS		 987
988 break;
be60a902 989
5653fc33
WD		 990 case CFI_CMDSET_AMD_STANDARD:
991 case CFI_CMDSET_AMD_EXTENDED:
7570a0cc 992 flash_unlock_seq(info, sector);
96ef831f
GL		 993
994#ifdef CONFIG_FLASH_SPANSION_S29WS_N
995 offset = ((unsigned long)dst - info->start[sector]) >> shift;
996#endif
997 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER);
998 cnt = len >> shift;
7dedefdf 999 flash_write_cmd(info, sector, offset, cnt - 1);
be60a902
HS		 1000
1001 switch (info->portwidth) {
1002 case FLASH_CFI_8BIT:
cdbaefb5
HS		 1003 while (cnt-- > 0) {
1004 flash_write8(flash_read8(src), dst);
1005 src += 1, dst += 1;
1006 }
be60a902
HS		 1007 break;
1008 case FLASH_CFI_16BIT:
cdbaefb5
HS		 1009 while (cnt-- > 0) {
1010 flash_write16(flash_read16(src), dst);
1011 src += 2, dst += 2;
1012 }
be60a902
HS		 1013 break;
1014 case FLASH_CFI_32BIT:
cdbaefb5
HS		 1015 while (cnt-- > 0) {
1016 flash_write32(flash_read32(src), dst);
1017 src += 4, dst += 4;
1018 }
be60a902
HS		 1019 break;
1020 case FLASH_CFI_64BIT:
cdbaefb5
HS		 1021 while (cnt-- > 0) {
1022 flash_write64(flash_read64(src), dst);
1023 src += 8, dst += 8;
1024 }
be60a902
HS		 1025 break;
1026 default:
12d30aa7
HS		 1027 retcode = ERR_INVAL;
1028 goto out_unmap;
be60a902
HS		 1029 }
1030
188a5565 1031 flash_write_cmd(info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
e5720823
TC		 1032 if (use_flash_status_poll(info))
1033 retcode = flash_status_poll(info, src - (1 << shift),
1034 dst - (1 << shift),
1035 info->buffer_write_tout,
1036 "buffer write");
1037 else
1038 retcode = flash_full_status_check(info, sector,
1039 info->buffer_write_tout,
1040 "buffer write");
12d30aa7 1041 break;
be60a902 1042
5653fc33 1043 default:
188a5565 1044 debug("Unknown Command Set\n");
12d30aa7
HS		 1045 retcode = ERR_INVAL;
1046 break;
5653fc33 1047 }
12d30aa7
HS		 1048
1049out_unmap:
12d30aa7 1050 return retcode;
5653fc33 1051}
6d0f6bcf 1052#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
be60a902 1053
5653fc33 1054/*-----------------------------------------------------------------------
5653fc33 1055 */
ca2b07a8 1056int flash_erase(flash_info_t *info, int s_first, int s_last)
5653fc33 1057{
be60a902
HS		 1058 int rcode = 0;
1059 int prot;
1060 flash_sect_t sect;
e5720823 1061 int st;
5653fc33 1062
be60a902 1063 if (info->flash_id != FLASH_MAN_CFI) {
188a5565 1064 puts("Can't erase unknown flash type - aborted\n");
be60a902
HS		 1065 return 1;
1066 }
4f89da49 1067 if (s_first < 0 || s_first > s_last) {
188a5565 1068 puts("- no sectors to erase\n");
be60a902
HS		 1069 return 1;
1070 }
2662b40c 1071
be60a902 1072 prot = 0;
0412e903
MS		 1073 for (sect = s_first; sect <= s_last; ++sect)
1074 if (info->protect[sect])
be60a902 1075 prot++;
be60a902 1076 if (prot) {
188a5565 1077 printf("- Warning: %d protected sectors will not be erased!\n",
c0350fbf 1078 prot);
6ea808ef 1079 } else if (flash_verbose) {
188a5565 1080 putc('\n');
be60a902 1081 }
bf9e3b38 1082
be60a902 1083 for (sect = s_first; sect <= s_last; sect++) {
de15a06a
JH		 1084 if (ctrlc()) {
1085 printf("\n");
1086 return 1;
1087 }
1088
be60a902 1089 if (info->protect[sect] == 0) { /* not protected */
6822a647
JH		 1090#ifdef CONFIG_SYS_FLASH_CHECK_BLANK_BEFORE_ERASE
1091 int k;
1092 int size;
1093 int erased;
1094 u32 *flash;
1095
1096 /*
1097 * Check if whole sector is erased
1098 */
1099 size = flash_sector_size(info, sect);
1100 erased = 1;
1101 flash = (u32 *)info->start[sect];
1102 /* divide by 4 for longword access */
1103 size = size >> 2;
1104 for (k = 0; k < size; k++) {
1105 if (flash_read32(flash++) != 0xffffffff) {
1106 erased = 0;
1107 break;
1108 }
1109 }
1110 if (erased) {
1111 if (flash_verbose)
1112 putc(',');
1113 continue;
1114 }
1115#endif
be60a902 1116 switch (info->vendor) {
9c048b52 1117 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 1118 case CFI_CMDSET_INTEL_STANDARD:
1119 case CFI_CMDSET_INTEL_EXTENDED:
188a5565 1120 flash_write_cmd(info, sect, 0,
c0350fbf 1121 FLASH_CMD_CLEAR_STATUS);
188a5565 1122 flash_write_cmd(info, sect, 0,
c0350fbf 1123 FLASH_CMD_BLOCK_ERASE);
188a5565 1124 flash_write_cmd(info, sect, 0,
c0350fbf 1125 FLASH_CMD_ERASE_CONFIRM);
be60a902
HS		 1126 break;
1127 case CFI_CMDSET_AMD_STANDARD:
1128 case CFI_CMDSET_AMD_EXTENDED:
188a5565
MS		 1129 flash_unlock_seq(info, sect);
1130 flash_write_cmd(info, sect,
be60a902
HS		 1131 info->addr_unlock1,
1132 AMD_CMD_ERASE_START);
188a5565
MS		 1133 flash_unlock_seq(info, sect);
1134 flash_write_cmd(info, sect, 0,
c0350fbf 1135 info->cmd_erase_sector);
be60a902
HS		 1136 break;
1137#ifdef CONFIG_FLASH_CFI_LEGACY
1138 case CFI_CMDSET_AMD_LEGACY:
188a5565
MS		 1139 flash_unlock_seq(info, 0);
1140 flash_write_cmd(info, 0, info->addr_unlock1,
be60a902 1141 AMD_CMD_ERASE_START);
188a5565
MS		 1142 flash_unlock_seq(info, 0);
1143 flash_write_cmd(info, sect, 0,
be60a902
HS		 1144 AMD_CMD_ERASE_SECTOR);
1145 break;
1146#endif
1147 default:
9f720216 1148 debug("Unknown flash vendor %d\n",
c0350fbf 1149 info->vendor);
be60a902 1150 break;
bf9e3b38 1151 }
be60a902 1152
e5720823 1153 if (use_flash_status_poll(info)) {
11dc4010 1154 cfiword_t cword;
e5720823 1155 void *dest;
7223a8cb 1156
622b9527 1157 cword.w64 = 0xffffffffffffffffULL;
e5720823
TC		 1158 dest = flash_map(info, sect, 0);
1159 st = flash_status_poll(info, &cword, dest,
ddcf0540
MS		 1160 info->erase_blk_tout,
1161 "erase");
e5720823 1162 flash_unmap(info, sect, 0, dest);
12d7fed9 1163 } else {
e5720823
TC		 1164 st = flash_full_status_check(info, sect,
1165 info->erase_blk_tout,
1166 "erase");
12d7fed9
MS		 1167 }
1168
e5720823 1169 if (st)
be60a902 1170 rcode = 1;
e5720823 1171 else if (flash_verbose)
188a5565 1172 putc('.');
5653fc33 1173 }
5653fc33 1174 }
6ea808ef
PZ		 1175
1176 if (flash_verbose)
188a5565 1177 puts(" done\n");
6ea808ef 1178
be60a902 1179 return rcode;
5653fc33 1180}
bf9e3b38 1181
70084df7
SR		 1182#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
1183static int sector_erased(flash_info_t *info, int i)
1184{
1185 int k;
1186 int size;
4d2ca9d6 1187 u32 *flash;
70084df7
SR		 1188
1189 /*
1190 * Check if whole sector is erased
1191 */
1192 size = flash_sector_size(info, i);
4d2ca9d6 1193 flash = (u32 *)info->start[i];
70084df7
SR		 1194 /* divide by 4 for longword access */
1195 size = size >> 2;
1196
1197 for (k = 0; k < size; k++) {
4d2ca9d6 1198 if (flash_read32(flash++) != 0xffffffff)
70084df7
SR		 1199 return 0; /* not erased */
1200 }
1201
1202 return 1; /* erased */
1203}
1204#endif /* CONFIG_SYS_FLASH_EMPTY_INFO */
1205
ca2b07a8 1206void flash_print_info(flash_info_t *info)
5653fc33 1207{
be60a902 1208 int i;
4d13cbad 1209
be60a902 1210 if (info->flash_id != FLASH_MAN_CFI) {
188a5565 1211 puts("missing or unknown FLASH type\n");
be60a902
HS		 1212 return;
1213 }
1214
188a5565 1215 printf("%s flash (%d x %d)",
c0350fbf
MS		 1216 info->name,
1217 (info->portwidth << 3), (info->chipwidth << 3));
640f4e35 1218 if (info->size < 1024 * 1024)
188a5565 1219 printf(" Size: %ld kB in %d Sectors\n",
c0350fbf 1220 info->size >> 10, info->sector_count);
be60a902 1221 else
188a5565 1222 printf(" Size: %ld MB in %d Sectors\n",
c0350fbf 1223 info->size >> 20, info->sector_count);
188a5565 1224 printf(" ");
be60a902 1225 switch (info->vendor) {
dde0913b
MS		 1226 case CFI_CMDSET_INTEL_PROG_REGIONS:
1227 printf("Intel Prog Regions");
1228 break;
1229 case CFI_CMDSET_INTEL_STANDARD:
1230 printf("Intel Standard");
1231 break;
1232 case CFI_CMDSET_INTEL_EXTENDED:
1233 printf("Intel Extended");
1234 break;
1235 case CFI_CMDSET_AMD_STANDARD:
1236 printf("AMD Standard");
1237 break;
1238 case CFI_CMDSET_AMD_EXTENDED:
1239 printf("AMD Extended");
1240 break;
be60a902 1241#ifdef CONFIG_FLASH_CFI_LEGACY
dde0913b
MS		 1242 case CFI_CMDSET_AMD_LEGACY:
1243 printf("AMD Legacy");
1244 break;
4d13cbad 1245#endif
dde0913b
MS		 1246 default:
1247 printf("Unknown (%d)", info->vendor);
1248 break;
be60a902 1249 }
188a5565 1250 printf(" command set, Manufacturer ID: 0x%02X, Device ID: 0x",
c0350fbf 1251 info->manufacturer_id);
188a5565 1252 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
c0350fbf 1253 info->device_id);
5b448adb
HS		 1254 if ((info->device_id & 0xff) == 0x7E) {
1255 printf(info->chipwidth == FLASH_CFI_16BIT ? "%04X" : "%02X",
c0350fbf 1256 info->device_id2);
be60a902 1257 }
4f89da49 1258 if (info->vendor == CFI_CMDSET_AMD_STANDARD && info->legacy_unlock)
d2af028d 1259 printf("\n Advanced Sector Protection (PPB) enabled");
188a5565 1260 printf("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
c0350fbf 1261 info->erase_blk_tout, info->write_tout);
be60a902 1262 if (info->buffer_size > 1) {
876c52f3 1263 printf(" Buffer write timeout: %ld ms, ",
c0350fbf 1264 info->buffer_write_tout);
876c52f3 1265 printf("buffer size: %d bytes\n", info->buffer_size);
5653fc33 1266 }
5653fc33 1267
188a5565 1268 puts("\n Sector Start Addresses:");
be60a902 1269 for (i = 0; i < info->sector_count; ++i) {
2e97394a 1270 if (ctrlc())
70084df7 1271 break;
be60a902 1272 if ((i % 5) == 0)
70084df7 1273 putc('\n');
6d0f6bcf 1274#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
be60a902 1275 /* print empty and read-only info */
188a5565 1276 printf(" %08lX %c %s ",
c0350fbf
MS		 1277 info->start[i],
1278 sector_erased(info, i) ? 'E' : ' ',
1279 info->protect[i] ? "RO" : " ");
6d0f6bcf 1280#else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */
188a5565 1281 printf(" %08lX %s ",
c0350fbf
MS		 1282 info->start[i],
1283 info->protect[i] ? "RO" : " ");
bf9e3b38 1284#endif
be60a902 1285 }
188a5565 1286 putc('\n');
5653fc33
WD		 1287}
1288
9a042e9c
JVB		 1289/*-----------------------------------------------------------------------
1290 * This is used in a few places in write_buf() to show programming
1291 * progress. Making it a function is nasty because it needs to do side
1292 * effect updates to digit and dots. Repeated code is nasty too, so
1293 * we define it once here.
1294 */
98fbad63 1295#if CONFIG_FLASH_SHOW_PROGRESS
f0105727 1296#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \
6ea808ef
PZ		 1297 if (flash_verbose) { \
1298 dots -= dots_sub; \
4f89da49 1299 if (scale > 0 && dots <= 0) { \
6ea808ef 1300 if ((digit % 5) == 0) \
188a5565 1301 printf("%d", digit / 5); \
6ea808ef 1302 else \
188a5565 1303 putc('.'); \
6ea808ef
PZ		 1304 digit--; \
1305 dots += scale; \
1306 } \
9a042e9c 1307 }
f0105727
SR		 1308#else
1309#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub)
1310#endif
9a042e9c 1311
be60a902
HS		 1312/*-----------------------------------------------------------------------
1313 * Copy memory to flash, returns:
1314 * 0 - OK
1315 * 1 - write timeout
1316 * 2 - Flash not erased
5653fc33 1317 */
ca2b07a8 1318int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
5653fc33 1319{
be60a902 1320 ulong wp;
12d30aa7 1321 uchar *p;
be60a902 1322 int aln;
5653fc33 1323 cfiword_t cword;
be60a902 1324 int i, rc;
6d0f6bcf 1325#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
be60a902 1326 int buffered_size;
5653fc33 1327#endif
98fbad63 1328#if CONFIG_FLASH_SHOW_PROGRESS
9a042e9c
JVB		 1329 int digit = CONFIG_FLASH_SHOW_PROGRESS;
1330 int scale = 0;
1331 int dots = 0;
1332
1333 /*
1334 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes.
1335 */
1336 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) {
1337 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) /
1338 CONFIG_FLASH_SHOW_PROGRESS);
1339 }
1340#endif
1341
be60a902
HS		 1342 /* get lower aligned address */
1343 wp = (addr & ~(info->portwidth - 1));
3a197b2f 1344
be60a902 1345 /* handle unaligned start */
d3525b6b
MS		 1346 aln = addr - wp;
1347 if (aln != 0) {
622b9527 1348 cword.w32 = 0;
09ce9921 1349 p = (uchar *)wp;
12d30aa7 1350 for (i = 0; i < aln; ++i)
188a5565 1351 flash_add_byte(info, &cword, flash_read8(p + i));
5653fc33 1352
be60a902 1353 for (; (i < info->portwidth) && (cnt > 0); i++) {
188a5565 1354 flash_add_byte(info, &cword, *src++);
be60a902 1355 cnt--;
be60a902 1356 }
12d30aa7 1357 for (; (cnt == 0) && (i < info->portwidth); ++i)
188a5565 1358 flash_add_byte(info, &cword, flash_read8(p + i));
12d30aa7 1359
188a5565 1360 rc = flash_write_cfiword(info, wp, cword);
12d30aa7 1361 if (rc != 0)
be60a902 1362 return rc;
12d30aa7
HS		 1363
1364 wp += i;
f0105727 1365 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
be60a902
HS		 1366 }
1367
1368 /* handle the aligned part */
6d0f6bcf 1369#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
be60a902
HS		 1370 buffered_size = (info->portwidth / info->chipwidth);
1371 buffered_size *= info->buffer_size;
1372 while (cnt >= info->portwidth) {
1373 /* prohibit buffer write when buffer_size is 1 */
1374 if (info->buffer_size == 1) {
622b9527 1375 cword.w32 = 0;
be60a902 1376 for (i = 0; i < info->portwidth; i++)
188a5565 1377 flash_add_byte(info, &cword, *src++);
d3525b6b
MS		 1378 rc = flash_write_cfiword(info, wp, cword);
1379 if (rc != 0)
be60a902
HS		 1380 return rc;
1381 wp += info->portwidth;
1382 cnt -= info->portwidth;
1383 continue;
1384 }
1385
1386 /* write buffer until next buffered_size aligned boundary */
1387 i = buffered_size - (wp % buffered_size);
1388 if (i > cnt)
1389 i = cnt;
d3525b6b
MS		 1390 rc = flash_write_cfibuffer(info, wp, src, i);
1391 if (rc != ERR_OK)
be60a902
HS		 1392 return rc;
1393 i -= i & (info->portwidth - 1);
1394 wp += i;
1395 src += i;
1396 cnt -= i;
f0105727 1397 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
de15a06a
JH		 1398 /* Only check every once in a while */
1399 if ((cnt & 0xFFFF) < buffered_size && ctrlc())
1400 return ERR_ABORTED;
be60a902
HS		 1401 }
1402#else
1403 while (cnt >= info->portwidth) {
622b9527 1404 cword.w32 = 0;
0412e903 1405 for (i = 0; i < info->portwidth; i++)
188a5565 1406 flash_add_byte(info, &cword, *src++);
d3525b6b
MS		 1407 rc = flash_write_cfiword(info, wp, cword);
1408 if (rc != 0)
be60a902
HS		 1409 return rc;
1410 wp += info->portwidth;
1411 cnt -= info->portwidth;
f0105727 1412 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth);
de15a06a
JH		 1413 /* Only check every once in a while */
1414 if ((cnt & 0xFFFF) < info->portwidth && ctrlc())
1415 return ERR_ABORTED;
be60a902 1416 }
6d0f6bcf 1417#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
9a042e9c 1418
0412e903 1419 if (cnt == 0)
be60a902 1420 return (0);
be60a902
HS		 1421
1422 /*
1423 * handle unaligned tail bytes
1424 */
622b9527 1425 cword.w32 = 0;
09ce9921 1426 p = (uchar *)wp;
12d30aa7 1427 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) {
188a5565 1428 flash_add_byte(info, &cword, *src++);
be60a902
HS		 1429 --cnt;
1430 }
12d30aa7 1431 for (; i < info->portwidth; ++i)
188a5565 1432 flash_add_byte(info, &cword, flash_read8(p + i));
be60a902 1433
188a5565 1434 return flash_write_cfiword(info, wp, cword);
5653fc33 1435}
bf9e3b38 1436
20043a4c
SR		 1437static inline int manufact_match(flash_info_t *info, u32 manu)
1438{
1439 return info->manufacturer_id == ((manu & FLASH_VENDMASK) >> 16);
1440}
1441
5653fc33
WD		 1442/*-----------------------------------------------------------------------
1443 */
6d0f6bcf 1444#ifdef CONFIG_SYS_FLASH_PROTECTION
be60a902 1445
81316a90
HB		 1446static int cfi_protect_bugfix(flash_info_t *info, long sector, int prot)
1447{
88ecd8bf 1448 if (manufact_match(info, INTEL_MANUFACT) &&
c0350fbf 1449 info->device_id == NUMONYX_256MBIT) {
81316a90
HB		 1450 /*
1451 * see errata called
1452 * "Numonyx Axcell P33/P30 Specification Update" :)
1453 */
1454 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_ID);
1455 if (!flash_isequal(info, sector, FLASH_OFFSET_PROTECT,
1456 prot)) {
1457 /*
1458 * cmd must come before FLASH_CMD_PROTECT + 20us
1459 * Disable interrupts which might cause a timeout here.
1460 */
1461 int flag = disable_interrupts();
1462 unsigned short cmd;
1463
1464 if (prot)
1465 cmd = FLASH_CMD_PROTECT_SET;
1466 else
1467 cmd = FLASH_CMD_PROTECT_CLEAR;
58eab328
AP		 1468
1469 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
81316a90
HB		 1470 flash_write_cmd(info, sector, 0, cmd);
1471 /* re-enable interrupts if necessary */
1472 if (flag)
1473 enable_interrupts();
1474 }
1475 return 1;
1476 }
1477 return 0;
1478}
1479
ca2b07a8 1480int flash_real_protect(flash_info_t *info, long sector, int prot)
5653fc33 1481{
be60a902 1482 int retcode = 0;
5653fc33 1483
bc9019e1 1484 switch (info->vendor) {
dde0913b
MS		 1485 case CFI_CMDSET_INTEL_PROG_REGIONS:
1486 case CFI_CMDSET_INTEL_STANDARD:
1487 case CFI_CMDSET_INTEL_EXTENDED:
1488 if (!cfi_protect_bugfix(info, sector, prot)) {
1489 flash_write_cmd(info, sector, 0,
c0350fbf 1490 FLASH_CMD_CLEAR_STATUS);
dde0913b 1491 flash_write_cmd(info, sector, 0,
c0350fbf 1492 FLASH_CMD_PROTECT);
dde0913b 1493 if (prot)
81316a90 1494 flash_write_cmd(info, sector, 0,
c0350fbf 1495 FLASH_CMD_PROTECT_SET);
dde0913b 1496 else
81316a90 1497 flash_write_cmd(info, sector, 0,
c0350fbf 1498 FLASH_CMD_PROTECT_CLEAR);
dde0913b
MS		 1499 }
1500 break;
1501 case CFI_CMDSET_AMD_EXTENDED:
1502 case CFI_CMDSET_AMD_STANDARD:
1503 /* U-Boot only checks the first byte */
1504 if (manufact_match(info, ATM_MANUFACT)) {
1505 if (prot) {
1506 flash_unlock_seq(info, 0);
1507 flash_write_cmd(info, 0,
1508 info->addr_unlock1,
1509 ATM_CMD_SOFTLOCK_START);
1510 flash_unlock_seq(info, 0);
1511 flash_write_cmd(info, sector, 0,
1512 ATM_CMD_LOCK_SECT);
1513 } else {
1514 flash_write_cmd(info, 0,
1515 info->addr_unlock1,
1516 AMD_CMD_UNLOCK_START);
1517 if (info->device_id == ATM_ID_BV6416)
1518 flash_write_cmd(info, sector,
c0350fbf 1519 0, ATM_CMD_UNLOCK_SECT);
54652991 1520 }
dde0913b
MS		 1521 }
1522 if (info->legacy_unlock) {
1523 int flag = disable_interrupts();
1524 int lock_flag;
1525
1526 flash_unlock_seq(info, 0);
1527 flash_write_cmd(info, 0, info->addr_unlock1,
1528 AMD_CMD_SET_PPB_ENTRY);
1529 lock_flag = flash_isset(info, sector, 0, 0x01);
1530 if (prot) {
1531 if (lock_flag) {
188a5565 1532 flash_write_cmd(info, sector, 0,
c0350fbf 1533 AMD_CMD_PPB_LOCK_BC1);
dde0913b 1534 flash_write_cmd(info, sector, 0,
c0350fbf 1535 AMD_CMD_PPB_LOCK_BC2);
bc9019e1 1536 }
dde0913b 1537 debug("sector %ld %slocked\n", sector,
c0350fbf 1538 lock_flag ? "" : "already ");
dde0913b
MS		 1539 } else {
1540 if (!lock_flag) {
1541 debug("unlock %ld\n", sector);
1542 flash_write_cmd(info, 0, 0,
c0350fbf 1543 AMD_CMD_PPB_UNLOCK_BC1);
dde0913b 1544 flash_write_cmd(info, 0, 0,
c0350fbf 1545 AMD_CMD_PPB_UNLOCK_BC2);
66863b05 1546 }
dde0913b 1547 debug("sector %ld %sunlocked\n", sector,
c0350fbf 1548 !lock_flag ? "" : "already ");
66863b05 1549 }
dde0913b
MS		 1550 if (flag)
1551 enable_interrupts();
1552
1553 if (flash_status_check(info, sector,
c0350fbf
MS		 1554 info->erase_blk_tout,
1555 prot ? "protect" : "unprotect"))
dde0913b
MS		 1556 printf("status check error\n");
1557
1558 flash_write_cmd(info, 0, 0,
1559 AMD_CMD_SET_PPB_EXIT_BC1);
1560 flash_write_cmd(info, 0, 0,
1561 AMD_CMD_SET_PPB_EXIT_BC2);
1562 }
1563 break;
4e00acde 1564#ifdef CONFIG_FLASH_CFI_LEGACY
dde0913b
MS		 1565 case CFI_CMDSET_AMD_LEGACY:
1566 flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1567 flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
1568 if (prot)
ddcf0540
MS		 1569 flash_write_cmd(info, sector, 0,
1570 FLASH_CMD_PROTECT_SET);
dde0913b 1571 else
ddcf0540
MS		 1572 flash_write_cmd(info, sector, 0,
1573 FLASH_CMD_PROTECT_CLEAR);
4e00acde 1574#endif
bc9019e1 1575 };
bf9e3b38 1576
df4e813b
SR		 1577 /*
1578 * Flash needs to be in status register read mode for
1579 * flash_full_status_check() to work correctly
1580 */
1581 flash_write_cmd(info, sector, 0, FLASH_CMD_READ_STATUS);
d3525b6b 1582 retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
c0350fbf 1583 prot ? "protect" : "unprotect");
d3525b6b 1584 if (retcode == 0) {
be60a902
HS		 1585 info->protect[sector] = prot;
1586
1587 /*
1588 * On some of Intel's flash chips (marked via legacy_unlock)
1589 * unprotect unprotects all locking.
1590 */
4f89da49 1591 if (prot == 0 && info->legacy_unlock) {
be60a902
HS		 1592 flash_sect_t i;
1593
1594 for (i = 0; i < info->sector_count; i++) {
1595 if (info->protect[i])
188a5565 1596 flash_real_protect(info, i, 1);
be60a902 1597 }
5653fc33 1598 }
5653fc33 1599 }
be60a902 1600 return retcode;
5653fc33 1601}
bf9e3b38 1602
5653fc33 1603/*-----------------------------------------------------------------------
be60a902 1604 * flash_read_user_serial - read the OneTimeProgramming cells
5653fc33 1605 */
ca2b07a8 1606void flash_read_user_serial(flash_info_t *info, void *buffer, int offset,
c0350fbf 1607 int len)
5653fc33 1608{
be60a902
HS		 1609 uchar *src;
1610 uchar *dst;
bf9e3b38 1611
be60a902 1612 dst = buffer;
188a5565
MS		 1613 src = flash_map(info, 0, FLASH_OFFSET_USER_PROTECTION);
1614 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1615 memcpy(dst, src + offset, len);
1616 flash_write_cmd(info, 0, 0, info->cmd_reset);
a90b9575 1617 udelay(1);
12d30aa7 1618 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src);
5653fc33
WD		 1619}
1620
be60a902
HS		 1621/*
1622 * flash_read_factory_serial - read the device Id from the protection area
5653fc33 1623 */
ca2b07a8 1624void flash_read_factory_serial(flash_info_t *info, void *buffer, int offset,
c0350fbf 1625 int len)
5653fc33 1626{
be60a902 1627 uchar *src;
bf9e3b38 1628
188a5565
MS		 1629 src = flash_map(info, 0, FLASH_OFFSET_INTEL_PROTECTION);
1630 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1631 memcpy(buffer, src + offset, len);
1632 flash_write_cmd(info, 0, 0, info->cmd_reset);
a90b9575 1633 udelay(1);
12d30aa7 1634 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src);
5653fc33
WD		 1635}
1636
6d0f6bcf 1637#endif /* CONFIG_SYS_FLASH_PROTECTION */
be60a902 1638
0ddf06dd
HS		 1639/*-----------------------------------------------------------------------
1640 * Reverse the order of the erase regions in the CFI QRY structure.
1641 * This is needed for chips that are either a) correctly detected as
1642 * top-boot, or b) buggy.
1643 */
1644static void cfi_reverse_geometry(struct cfi_qry *qry)
1645{
1646 unsigned int i, j;
1647 u32 tmp;
1648
1649 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) {
4f89da49
MS		 1650 tmp = get_unaligned(&qry->erase_region_info[i]);
1651 put_unaligned(get_unaligned(&qry->erase_region_info[j]),
1652 &qry->erase_region_info[i]);
1653 put_unaligned(tmp, &qry->erase_region_info[j]);
0ddf06dd
HS		 1654 }
1655}
be60a902 1656
260421a2
SR		 1657/*-----------------------------------------------------------------------
1658 * read jedec ids from device and set corresponding fields in info struct
1659 *
1660 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct
1661 *
0ddf06dd
HS		 1662 */
1663static void cmdset_intel_read_jedec_ids(flash_info_t *info)
1664{
1665 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
a90b9575 1666 udelay(1);
0ddf06dd
HS		 1667 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1668 udelay(1000); /* some flash are slow to respond */
188a5565 1669 info->manufacturer_id = flash_read_uchar(info,
c0350fbf 1670 FLASH_OFFSET_MANUFACTURER_ID);
d77c7ac4 1671 info->device_id = (info->chipwidth == FLASH_CFI_16BIT) ?
188a5565
MS		 1672 flash_read_word(info, FLASH_OFFSET_DEVICE_ID) :
1673 flash_read_uchar(info, FLASH_OFFSET_DEVICE_ID);
0ddf06dd
HS		 1674 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1675}
1676
1677static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry)
1678{
1679 info->cmd_reset = FLASH_CMD_RESET;
1680
1681 cmdset_intel_read_jedec_ids(info);
1682 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1683
6d0f6bcf 1684#ifdef CONFIG_SYS_FLASH_PROTECTION
0ddf06dd
HS		 1685 /* read legacy lock/unlock bit from intel flash */
1686 if (info->ext_addr) {
c0350fbf
MS		 1687 info->legacy_unlock =
1688 flash_read_uchar(info, info->ext_addr + 5) & 0x08;
0ddf06dd
HS		 1689 }
1690#endif
1691
1692 return 0;
1693}
1694
1695static void cmdset_amd_read_jedec_ids(flash_info_t *info)
1696{
c8a9a82c
MS		 1697 ushort bank_id = 0;
1698 uchar manu_id;
2544f470 1699 uchar feature;
3a7b2c21 1700
0ddf06dd
HS		 1701 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1702 flash_unlock_seq(info, 0);
1703 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID);
1704 udelay(1000); /* some flash are slow to respond */
90447ecb 1705
c8a9a82c 1706 manu_id = flash_read_uchar(info, FLASH_OFFSET_MANUFACTURER_ID);
3a7b2c21 1707 /* JEDEC JEP106Z specifies ID codes up to bank 7 */
c8a9a82c
MS		 1708 while (manu_id == FLASH_CONTINUATION_CODE && bank_id < 0x800) {
1709 bank_id += 0x100;
1710 manu_id = flash_read_uchar(info,
c0350fbf 1711 bank_id | FLASH_OFFSET_MANUFACTURER_ID);
3a7b2c21 1712 }
c8a9a82c 1713 info->manufacturer_id = manu_id;
90447ecb 1714
2544f470
YS		 1715 debug("info->ext_addr = 0x%x, cfi_version = 0x%x\n",
1716 info->ext_addr, info->cfi_version);
1717 if (info->ext_addr && info->cfi_version >= 0x3134) {
1718 /* read software feature (at 0x53) */
1719 feature = flash_read_uchar(info, info->ext_addr + 0x13);
1720 debug("feature = 0x%x\n", feature);
1721 info->sr_supported = feature & 0x1;
1722 }
72443c7f 1723
b168386b 1724 switch (info->chipwidth) {
90447ecb 1725 case FLASH_CFI_8BIT:
188a5565 1726 info->device_id = flash_read_uchar(info,
c0350fbf 1727 FLASH_OFFSET_DEVICE_ID);
90447ecb
TK		 1728 if (info->device_id == 0x7E) {
1729 /* AMD 3-byte (expanded) device ids */
188a5565 1730 info->device_id2 = flash_read_uchar(info,
c0350fbf 1731 FLASH_OFFSET_DEVICE_ID2);
90447ecb 1732 info->device_id2 <<= 8;
188a5565 1733 info->device_id2 |= flash_read_uchar(info,
90447ecb
TK		 1734 FLASH_OFFSET_DEVICE_ID3);
1735 }
1736 break;
1737 case FLASH_CFI_16BIT:
188a5565 1738 info->device_id = flash_read_word(info,
c0350fbf 1739 FLASH_OFFSET_DEVICE_ID);
5b448adb
HS		 1740 if ((info->device_id & 0xff) == 0x7E) {
1741 /* AMD 3-byte (expanded) device ids */
188a5565 1742 info->device_id2 = flash_read_uchar(info,
c0350fbf 1743 FLASH_OFFSET_DEVICE_ID2);
5b448adb 1744 info->device_id2 <<= 8;
188a5565 1745 info->device_id2 |= flash_read_uchar(info,
5b448adb
HS		 1746 FLASH_OFFSET_DEVICE_ID3);
1747 }
90447ecb
TK		 1748 break;
1749 default:
1750 break;
0ddf06dd
HS		 1751 }
1752 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
a90b9575 1753 udelay(1);
0ddf06dd
HS		 1754}
1755
1756static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
1757{
1758 info->cmd_reset = AMD_CMD_RESET;
07b2c5c0 1759 info->cmd_erase_sector = AMD_CMD_ERASE_SECTOR;
0ddf06dd
HS		 1760
1761 cmdset_amd_read_jedec_ids(info);
1762 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1763
66863b05 1764#ifdef CONFIG_SYS_FLASH_PROTECTION
ac6b9115
SR		 1765 if (info->ext_addr) {
1766 /* read sector protect/unprotect scheme (at 0x49) */
1767 if (flash_read_uchar(info, info->ext_addr + 9) == 0x8)
66863b05
AG		 1768 info->legacy_unlock = 1;
1769 }
1770#endif
1771
0ddf06dd
HS		 1772 return 0;
1773}
1774
1775#ifdef CONFIG_FLASH_CFI_LEGACY
ca2b07a8 1776static void flash_read_jedec_ids(flash_info_t *info)
260421a2
SR		 1777{
1778 info->manufacturer_id = 0;
1779 info->device_id = 0;
1780 info->device_id2 = 0;
1781
1782 switch (info->vendor) {
9c048b52 1783 case CFI_CMDSET_INTEL_PROG_REGIONS:
260421a2
SR		 1784 case CFI_CMDSET_INTEL_STANDARD:
1785 case CFI_CMDSET_INTEL_EXTENDED:
8225d1e3 1786 cmdset_intel_read_jedec_ids(info);
260421a2
SR		 1787 break;
1788 case CFI_CMDSET_AMD_STANDARD:
1789 case CFI_CMDSET_AMD_EXTENDED:
8225d1e3 1790 cmdset_amd_read_jedec_ids(info);
260421a2
SR		 1791 break;
1792 default:
1793 break;
1794 }
1795}
1796
5653fc33 1797/*-----------------------------------------------------------------------
be60a902
HS		 1798 * Call board code to request info about non-CFI flash.
1799 * board_flash_get_legacy needs to fill in at least:
1800 * info->portwidth, info->chipwidth and info->interface for Jedec probing.
7e5b9b47 1801 */
09ce9921 1802static int flash_detect_legacy(phys_addr_t base, int banknum)
5653fc33 1803{
be60a902 1804 flash_info_t *info = &flash_info[banknum];
7e5b9b47 1805
be60a902
HS		 1806 if (board_flash_get_legacy(base, banknum, info)) {
1807 /* board code may have filled info completely. If not, we
a6d18f27
MS		 1808 * use JEDEC ID probing.
1809 */
be60a902
HS		 1810 if (!info->vendor) {
1811 int modes[] = {
1812 CFI_CMDSET_AMD_STANDARD,
1813 CFI_CMDSET_INTEL_STANDARD
1814 };
1815 int i;
7e5b9b47 1816
31bf0f57 1817 for (i = 0; i < ARRAY_SIZE(modes); i++) {
be60a902 1818 info->vendor = modes[i];
09ce9921
BB		 1819 info->start[0] =
1820 (ulong)map_physmem(base,
e1fb6d0d 1821 info->portwidth,
09ce9921 1822 MAP_NOCACHE);
88ecd8bf 1823 if (info->portwidth == FLASH_CFI_8BIT &&
c0350fbf 1824 info->interface == FLASH_CFI_X8X16) {
be60a902
HS		 1825 info->addr_unlock1 = 0x2AAA;
1826 info->addr_unlock2 = 0x5555;
1827 } else {
1828 info->addr_unlock1 = 0x5555;
1829 info->addr_unlock2 = 0x2AAA;
1830 }
1831 flash_read_jedec_ids(info);
1832 debug("JEDEC PROBE: ID %x %x %x\n",
c0350fbf
MS		 1833 info->manufacturer_id,
1834 info->device_id,
1835 info->device_id2);
09ce9921 1836 if (jedec_flash_match(info, info->start[0]))
be60a902 1837 break;
9860137f
MS		 1838
1839 unmap_physmem((void *)info->start[0],
1840 info->portwidth);
be60a902
HS		 1841 }
1842 }
1843
b168386b 1844 switch (info->vendor) {
9c048b52 1845 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 1846 case CFI_CMDSET_INTEL_STANDARD:
1847 case CFI_CMDSET_INTEL_EXTENDED:
1848 info->cmd_reset = FLASH_CMD_RESET;
1849 break;
1850 case CFI_CMDSET_AMD_STANDARD:
1851 case CFI_CMDSET_AMD_EXTENDED:
1852 case CFI_CMDSET_AMD_LEGACY:
1853 info->cmd_reset = AMD_CMD_RESET;
1854 break;
1855 }
1856 info->flash_id = FLASH_MAN_CFI;
1857 return 1;
1858 }
1859 return 0; /* use CFI */
1860}
1861#else
09ce9921 1862static inline int flash_detect_legacy(phys_addr_t base, int banknum)
be60a902
HS		 1863{
1864 return 0; /* use CFI */
1865}
1866#endif
1867
1868/*-----------------------------------------------------------------------
1869 * detect if flash is compatible with the Common Flash Interface (CFI)
1870 * http://www.jedec.org/download/search/jesd68.pdf
1871 */
c0350fbf
MS		 1872static void flash_read_cfi(flash_info_t *info, void *buf, unsigned int start,
1873 size_t len)
e23741f4
HS		 1874{
1875 u8 *p = buf;
1876 unsigned int i;
1877
1878 for (i = 0; i < len; i++)
e303be2d 1879 p[i] = flash_read_uchar(info, start + i);
e23741f4
HS		 1880}
1881
11dc4010 1882static void __flash_cmd_reset(flash_info_t *info)
fa36ae79
SR		 1883{
1884 /*
1885 * We do not yet know what kind of commandset to use, so we issue
1886 * the reset command in both Intel and AMD variants, in the hope
1887 * that AMD flash roms ignore the Intel command.
1888 */
1889 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
a90b9575 1890 udelay(1);
fa36ae79
SR		 1891 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1892}
7223a8cb 1893
fa36ae79 1894void flash_cmd_reset(flash_info_t *info)
640f4e35 1895 __attribute__((weak, alias("__flash_cmd_reset")));
fa36ae79 1896
ca2b07a8 1897static int __flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry)
be60a902
HS		 1898{
1899 int cfi_offset;
1900
e303be2d
SR		 1901 /* Issue FLASH reset command */
1902 flash_cmd_reset(info);
1903
31bf0f57 1904 for (cfi_offset = 0; cfi_offset < ARRAY_SIZE(flash_offset_cfi);
be60a902 1905 cfi_offset++) {
188a5565 1906 flash_write_cmd(info, 0, flash_offset_cfi[cfi_offset],
c0350fbf 1907 FLASH_CMD_CFI);
88ecd8bf 1908 if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') &&
ddcf0540
MS		 1909 flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
1910 flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
c0350fbf
MS		 1911 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP,
1912 sizeof(struct cfi_qry));
e23741f4 1913 info->interface = le16_to_cpu(qry->interface_desc);
53879b17
JT		 1914 /* Some flash chips can support multiple bus widths.
1915 * In this case, override the interface width and
1916 * limit it to the port width.
1917 */
1918 if ((info->interface == FLASH_CFI_X8X16) &&
1919 (info->portwidth == FLASH_CFI_8BIT)) {
1920 debug("Overriding 16-bit interface width to"
1921 " 8-bit port width\n");
1922 info->interface = FLASH_CFI_X8;
1923 } else if ((info->interface == FLASH_CFI_X16X32) &&
1924 (info->portwidth == FLASH_CFI_16BIT)) {
1925 debug("Overriding 16-bit interface width to"
1926 " 16-bit port width\n");
1927 info->interface = FLASH_CFI_X16;
1928 }
e303be2d 1929
be60a902 1930 info->cfi_offset = flash_offset_cfi[cfi_offset];
188a5565 1931 debug("device interface is %d\n",
c0350fbf 1932 info->interface);
53879b17
JT		 1933 debug("found port %d chip %d chip_lsb %d ",
1934 info->portwidth, info->chipwidth, info->chip_lsb);
188a5565 1935 debug("port %d bits chip %d bits\n",
c0350fbf
MS		 1936 info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1937 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
be60a902
HS		 1938
1939 /* calculate command offsets as in the Linux driver */
e303be2d
SR		 1940 info->addr_unlock1 = 0x555;
1941 info->addr_unlock2 = 0x2aa;
7e5b9b47
HS		 1942
1943 /*
1944 * modify the unlock address if we are
1945 * in compatibility mode
1946 */
b168386b 1947 if (/* x8/x16 in x8 mode */
4f89da49
MS		 1948 (info->chipwidth == FLASH_CFI_BY8 &&
1949 info->interface == FLASH_CFI_X8X16) ||
b168386b 1950 /* x16/x32 in x16 mode */
4f89da49 1951 (info->chipwidth == FLASH_CFI_BY16 &&
0cec0a12 1952 info->interface == FLASH_CFI_X16X32)) {
7e5b9b47
HS		 1953 info->addr_unlock1 = 0xaaa;
1954 info->addr_unlock2 = 0x555;
1955 }
1956
1957 info->name = "CFI conformant";
1958 return 1;
1959 }
1960 }
1961
1962 return 0;
1963}
1964
ca2b07a8 1965static int flash_detect_cfi(flash_info_t *info, struct cfi_qry *qry)
7e5b9b47 1966{
188a5565 1967 debug("flash detect cfi\n");
bf9e3b38 1968
6d0f6bcf 1969 for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH;
bf9e3b38
WD		 1970 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
1971 for (info->chipwidth = FLASH_CFI_BY8;
1972 info->chipwidth <= info->portwidth;
53879b17
JT		 1973 info->chipwidth <<= 1) {
1974 /*
1975 * First, try detection without shifting the addresses
1976 * for 8bit devices (16bit wide connection)
1977 */
1978 info->chip_lsb = 0;
1979 if (__flash_detect_cfi(info, qry))
1980 return 1;
1981
1982 /*
1983 * Not detected, so let's try with shifting
1984 * for 8bit devices
1985 */
1986 info->chip_lsb = 1;
e303be2d 1987 if (__flash_detect_cfi(info, qry))
7e5b9b47 1988 return 1;
53879b17 1989 }
5653fc33 1990 }
188a5565 1991 debug("not found\n");
5653fc33
WD		 1992 return 0;
1993}
bf9e3b38 1994
467bcee1
HS		 1995/*
1996 * Manufacturer-specific quirks. Add workarounds for geometry
1997 * reversal, etc. here.
1998 */
1999static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry)
2000{
2001 /* check if flash geometry needs reversal */
2002 if (qry->num_erase_regions > 1) {
2003 /* reverse geometry if top boot part */
2004 if (info->cfi_version < 0x3131) {
2005 /* CFI < 1.1, try to guess from device id */
2006 if ((info->device_id & 0x80) != 0)
2007 cfi_reverse_geometry(qry);
e303be2d 2008 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
467bcee1
HS		 2009 /* CFI >= 1.1, deduct from top/bottom flag */
2010 /* note: ext_addr is valid since cfi_version > 0 */
2011 cfi_reverse_geometry(qry);
2012 }
2013 }
2014}
2015
2016static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry)
2017{
2018 int reverse_geometry = 0;
2019
2020 /* Check the "top boot" bit in the PRI */
2021 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1))
2022 reverse_geometry = 1;
2023
2024 /* AT49BV6416(T) list the erase regions in the wrong order.
2025 * However, the device ID is identical with the non-broken
cb82a532 2026 * AT49BV642D they differ in the high byte.
467bcee1 2027 */
467bcee1
HS		 2028 if (info->device_id == 0xd6 || info->device_id == 0xd2)
2029 reverse_geometry = !reverse_geometry;
467bcee1
HS		 2030
2031 if (reverse_geometry)
2032 cfi_reverse_geometry(qry);
2033}
2034
e8eac437
RR		 2035static void flash_fixup_stm(flash_info_t *info, struct cfi_qry *qry)
2036{
2037 /* check if flash geometry needs reversal */
2038 if (qry->num_erase_regions > 1) {
2039 /* reverse geometry if top boot part */
2040 if (info->cfi_version < 0x3131) {
6a011ce8
MF		 2041 /* CFI < 1.1, guess by device id */
2042 if (info->device_id == 0x22CA || /* M29W320DT */
2043 info->device_id == 0x2256 || /* M29W320ET */
2044 info->device_id == 0x22D7) { /* M29W800DT */
e8eac437
RR		 2045 cfi_reverse_geometry(qry);
2046 }
4c2105cb
MF		 2047 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
2048 /* CFI >= 1.1, deduct from top/bottom flag */
2049 /* note: ext_addr is valid since cfi_version > 0 */
2050 cfi_reverse_geometry(qry);
e8eac437
RR		 2051 }
2052 }
2053}
2054
07b2c5c0
AD		 2055static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry)
2056{
2057 /*
2058 * SST, for many recent nor parallel flashes, says they are
2059 * CFI-conformant. This is not true, since qry struct.
2060 * reports a std. AMD command set (0x0002), while SST allows to
2061 * erase two different sector sizes for the same memory.
2062 * 64KB sector (SST call it block) needs 0x30 to be erased.
2063 * 4KB sector (SST call it sector) needs 0x50 to be erased.
2064 * Since CFI query detect the 4KB number of sectors, users expects
2065 * a sector granularity of 4KB, and it is here set.
2066 */
2067 if (info->device_id == 0x5D23 || /* SST39VF3201B */
2068 info->device_id == 0x5C23) { /* SST39VF3202B */
2069 /* set sector granularity to 4KB */
640f4e35 2070 info->cmd_erase_sector = 0x50;
07b2c5c0
AD		 2071 }
2072}
2073
c502321c
JT		 2074static void flash_fixup_num(flash_info_t *info, struct cfi_qry *qry)
2075{
2076 /*
2077 * The M29EW devices seem to report the CFI information wrong
2078 * when it's in 8 bit mode.
2079 * There's an app note from Numonyx on this issue.
2080 * So adjust the buffer size for M29EW while operating in 8-bit mode
2081 */
4f89da49 2082 if (qry->max_buf_write_size > 0x8 &&
c0350fbf
MS		 2083 info->device_id == 0x7E &&
2084 (info->device_id2 == 0x2201 ||
2085 info->device_id2 == 0x2301 ||
2086 info->device_id2 == 0x2801 ||
2087 info->device_id2 == 0x4801)) {
876c52f3
MS		 2088 debug("Adjusted buffer size on Numonyx flash");
2089 debug(" M29EW family in 8 bit mode\n");
c502321c
JT		 2090 qry->max_buf_write_size = 0x8;
2091 }
2092}
2093
5653fc33
WD		 2094/*
2095 * The following code cannot be run from FLASH!
2096 *
2097 */
188a5565 2098ulong flash_get_size(phys_addr_t base, int banknum)
5653fc33 2099{
bf9e3b38 2100 flash_info_t *info = &flash_info[banknum];
5653fc33
WD		 2101 int i, j;
2102 flash_sect_t sect_cnt;
09ce9921 2103 phys_addr_t sector;
5653fc33
WD		 2104 unsigned long tmp;
2105 int size_ratio;
2106 uchar num_erase_regions;
bf9e3b38
WD		 2107 int erase_region_size;
2108 int erase_region_count;
e23741f4 2109 struct cfi_qry qry;
34bbb8fb 2110 unsigned long max_size;
260421a2 2111
f979690e
KG		 2112 memset(&qry, 0, sizeof(qry));
2113
260421a2
SR		 2114 info->ext_addr = 0;
2115 info->cfi_version = 0;
6d0f6bcf 2116#ifdef CONFIG_SYS_FLASH_PROTECTION
2662b40c
SR		 2117 info->legacy_unlock = 0;
2118#endif
5653fc33 2119
09ce9921 2120 info->start[0] = (ulong)map_physmem(base, info->portwidth, MAP_NOCACHE);
5653fc33 2121
188a5565 2122 if (flash_detect_cfi(info, &qry)) {
4f89da49
MS		 2123 info->vendor = le16_to_cpu(get_unaligned(&qry.p_id));
2124 info->ext_addr = le16_to_cpu(get_unaligned(&qry.p_adr));
e23741f4
HS		 2125 num_erase_regions = qry.num_erase_regions;
2126
260421a2 2127 if (info->ext_addr) {
640f4e35 2128 info->cfi_version = (ushort)flash_read_uchar(info,
e303be2d 2129 info->ext_addr + 3) << 8;
640f4e35 2130 info->cfi_version |= (ushort)flash_read_uchar(info,
e303be2d 2131 info->ext_addr + 4);
260421a2 2132 }
0ddf06dd 2133
bf9e3b38 2134#ifdef DEBUG
188a5565 2135 flash_printqry(&qry);
bf9e3b38 2136#endif
0ddf06dd 2137
bf9e3b38 2138 switch (info->vendor) {
9c048b52 2139 case CFI_CMDSET_INTEL_PROG_REGIONS:
5653fc33
WD		 2140 case CFI_CMDSET_INTEL_STANDARD:
2141 case CFI_CMDSET_INTEL_EXTENDED:
0ddf06dd 2142 cmdset_intel_init(info, &qry);
5653fc33
WD		 2143 break;
2144 case CFI_CMDSET_AMD_STANDARD:
2145 case CFI_CMDSET_AMD_EXTENDED:
0ddf06dd 2146 cmdset_amd_init(info, &qry);
5653fc33 2147 break;
0ddf06dd
HS		 2148 default:
2149 printf("CFI: Unknown command set 0x%x\n",
c0350fbf 2150 info->vendor);
0ddf06dd
HS		 2151 /*
2152 * Unfortunately, this means we don't know how
2153 * to get the chip back to Read mode. Might
2154 * as well try an Intel-style reset...
2155 */
2156 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
2157 return 0;
5653fc33 2158 }
cd37d9e6 2159
467bcee1
HS		 2160 /* Do manufacturer-specific fixups */
2161 switch (info->manufacturer_id) {
2c9f48af
MS		 2162 case 0x0001: /* AMD */
2163 case 0x0037: /* AMIC */
467bcee1
HS		 2164 flash_fixup_amd(info, &qry);
2165 break;
2166 case 0x001f:
2167 flash_fixup_atmel(info, &qry);
2168 break;
e8eac437
RR		 2169 case 0x0020:
2170 flash_fixup_stm(info, &qry);
2171 break;
07b2c5c0
AD		 2172 case 0x00bf: /* SST */
2173 flash_fixup_sst(info, &qry);
2174 break;
c502321c
JT		 2175 case 0x0089: /* Numonyx */
2176 flash_fixup_num(info, &qry);
2177 break;
467bcee1
HS		 2178 }
2179
188a5565
MS		 2180 debug("manufacturer is %d\n", info->vendor);
2181 debug("manufacturer id is 0x%x\n", info->manufacturer_id);
2182 debug("device id is 0x%x\n", info->device_id);
2183 debug("device id2 is 0x%x\n", info->device_id2);
2184 debug("cfi version is 0x%04x\n", info->cfi_version);
260421a2 2185
5653fc33 2186 size_ratio = info->portwidth / info->chipwidth;
bf9e3b38 2187 /* if the chip is x8/x16 reduce the ratio by half */
4f89da49 2188 if (info->interface == FLASH_CFI_X8X16 &&
c0350fbf 2189 info->chipwidth == FLASH_CFI_BY8) {
bf9e3b38
WD		 2190 size_ratio >>= 1;
2191 }
188a5565 2192 debug("size_ratio %d port %d bits chip %d bits\n",
c0350fbf
MS		 2193 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
2194 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
ec50a8e3
IY		 2195 info->size = 1 << qry.dev_size;
2196 /* multiply the size by the number of chips */
2197 info->size *= size_ratio;
34bbb8fb 2198 max_size = cfi_flash_bank_size(banknum);
43bacbe6
NS		 2199#ifdef CONFIG_CFI_FLASH
2200 if (max_size)
2201 max_size = min((unsigned long)info->addr_size, max_size);
2202 else
2203 max_size = info->addr_size;
2204#endif
4f89da49 2205 if (max_size && info->size > max_size) {
ec50a8e3
IY		 2206 debug("[truncated from %ldMiB]", info->size >> 20);
2207 info->size = max_size;
2208 }
188a5565 2209 debug("found %d erase regions\n", num_erase_regions);
5653fc33
WD		 2210 sect_cnt = 0;
2211 sector = base;
bf9e3b38
WD		 2212 for (i = 0; i < num_erase_regions; i++) {
2213 if (i > NUM_ERASE_REGIONS) {
188a5565 2214 printf("%d erase regions found, only %d used\n",
c0350fbf 2215 num_erase_regions, NUM_ERASE_REGIONS);
5653fc33
WD		 2216 break;
2217 }
e23741f4 2218
aedadf10 2219 tmp = le32_to_cpu(get_unaligned(
4f89da49 2220 &qry.erase_region_info[i]));
0ddf06dd 2221 debug("erase region %u: 0x%08lx\n", i, tmp);
e23741f4
HS		 2222
2223 erase_region_count = (tmp & 0xffff) + 1;
2224 tmp >>= 16;
bf9e3b38
WD		 2225 erase_region_size =
2226 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
ddcf0540
MS		 2227 debug("erase_region_count = %d ", erase_region_count);
2228 debug("erase_region_size = %d\n", erase_region_size);
bf9e3b38 2229 for (j = 0; j < erase_region_count; j++) {
ec50a8e3
IY		 2230 if (sector - base >= info->size)
2231 break;
6d0f6bcf 2232 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
81b20ccc
MS		 2233 printf("ERROR: too many flash sectors\n");
2234 break;
2235 }
09ce9921
BB		 2236 info->start[sect_cnt] =
2237 (ulong)map_physmem(sector,
2238 info->portwidth,
2239 MAP_NOCACHE);
5653fc33 2240 sector += (erase_region_size * size_ratio);
a1191902
WD		 2241
2242 /*
7e5b9b47
HS		 2243 * Only read protection status from
2244 * supported devices (intel...)
a1191902
WD		 2245 */
2246 switch (info->vendor) {
9c048b52 2247 case CFI_CMDSET_INTEL_PROG_REGIONS:
a1191902
WD		 2248 case CFI_CMDSET_INTEL_EXTENDED:
2249 case CFI_CMDSET_INTEL_STANDARD:
df4e813b
SR		 2250 /*
2251 * Set flash to read-id mode. Otherwise
2252 * reading protected status is not
2253 * guaranteed.
2254 */
2255 flash_write_cmd(info, sect_cnt, 0,
2256 FLASH_CMD_READ_ID);
a1191902 2257 info->protect[sect_cnt] =
188a5565 2258 flash_isset(info, sect_cnt,
c0350fbf
MS		 2259 FLASH_OFFSET_PROTECT,
2260 FLASH_STATUS_PROTECT);
edc498c6
VK		 2261 flash_write_cmd(info, sect_cnt, 0,
2262 FLASH_CMD_RESET);
a1191902 2263 break;
03deff43
SR		 2264 case CFI_CMDSET_AMD_EXTENDED:
2265 case CFI_CMDSET_AMD_STANDARD:
ac6b9115 2266 if (!info->legacy_unlock) {
03deff43
SR		 2267 /* default: not protected */
2268 info->protect[sect_cnt] = 0;
2269 break;
2270 }
2271
2272 /* Read protection (PPB) from sector */
2273 flash_write_cmd(info, 0, 0,
2274 info->cmd_reset);
2275 flash_unlock_seq(info, 0);
2276 flash_write_cmd(info, 0,
2277 info->addr_unlock1,
94657482 2278 AMD_CMD_SET_PPB_ENTRY);
03deff43 2279 info->protect[sect_cnt] =
94657482
MV		 2280 !flash_isset(info, sect_cnt,
2281 0, 0x01);
2282 flash_write_cmd(info, 0, 0,
2283 info->cmd_reset);
03deff43 2284 break;
a1191902 2285 default:
7e5b9b47
HS		 2286 /* default: not protected */
2287 info->protect[sect_cnt] = 0;
a1191902
WD		 2288 }
2289
5653fc33
WD		 2290 sect_cnt++;
2291 }
2292 }
2293
2294 info->sector_count = sect_cnt;
e23741f4
HS		 2295 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size);
2296 tmp = 1 << qry.block_erase_timeout_typ;
7e5b9b47 2297 info->erase_blk_tout = tmp *
e23741f4
HS		 2298 (1 << qry.block_erase_timeout_max);
2299 tmp = (1 << qry.buf_write_timeout_typ) *
2300 (1 << qry.buf_write_timeout_max);
2301
7e5b9b47 2302 /* round up when converting to ms */
e23741f4
HS		 2303 info->buffer_write_tout = (tmp + 999) / 1000;
2304 tmp = (1 << qry.word_write_timeout_typ) *
2305 (1 << qry.word_write_timeout_max);
7e5b9b47 2306 /* round up when converting to ms */
e23741f4 2307 info->write_tout = (tmp + 999) / 1000;
5653fc33 2308 info->flash_id = FLASH_MAN_CFI;
4f89da49
MS		 2309 if (info->interface == FLASH_CFI_X8X16 &&
2310 info->chipwidth == FLASH_CFI_BY8) {
7e5b9b47
HS		 2311 /* XXX - Need to test on x8/x16 in parallel. */
2312 info->portwidth >>= 1;
855a496f 2313 }
2215987e 2314
188a5565 2315 flash_write_cmd(info, 0, 0, info->cmd_reset);
5653fc33
WD		 2316 }
2317
bf9e3b38 2318 return (info->size);
5653fc33
WD		 2319}
2320
4ffeab2c 2321#ifdef CONFIG_FLASH_CFI_MTD
6ea808ef
PZ		 2322void flash_set_verbose(uint v)
2323{
2324 flash_verbose = v;
2325}
4ffeab2c 2326#endif
6ea808ef 2327
6f726f95
SR		 2328static void cfi_flash_set_config_reg(u32 base, u16 val)
2329{
2330#ifdef CONFIG_SYS_CFI_FLASH_CONFIG_REGS
2331 /*
2332 * Only set this config register if really defined
2333 * to a valid value (0xffff is invalid)
2334 */
2335 if (val == 0xffff)
2336 return;
2337
2338 /*
2339 * Set configuration register. Data is "encrypted" in the 16 lower
2340 * address bits.
2341 */
2342 flash_write16(FLASH_CMD_SETUP, (void *)(base + (val << 1)));
2343 flash_write16(FLASH_CMD_SET_CR_CONFIRM, (void *)(base + (val << 1)));
2344
2345 /*
2346 * Finally issue reset-command to bring device back to
2347 * read-array mode
2348 */
2349 flash_write16(FLASH_CMD_RESET, (void *)base);
2350#endif
2351}
2352
5653fc33
WD		 2353/*-----------------------------------------------------------------------
2354 */
6ee1416e 2355
236c49a1 2356static void flash_protect_default(void)
6ee1416e 2357{
2c51983b
PT		 2358#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
2359 int i;
2360 struct apl_s {
2361 ulong start;
2362 ulong size;
2363 } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST;
2364#endif
2365
6ee1416e 2366 /* Monitor protection ON by default */
d75eacf9 2367#if defined(CONFIG_SYS_MONITOR_BASE) && \
65cc0e2a 2368 (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE) && \
6ee1416e
HS		 2369 (!defined(CONFIG_MONITOR_IS_IN_RAM))
2370 flash_protect(FLAG_PROTECT_SET,
c0350fbf
MS		 2371 CONFIG_SYS_MONITOR_BASE,
2372 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
2373 flash_get_info(CONFIG_SYS_MONITOR_BASE));
6ee1416e
HS		 2374#endif
2375
2376 /* Environment protection ON by default */
2377#ifdef CONFIG_ENV_IS_IN_FLASH
2378 flash_protect(FLAG_PROTECT_SET,
c0350fbf
MS		 2379 CONFIG_ENV_ADDR,
2380 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
2381 flash_get_info(CONFIG_ENV_ADDR));
6ee1416e
HS		 2382#endif
2383
2384 /* Redundant environment protection ON by default */
2385#ifdef CONFIG_ENV_ADDR_REDUND
2386 flash_protect(FLAG_PROTECT_SET,
c0350fbf
MS		 2387 CONFIG_ENV_ADDR_REDUND,
2388 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
2389 flash_get_info(CONFIG_ENV_ADDR_REDUND));
6ee1416e
HS		 2390#endif
2391
2392#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
31bf0f57 2393 for (i = 0; i < ARRAY_SIZE(apl); i++) {
31d34143 2394 debug("autoprotecting from %08lx to %08lx\n",
6ee1416e
HS		 2395 apl[i].start, apl[i].start + apl[i].size - 1);
2396 flash_protect(FLAG_PROTECT_SET,
c0350fbf
MS		 2397 apl[i].start,
2398 apl[i].start + apl[i].size - 1,
2399 flash_get_info(apl[i].start));
6ee1416e
HS		 2400 }
2401#endif
2402}
2403
188a5565 2404unsigned long flash_init(void)
5653fc33 2405{
be60a902
HS		 2406 unsigned long size = 0;
2407 int i;
5653fc33 2408
6d0f6bcf 2409#ifdef CONFIG_SYS_FLASH_PROTECTION
3a3baf3e
ES		 2410 /* read environment from EEPROM */
2411 char s[64];
7223a8cb 2412
00caae6d 2413 env_get_f("unlock", s, sizeof(s));
81b20ccc 2414#endif
5653fc33 2415
f1056910
TC		 2416#ifdef CONFIG_CFI_FLASH /* for driver model */
2417 cfi_flash_init_dm();
2418#endif
2419
be60a902 2420 /* Init: no FLASHes known */
98150e7e 2421 for (i = 0; i < CFI_FLASH_BANKS; ++i) {
be60a902 2422 flash_info[i].flash_id = FLASH_UNKNOWN;
5653fc33 2423
6f726f95
SR		 2424 /* Optionally write flash configuration register */
2425 cfi_flash_set_config_reg(cfi_flash_bank_addr(i),
2426 cfi_flash_config_reg(i));
2427
b00e19cc 2428 if (!flash_detect_legacy(cfi_flash_bank_addr(i), i))
34bbb8fb 2429 flash_get_size(cfi_flash_bank_addr(i), i);
be60a902
HS		 2430 size += flash_info[i].size;
2431 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
6d0f6bcf 2432#ifndef CONFIG_SYS_FLASH_QUIET_TEST
876c52f3
MS		 2433 printf("## Unknown flash on Bank %d ", i + 1);
2434 printf("- Size = 0x%08lx = %ld MB\n",
c0350fbf
MS		 2435 flash_info[i].size,
2436 flash_info[i].size >> 20);
6d0f6bcf 2437#endif /* CONFIG_SYS_FLASH_QUIET_TEST */
be60a902 2438 }
6d0f6bcf 2439#ifdef CONFIG_SYS_FLASH_PROTECTION
c15df21f 2440 else if (strcmp(s, "yes") == 0) {
be60a902
HS		 2441 /*
2442 * Only the U-Boot image and it's environment
2443 * is protected, all other sectors are
2444 * unprotected (unlocked) if flash hardware
6d0f6bcf 2445 * protection is used (CONFIG_SYS_FLASH_PROTECTION)
be60a902
HS		 2446 * and the environment variable "unlock" is
2447 * set to "yes".
2448 */
2449 if (flash_info[i].legacy_unlock) {
2450 int k;
5653fc33 2451
be60a902
HS		 2452 /*
2453 * Disable legacy_unlock temporarily,
2454 * since flash_real_protect would
2455 * relock all other sectors again
2456 * otherwise.
2457 */
2458 flash_info[i].legacy_unlock = 0;
5653fc33 2459
be60a902
HS		 2460 /*
2461 * Legacy unlocking (e.g. Intel J3) ->
2462 * unlock only one sector. This will
2463 * unlock all sectors.
2464 */
188a5565 2465 flash_real_protect(&flash_info[i], 0, 0);
5653fc33 2466
be60a902 2467 flash_info[i].legacy_unlock = 1;
5653fc33 2468
be60a902
HS		 2469 /*
2470 * Manually mark other sectors as
2471 * unlocked (unprotected)
2472 */
2473 for (k = 1; k < flash_info[i].sector_count; k++)
2474 flash_info[i].protect[k] = 0;
2475 } else {
2476 /*
2477 * No legancy unlocking -> unlock all sectors
2478 */
188a5565 2479 flash_protect(FLAG_PROTECT_CLEAR,
c0350fbf
MS		 2480 flash_info[i].start[0],
2481 flash_info[i].start[0]
2482 + flash_info[i].size - 1,
2483 &flash_info[i]);
79b4cda0 2484 }
79b4cda0 2485 }
6d0f6bcf 2486#endif /* CONFIG_SYS_FLASH_PROTECTION */
be60a902 2487 }
79b4cda0 2488
6ee1416e 2489 flash_protect_default();
91809ed5
PZ		 2490#ifdef CONFIG_FLASH_CFI_MTD
2491 cfi_mtd_init();
2492#endif
2493
be60a902 2494 return (size);
5653fc33 2495}
f1056910
TC		 2496
2497#ifdef CONFIG_CFI_FLASH /* for driver model */
2498static int cfi_flash_probe(struct udevice *dev)
2499{
492b9917 2500 fdt_addr_t addr;
43bacbe6 2501 fdt_size_t size;
492b9917 2502 int idx;
f1056910 2503
492b9917 2504 for (idx = 0; idx < CFI_MAX_FLASH_BANKS; idx++) {
43bacbe6 2505 addr = dev_read_addr_size_index(dev, idx, &size);
492b9917
AP		 2506 if (addr == FDT_ADDR_T_NONE)
2507 break;
8bfeb33c 2508
1ec0a37e
MV		 2509 flash_info[cfi_flash_num_flash_banks].dev = dev;
2510 flash_info[cfi_flash_num_flash_banks].base = addr;
43bacbe6 2511 flash_info[cfi_flash_num_flash_banks].addr_size = size;
1ec0a37e 2512 cfi_flash_num_flash_banks++;
f1056910 2513 }
1ec0a37e 2514 gd->bd->bi_flashstart = flash_info[0].base;
f1056910
TC		 2515
2516 return 0;
2517}
2518
2519static const struct udevice_id cfi_flash_ids[] = {
2520 { .compatible = "cfi-flash" },
2521 { .compatible = "jedec-flash" },
2522 {}
2523};
2524
2525U_BOOT_DRIVER(cfi_flash) = {
2526 .name = "cfi_flash",
2527 .id = UCLASS_MTD,
2528 .of_match = cfi_flash_ids,
2529 .probe = cfi_flash_probe,
2530};
2531#endif /* CONFIG_CFI_FLASH */
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