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Commit | Line | Data |
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5bbc265b AF |
1 | |
2 | menuconfig NAND | |
3 | bool "NAND Device Support" | |
4 | if NAND | |
4b0abf9f | 5 | |
65e4145a MY |
6 | config SYS_NAND_SELF_INIT |
7 | bool | |
8 | help | |
9 | This option, if enabled, provides more flexible and linux-like | |
10 | NAND initialization process. | |
11 | ||
4b0abf9f | 12 | config NAND_DENALI |
dc774e69 | 13 | bool |
65e4145a | 14 | select SYS_NAND_SELF_INIT |
8f1a80e9 | 15 | imply CMD_NAND |
4b0abf9f | 16 | |
1d9654dc MY |
17 | config NAND_DENALI_DT |
18 | bool "Support Denali NAND controller as a DT device" | |
dc774e69 MY |
19 | select NAND_DENALI |
20 | depends on OF_CONTROL && DM | |
1d9654dc MY |
21 | help |
22 | Enable the driver for NAND flash on platforms using a Denali NAND | |
23 | controller as a DT device. | |
24 | ||
4b0abf9f MY |
25 | config NAND_DENALI_SPARE_AREA_SKIP_BYTES |
26 | int "Number of bytes skipped in OOB area" | |
27 | depends on NAND_DENALI | |
28 | range 0 63 | |
29 | help | |
30 | This option specifies the number of bytes to skip from the beginning | |
31 | of OOB area before last ECC sector data starts. This is potentially | |
32 | used to preserve the bad block marker in the OOB area. | |
33 | ||
0a9ef451 AF |
34 | config NAND_OMAP_GPMC |
35 | bool "Support OMAP GPMC NAND controller" | |
36 | depends on ARCH_OMAP2PLUS | |
37 | help | |
38 | Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. | |
39 | GPMC controller is used for parallel NAND flash devices, and can | |
40 | do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 | |
41 | and BCH16 ECC algorithms. | |
42 | ||
43 | config NAND_OMAP_GPMC_PREFETCH | |
44 | bool "Enable GPMC Prefetch" | |
45 | depends on NAND_OMAP_GPMC | |
39e70961 | 46 | default y |
0a9ef451 AF |
47 | help |
48 | On OMAP platforms that use the GPMC controller | |
49 | (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that | |
50 | uses the prefetch mode to speed up read operations. | |
51 | ||
52 | config NAND_OMAP_ELM | |
53 | bool "Enable ELM driver for OMAPxx and AMxx platforms." | |
54 | depends on NAND_OMAP_GPMC && !OMAP34XX | |
55 | help | |
56 | ELM controller is used for ECC error detection (not ECC calculation) | |
57 | of BCH4, BCH8 and BCH16 ECC algorithms. | |
58 | Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, | |
59 | thus such SoC platforms need to depend on software library for ECC error | |
60 | detection. However ECC calculation on such plaforms would still be | |
61 | done by GPMC controller. | |
62 | ||
5519194d | 63 | config NAND_VF610_NFC |
064b55cf | 64 | bool "Support for Freescale NFC for VF610" |
5519194d | 65 | select SYS_NAND_SELF_INIT |
8f1a80e9 | 66 | imply CMD_NAND |
5519194d SA |
67 | help |
68 | Enables support for NAND Flash Controller on some Freescale | |
064b55cf | 69 | processors like the VF610, MCF54418 or Kinetis K70. |
5519194d SA |
70 | The driver supports a maximum 2k page size. The driver |
71 | currently does not support hardware ECC. | |
72 | ||
080a71e8 SA |
73 | choice |
74 | prompt "Hardware ECC strength" | |
75 | depends on NAND_VF610_NFC | |
76 | default SYS_NAND_VF610_NFC_45_ECC_BYTES | |
77 | help | |
78 | Select the ECC strength used in the hardware BCH ECC block. | |
79 | ||
80 | config SYS_NAND_VF610_NFC_45_ECC_BYTES | |
81 | bool "24-error correction (45 ECC bytes)" | |
82 | ||
83 | config SYS_NAND_VF610_NFC_60_ECC_BYTES | |
84 | bool "32-error correction (60 ECC bytes)" | |
85 | ||
86 | endchoice | |
87 | ||
873960c8 SR |
88 | config NAND_PXA3XX |
89 | bool "Support for NAND on PXA3xx and Armada 370/XP/38x" | |
90 | select SYS_NAND_SELF_INIT | |
8f1a80e9 | 91 | imply CMD_NAND |
873960c8 SR |
92 | help |
93 | This enables the driver for the NAND flash device found on | |
94 | PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). | |
95 | ||
e5268616 | 96 | config NAND_SUNXI |
4ccae81c | 97 | bool "Support for NAND on Allwinner SoCs" |
e5268616 HG |
98 | depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
99 | select SYS_NAND_SELF_INIT | |
5fe4c9f4 | 100 | select SYS_NAND_U_BOOT_LOCATIONS |
8f1a80e9 | 101 | imply CMD_NAND |
e5268616 | 102 | ---help--- |
4ccae81c BB |
103 | Enable support for NAND. This option enables the standard and |
104 | SPL drivers. | |
105 | The SPL driver only supports reading from the NAND using DMA | |
106 | transfers. | |
e5268616 | 107 | |
ff93c282 MR |
108 | if NAND_SUNXI |
109 | ||
110 | config NAND_SUNXI_SPL_ECC_STRENGTH | |
111 | int "Allwinner NAND SPL ECC Strength" | |
112 | default 64 | |
113 | ||
114 | config NAND_SUNXI_SPL_ECC_SIZE | |
115 | int "Allwinner NAND SPL ECC Step Size" | |
116 | default 1024 | |
117 | ||
118 | config NAND_SUNXI_SPL_USABLE_PAGE_SIZE | |
119 | int "Allwinner NAND SPL Usable Page Size" | |
120 | default 1024 | |
121 | ||
122 | endif | |
123 | ||
78cb965a SDPP |
124 | config NAND_ARASAN |
125 | bool "Configure Arasan Nand" | |
8f1a80e9 | 126 | imply CMD_NAND |
78cb965a SDPP |
127 | help |
128 | This enables Nand driver support for Arasan nand flash | |
129 | controller. This uses the hardware ECC for read and | |
130 | write operations. | |
131 | ||
0a9ef451 AF |
132 | config NAND_MXC |
133 | bool "MXC NAND support" | |
134 | depends on CPU_ARM926EJS || CPU_ARM1136 || MX5 | |
135 | imply CMD_NAND | |
136 | help | |
137 | This enables the NAND driver for the NAND flash controller on the | |
138 | i.MX27 / i.MX31 / i.MX5 rocessors. | |
139 | ||
df10a850 JT |
140 | config NAND_MXS |
141 | bool "MXS NAND support" | |
f78038dc | 142 | depends on MX6 || MX7 |
8f1a80e9 | 143 | imply CMD_NAND |
df10a850 JT |
144 | help |
145 | This enables NAND driver for the NAND flash controller on the | |
146 | MXS processors. | |
147 | ||
ae798d2e SDPP |
148 | config NAND_ZYNQ |
149 | bool "Support for Zynq Nand controller" | |
150 | select SYS_NAND_SELF_INIT | |
8f1a80e9 | 151 | imply CMD_NAND |
ae798d2e SDPP |
152 | help |
153 | This enables Nand driver support for Nand flash controller | |
154 | found on Zynq SoC. | |
155 | ||
8000d6ea JW |
156 | config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS |
157 | bool "Enable use of 1st stage bootloader timing for NAND" | |
158 | depends on NAND_ZYNQ | |
159 | help | |
160 | This flag prevent U-boot reconfigure NAND flash controller and reuse | |
161 | the NAND timing from 1st stage bootloader. | |
162 | ||
5519194d SA |
163 | comment "Generic NAND options" |
164 | ||
165 | # Enhance depends when converting drivers to Kconfig which use this config | |
166 | # option (mxc_nand, ndfc, omap_gpmc). | |
167 | config SYS_NAND_BUSWIDTH_16BIT | |
168 | bool "Use 16-bit NAND interface" | |
0a9ef451 | 169 | depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI |
5519194d SA |
170 | help |
171 | Indicates that NAND device has 16-bit wide data-bus. In absence of this | |
172 | config, bus-width of NAND device is assumed to be either 8-bit and later | |
173 | determined by reading ONFI params. | |
174 | Above config is useful when NAND device's bus-width information cannot | |
175 | be determined from on-chip ONFI params, like in following scenarios: | |
176 | - SPL boot does not support reading of ONFI parameters. This is done to | |
177 | keep SPL code foot-print small. | |
178 | - In current U-Boot flow using nand_init(), driver initialization | |
179 | happens in board_nand_init() which is called before any device probe | |
180 | (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are | |
181 | not available while configuring controller. So a static CONFIG_NAND_xx | |
182 | is needed to know the device's bus-width in advance. | |
183 | ||
494e1086 BB |
184 | if SPL |
185 | ||
186 | config SYS_NAND_U_BOOT_LOCATIONS | |
187 | bool "Define U-boot binaries locations in NAND" | |
188 | help | |
189 | Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. | |
190 | This option should not be enabled when compiling U-boot for boards | |
191 | defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h | |
192 | file. | |
193 | ||
d90ba790 HG |
194 | config SYS_NAND_U_BOOT_OFFS |
195 | hex "Location in NAND to read U-Boot from" | |
adc706b2 | 196 | default 0x800000 if NAND_SUNXI |
494e1086 | 197 | depends on SYS_NAND_U_BOOT_LOCATIONS |
d90ba790 HG |
198 | help |
199 | Set the offset from the start of the nand where u-boot should be | |
200 | loaded from. | |
201 | ||
80ef700f BB |
202 | config SYS_NAND_U_BOOT_OFFS_REDUND |
203 | hex "Location in NAND to read U-Boot from" | |
204 | default SYS_NAND_U_BOOT_OFFS | |
205 | depends on SYS_NAND_U_BOOT_LOCATIONS | |
206 | help | |
207 | Set the offset from the start of the nand where the redundant u-boot | |
208 | should be loaded from. | |
209 | ||
0a9ef451 AF |
210 | config SPL_NAND_AM33XX_BCH |
211 | bool "Enables SPL-NAND driver which supports ELM based" | |
212 | depends on NAND_OMAP_GPMC && !OMAP34XX | |
213 | default y | |
214 | help | |
215 | Hardware ECC correction. This is useful for platforms which have ELM | |
216 | hardware engine and use NAND boot mode. | |
217 | Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, | |
218 | so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling | |
219 | SPL-NAND driver with software ECC correction support. | |
220 | ||
845034e6 MY |
221 | config SPL_NAND_DENALI |
222 | bool "Support Denali NAND controller for SPL" | |
223 | help | |
224 | This is a small implementation of the Denali NAND controller | |
225 | for use on SPL. | |
226 | ||
0a9ef451 AF |
227 | config SPL_NAND_SIMPLE |
228 | bool "Use simple SPL NAND driver" | |
229 | depends on !SPL_NAND_AM33XX_BCH | |
230 | help | |
231 | Support for NAND boot using simple NAND drivers that | |
232 | expose the cmd_ctrl() interface. | |
845034e6 MY |
233 | endif |
234 | ||
5bbc265b | 235 | endif # if NAND |