]>
Commit | Line | Data |
---|---|---|
7d4b7955 SW |
1 | /* |
2 | * NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine | |
3 | * | |
4 | * (C) Copyright 2006-2008 | |
5 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
6 | * | |
7 | * Copyright (c) 2008 Freescale Semiconductor, Inc. | |
8 | * Author: Scott Wood <scottwood@freescale.com> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
7d4b7955 SW |
11 | */ |
12 | ||
13 | #include <common.h> | |
14 | #include <asm/io.h> | |
15 | #include <asm/fsl_lbc.h> | |
16 | #include <nand.h> | |
17 | ||
18 | #define WINDOW_SIZE 8192 | |
19 | ||
20 | static void nand_wait(void) | |
21 | { | |
22 | fsl_lbc_t *regs = LBC_BASE_ADDR; | |
23 | ||
24 | for (;;) { | |
25 | uint32_t status = in_be32(®s->ltesr); | |
26 | ||
27 | if (status == 1) | |
28 | return; | |
29 | ||
30 | if (status & 1) { | |
31 | puts("read failed (ltesr)\n"); | |
32 | for (;;); | |
33 | } | |
34 | } | |
35 | } | |
36 | ||
37 | static int nand_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) | |
38 | { | |
39 | fsl_lbc_t *regs = LBC_BASE_ADDR; | |
40 | uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE; | |
41 | const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS; | |
42 | const int block_shift = large ? 17 : 14; | |
43 | const int block_size = 1 << block_shift; | |
44 | const int page_size = large ? 2048 : 512; | |
45 | const int bad_marker = large ? page_size + 0 : page_size + 5; | |
46 | int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2; | |
47 | int pos = 0; | |
48 | char *dst = vdst; | |
49 | ||
50 | if (offs & (block_size - 1)) { | |
51 | puts("bad offset\n"); | |
52 | for (;;); | |
53 | } | |
54 | ||
55 | if (large) { | |
56 | fmr |= FMR_ECCM; | |
57 | out_be32(®s->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | | |
58 | (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); | |
59 | out_be32(®s->fir, | |
60 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
61 | (FIR_OP_CA << FIR_OP1_SHIFT) | | |
62 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
63 | (FIR_OP_CW1 << FIR_OP3_SHIFT) | | |
64 | (FIR_OP_RBW << FIR_OP4_SHIFT)); | |
65 | } else { | |
66 | out_be32(®s->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); | |
67 | out_be32(®s->fir, | |
68 | (FIR_OP_CW0 << FIR_OP0_SHIFT) | | |
69 | (FIR_OP_CA << FIR_OP1_SHIFT) | | |
70 | (FIR_OP_PA << FIR_OP2_SHIFT) | | |
71 | (FIR_OP_RBW << FIR_OP3_SHIFT)); | |
72 | } | |
73 | ||
74 | out_be32(®s->fbcr, 0); | |
75 | clrsetbits_be32(®s->bank[0].br, BR_DECC, BR_DECC_CHK_GEN); | |
76 | ||
77 | while (pos < uboot_size) { | |
78 | int i = 0; | |
79 | out_be32(®s->fbar, offs >> block_shift); | |
80 | ||
81 | do { | |
82 | int j; | |
83 | unsigned int page_offs = (offs & (block_size - 1)) << 1; | |
84 | ||
85 | out_be32(®s->ltesr, ~0); | |
86 | out_be32(®s->lteatr, 0); | |
87 | out_be32(®s->fpar, page_offs); | |
88 | out_be32(®s->fmr, fmr); | |
89 | out_be32(®s->lsor, 0); | |
90 | nand_wait(); | |
91 | ||
92 | page_offs %= WINDOW_SIZE; | |
93 | ||
94 | /* | |
95 | * If either of the first two pages are marked bad, | |
96 | * continue to the next block. | |
97 | */ | |
98 | if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) { | |
99 | puts("skipping\n"); | |
100 | offs = (offs + block_size) & ~(block_size - 1); | |
101 | pos &= ~(block_size - 1); | |
102 | break; | |
103 | } | |
104 | ||
105 | for (j = 0; j < page_size; j++) | |
106 | dst[pos + j] = buf[page_offs + j]; | |
107 | ||
108 | pos += page_size; | |
109 | offs += page_size; | |
110 | } while ((offs & (block_size - 1)) && (pos < uboot_size)); | |
111 | } | |
112 | ||
113 | return 0; | |
114 | } | |
115 | ||
116 | /* | |
117 | * The main entry for NAND booting. It's necessary that SDRAM is already | |
118 | * configured and available since this code loads the main U-Boot image | |
119 | * from NAND into SDRAM and starts it from there. | |
120 | */ | |
121 | void nand_boot(void) | |
122 | { | |
123 | __attribute__((noreturn)) void (*uboot)(void); | |
124 | /* | |
125 | * Load U-Boot image from NAND into RAM | |
126 | */ | |
127 | nand_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, | |
128 | CONFIG_SYS_NAND_U_BOOT_SIZE, | |
129 | (void *)CONFIG_SYS_NAND_U_BOOT_DST); | |
130 | ||
131 | #ifdef CONFIG_NAND_ENV_DST | |
132 | nand_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, | |
133 | (void *)CONFIG_NAND_ENV_DST); | |
134 | ||
135 | #ifdef CONFIG_ENV_OFFSET_REDUND | |
136 | nand_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, | |
137 | (void *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE); | |
138 | #endif | |
139 | #endif | |
140 | ||
141 | #ifdef CONFIG_SPL_FLUSH_IMAGE | |
142 | /* | |
143 | * Clean d-cache and invalidate i-cache, to | |
144 | * make sure that no stale data is executed. | |
145 | */ | |
146 | flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); | |
147 | #endif | |
148 | ||
149 | puts("transfering control\n"); | |
150 | /* | |
151 | * Jump to U-Boot image | |
152 | */ | |
153 | uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; | |
154 | (*uboot)(); | |
155 | } |