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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
12201a13 DB |
2 | /* |
3 | * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com> | |
4 | * Rohit Choraria <rohitkc@ti.com> | |
12201a13 DB |
5 | */ |
6 | ||
d678a59d | 7 | #include <common.h> |
f7ae49fc | 8 | #include <log.h> |
601b8901 | 9 | #include <system-constants.h> |
12201a13 | 10 | #include <asm/io.h> |
dd01a229 | 11 | #include <dm.h> |
1221ce45 | 12 | #include <linux/errno.h> |
c6bafdae RQ |
13 | |
14 | #ifdef CONFIG_ARCH_OMAP2PLUS | |
12201a13 | 15 | #include <asm/arch/mem.h> |
c6bafdae RQ |
16 | #endif |
17 | ||
dd01a229 RQ |
18 | #include <linux/io.h> |
19 | #include <linux/ioport.h> | |
6aff0509 | 20 | #include <linux/mtd/omap_gpmc.h> |
12201a13 | 21 | #include <linux/mtd/nand_ecc.h> |
1cefed1e | 22 | #include <linux/mtd/rawnand.h> |
4a093006 | 23 | #include <linux/bch.h> |
f7dad8f1 | 24 | #include <linux/compiler.h> |
12201a13 | 25 | #include <nand.h> |
7363cf05 RQ |
26 | |
27 | #include "omap_elm.h" | |
d016dc42 | 28 | |
c6bafdae RQ |
29 | #ifndef GPMC_MAX_CS |
30 | #define GPMC_MAX_CS 4 | |
31 | #endif | |
32 | ||
d016dc42 | 33 | #define BADBLOCK_MARKER_LENGTH 2 |
34 | #define SECTOR_BYTES 512 | |
04fcd258 RQ |
35 | #define ECCSIZE0_SHIFT 12 |
36 | #define ECCSIZE1_SHIFT 22 | |
37 | #define ECC1RESULTSIZE 0x1 | |
f5f1f614 | 38 | #define ECCCLEAR (0x1 << 8) |
39 | #define ECCRESULTREG1 (0x1 << 0) | |
6e562b11 | 40 | /* 4 bit padding to make byte aligned, 56 = 52 + 4 */ |
41 | #define BCH4_BIT_PAD 4 | |
42 | ||
71a7f956 | 43 | #ifdef CONFIG_BCH |
44 | static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, | |
45 | 0x97, 0x79, 0xe5, 0x24, 0xb5}; | |
46 | #endif | |
5c3f7e0e | 47 | static uint8_t cs_next; |
12201a13 | 48 | |
d8af3933 MS |
49 | #if defined(CONFIG_NAND_OMAP_GPMC_WSCFG) |
50 | static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] = | |
51 | { CONFIG_NAND_OMAP_GPMC_WSCFG }; | |
52 | #else | |
53 | /* wscfg is preset to zero since its a static variable */ | |
54 | static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE]; | |
55 | #endif | |
56 | ||
5c3f7e0e RL |
57 | /* |
58 | * Driver configurations | |
59 | */ | |
60 | struct omap_nand_info { | |
61 | struct bch_control *control; | |
62 | enum omap_ecc ecc_scheme; | |
d8af3933 MS |
63 | uint8_t cs; |
64 | uint8_t ws; /* wait status pin (0,1) */ | |
cd72a950 | 65 | void __iomem *fifo; |
5c3f7e0e RL |
66 | }; |
67 | ||
68 | /* We are wasting a bit of memory but al least we are safe */ | |
69 | static struct omap_nand_info omap_nand_info[GPMC_MAX_CS]; | |
70 | ||
12201a13 DB |
71 | /* |
72 | * omap_nand_hwcontrol - Set the address pointers corretly for the | |
73 | * following address/data/command operation | |
74 | */ | |
75 | static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd, | |
76 | uint32_t ctrl) | |
77 | { | |
17cb4b8f SW |
78 | register struct nand_chip *this = mtd_to_nand(mtd); |
79 | struct omap_nand_info *info = nand_get_controller_data(this); | |
5c3f7e0e | 80 | int cs = info->cs; |
12201a13 DB |
81 | |
82 | /* | |
83 | * Point the IO_ADDR to DATA and ADDRESS registers instead | |
84 | * of chip address | |
85 | */ | |
86 | switch (ctrl) { | |
87 | case NAND_CTRL_CHANGE | NAND_CTRL_CLE: | |
89411352 | 88 | this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; |
12201a13 DB |
89 | break; |
90 | case NAND_CTRL_CHANGE | NAND_CTRL_ALE: | |
89411352 | 91 | this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr; |
12201a13 DB |
92 | break; |
93 | case NAND_CTRL_CHANGE | NAND_NCE: | |
89411352 | 94 | this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; |
12201a13 DB |
95 | break; |
96 | } | |
97 | ||
98 | if (cmd != NAND_CMD_NONE) | |
99 | writeb(cmd, this->IO_ADDR_W); | |
100 | } | |
101 | ||
12c2f1ee | 102 | /* Check wait pin as dev ready indicator */ |
fb384c47 | 103 | static int omap_dev_ready(struct mtd_info *mtd) |
12c2f1ee | 104 | { |
17cb4b8f SW |
105 | register struct nand_chip *this = mtd_to_nand(mtd); |
106 | struct omap_nand_info *info = nand_get_controller_data(this); | |
d8af3933 | 107 | return gpmc_cfg->status & (1 << (8 + info->ws)); |
12c2f1ee | 108 | } |
12201a13 DB |
109 | |
110 | /* | |
111 | * gen_true_ecc - This function will generate true ECC value, which | |
112 | * can be used when correcting data read from NAND flash memory core | |
113 | * | |
114 | * @ecc_buf: buffer to store ecc code | |
115 | * | |
116 | * @return: re-formatted ECC value | |
117 | */ | |
118 | static uint32_t gen_true_ecc(uint8_t *ecc_buf) | |
119 | { | |
120 | return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) | | |
121 | ((ecc_buf[2] & 0x0F) << 8); | |
122 | } | |
123 | ||
124 | /* | |
125 | * omap_correct_data - Compares the ecc read from nand spare area with ECC | |
eae4b2b6 | 126 | * registers values and corrects one bit error if it has occurred |
12201a13 DB |
127 | * Further details can be had from OMAP TRM and the following selected links: |
128 | * http://en.wikipedia.org/wiki/Hamming_code | |
129 | * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf | |
130 | * | |
131 | * @mtd: MTD device structure | |
132 | * @dat: page data | |
133 | * @read_ecc: ecc read from nand flash | |
134 | * @calc_ecc: ecc read from ECC registers | |
135 | * | |
185f812c | 136 | * Return: 0 if data is OK or corrected, else returns -1 |
12201a13 | 137 | */ |
f7dad8f1 | 138 | static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, |
12201a13 DB |
139 | uint8_t *read_ecc, uint8_t *calc_ecc) |
140 | { | |
141 | uint32_t orig_ecc, new_ecc, res, hm; | |
142 | uint16_t parity_bits, byte; | |
143 | uint8_t bit; | |
144 | ||
145 | /* Regenerate the orginal ECC */ | |
146 | orig_ecc = gen_true_ecc(read_ecc); | |
147 | new_ecc = gen_true_ecc(calc_ecc); | |
148 | /* Get the XOR of real ecc */ | |
149 | res = orig_ecc ^ new_ecc; | |
150 | if (res) { | |
151 | /* Get the hamming width */ | |
152 | hm = hweight32(res); | |
153 | /* Single bit errors can be corrected! */ | |
154 | if (hm == 12) { | |
155 | /* Correctable data! */ | |
156 | parity_bits = res >> 16; | |
157 | bit = (parity_bits & 0x7); | |
158 | byte = (parity_bits >> 3) & 0x1FF; | |
159 | /* Flip the bit to correct */ | |
160 | dat[byte] ^= (0x1 << bit); | |
161 | } else if (hm == 1) { | |
162 | printf("Error: Ecc is wrong\n"); | |
163 | /* ECC itself is corrupted */ | |
164 | return 2; | |
165 | } else { | |
166 | /* | |
167 | * hm distance != parity pairs OR one, could mean 2 bit | |
168 | * error OR potentially be on a blank page.. | |
169 | * orig_ecc: contains spare area data from nand flash. | |
170 | * new_ecc: generated ecc while reading data area. | |
171 | * Note: if the ecc = 0, all data bits from which it was | |
172 | * generated are 0xFF. | |
173 | * The 3 byte(24 bits) ecc is generated per 512byte | |
174 | * chunk of a page. If orig_ecc(from spare area) | |
175 | * is 0xFF && new_ecc(computed now from data area)=0x0, | |
176 | * this means that data area is 0xFF and spare area is | |
177 | * 0xFF. A sure sign of a erased page! | |
178 | */ | |
179 | if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000)) | |
180 | return 0; | |
181 | printf("Error: Bad compare! failed\n"); | |
182 | /* detected 2 bit error */ | |
ceee07b6 | 183 | return -EBADMSG; |
12201a13 DB |
184 | } |
185 | } | |
186 | return 0; | |
187 | } | |
188 | ||
4a093006 | 189 | /* |
f5f1f614 | 190 | * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write |
4a093006 AB |
191 | * @mtd: MTD device structure |
192 | * @mode: Read/Write mode | |
193 | */ | |
194 | __maybe_unused | |
f5f1f614 | 195 | static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) |
4a093006 | 196 | { |
04fcd258 RQ |
197 | struct nand_chip *nand = mtd_to_nand(mtd); |
198 | struct omap_nand_info *info = nand_get_controller_data(nand); | |
f5f1f614 | 199 | unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0; |
04fcd258 | 200 | u32 val; |
f5f1f614 | 201 | |
04fcd258 RQ |
202 | /* Clear ecc and enable bits */ |
203 | writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); | |
204 | ||
205 | /* program ecc and result sizes */ | |
206 | val = ((((nand->ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) | | |
207 | ECC1RESULTSIZE); | |
208 | writel(val, &gpmc_cfg->ecc_size_config); | |
209 | ||
210 | switch (mode) { | |
211 | case NAND_ECC_READ: | |
212 | case NAND_ECC_WRITE: | |
213 | writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); | |
f5f1f614 | 214 | break; |
04fcd258 RQ |
215 | case NAND_ECC_READSYN: |
216 | writel(ECCCLEAR, &gpmc_cfg->ecc_control); | |
46840f66 | 217 | break; |
f5f1f614 | 218 | default: |
04fcd258 RQ |
219 | printf("%s: error: unrecognized Mode[%d]!\n", __func__, mode); |
220 | break; | |
d016dc42 | 221 | } |
04fcd258 RQ |
222 | |
223 | /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */ | |
224 | val = (dev_width << 7) | (info->cs << 1) | (0x1); | |
225 | writel(val, &gpmc_cfg->ecc_config); | |
4a093006 AB |
226 | } |
227 | ||
228 | /* | |
71a7f956 | 229 | * omap_calculate_ecc - Read ECC result |
230 | * @mtd: MTD structure | |
231 | * @dat: unused | |
232 | * @ecc_code: ecc_code buffer | |
233 | * Using noninverted ECC can be considered ugly since writing a blank | |
234 | * page ie. padding will clear the ECC bytes. This is no problem as | |
235 | * long nobody is trying to write data on the seemingly unused page. | |
236 | * Reading an erased page will produce an ECC mismatch between | |
237 | * generated and read ECC bytes that has to be dealt with separately. | |
238 | * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC | |
239 | * is used, the result of read will be 0x0 while the ECC offsets of the | |
240 | * spare area will be 0xFF which will result in an ECC mismatch. | |
c3754e9c | 241 | */ |
71a7f956 | 242 | static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, |
c3754e9c | 243 | uint8_t *ecc_code) |
04fcd258 RQ |
244 | { |
245 | u32 val; | |
246 | ||
247 | val = readl(&gpmc_cfg->ecc1_result); | |
248 | ecc_code[0] = val & 0xFF; | |
249 | ecc_code[1] = (val >> 16) & 0xFF; | |
250 | ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
255 | /* GPMC ecc engine settings for read */ | |
256 | #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ | |
257 | #define BCH8R_ECC_SIZE0 0x1a /* ecc_size0 = 26 */ | |
258 | #define BCH8R_ECC_SIZE1 0x2 /* ecc_size1 = 2 */ | |
259 | #define BCH4R_ECC_SIZE0 0xd /* ecc_size0 = 13 */ | |
260 | #define BCH4R_ECC_SIZE1 0x3 /* ecc_size1 = 3 */ | |
261 | ||
262 | /* GPMC ecc engine settings for write */ | |
263 | #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ | |
264 | #define BCH_ECC_SIZE0 0x0 /* ecc_size0 = 0, no oob protection */ | |
265 | #define BCH_ECC_SIZE1 0x20 /* ecc_size1 = 32 */ | |
266 | ||
267 | /** | |
268 | * omap_enable_hwecc_bch - Program GPMC to perform BCH ECC calculation | |
269 | * @mtd: MTD device structure | |
270 | * @mode: Read/Write mode | |
271 | * | |
272 | * When using BCH with SW correction (i.e. no ELM), sector size is set | |
273 | * to 512 bytes and we use BCH_WRAPMODE_6 wrapping mode | |
274 | * for both reading and writing with: | |
275 | * eccsize0 = 0 (no additional protected byte in spare area) | |
276 | * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) | |
277 | */ | |
278 | static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, | |
279 | int mode) | |
280 | { | |
281 | unsigned int bch_type; | |
282 | unsigned int dev_width, nsectors; | |
283 | struct nand_chip *chip = mtd_to_nand(mtd); | |
284 | struct omap_nand_info *info = nand_get_controller_data(chip); | |
285 | u32 val, wr_mode; | |
286 | unsigned int ecc_size1, ecc_size0; | |
287 | ||
288 | /* GPMC configurations for calculating ECC */ | |
289 | switch (info->ecc_scheme) { | |
290 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
291 | bch_type = 1; | |
292 | nsectors = 1; | |
293 | wr_mode = BCH_WRAPMODE_6; | |
294 | ecc_size0 = BCH_ECC_SIZE0; | |
295 | ecc_size1 = BCH_ECC_SIZE1; | |
296 | break; | |
297 | case OMAP_ECC_BCH8_CODE_HW: | |
298 | bch_type = 1; | |
84e6fe3c | 299 | nsectors = 1; |
04fcd258 RQ |
300 | if (mode == NAND_ECC_READ) { |
301 | wr_mode = BCH_WRAPMODE_1; | |
302 | ecc_size0 = BCH8R_ECC_SIZE0; | |
303 | ecc_size1 = BCH8R_ECC_SIZE1; | |
304 | } else { | |
305 | wr_mode = BCH_WRAPMODE_6; | |
306 | ecc_size0 = BCH_ECC_SIZE0; | |
307 | ecc_size1 = BCH_ECC_SIZE1; | |
308 | } | |
309 | break; | |
310 | case OMAP_ECC_BCH16_CODE_HW: | |
311 | bch_type = 0x2; | |
84e6fe3c | 312 | nsectors = 1; |
04fcd258 RQ |
313 | if (mode == NAND_ECC_READ) { |
314 | wr_mode = 0x01; | |
315 | ecc_size0 = 52; /* ECC bits in nibbles per sector */ | |
316 | ecc_size1 = 0; /* non-ECC bits in nibbles per sector */ | |
317 | } else { | |
318 | wr_mode = 0x01; | |
319 | ecc_size0 = 0; /* extra bits in nibbles per sector */ | |
320 | ecc_size1 = 52; /* OOB bits in nibbles per sector */ | |
321 | } | |
322 | break; | |
323 | default: | |
324 | return; | |
325 | } | |
326 | ||
327 | writel(ECCRESULTREG1, &gpmc_cfg->ecc_control); | |
328 | ||
329 | /* Configure ecc size for BCH */ | |
330 | val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT); | |
331 | writel(val, &gpmc_cfg->ecc_size_config); | |
332 | ||
333 | dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; | |
334 | ||
335 | /* BCH configuration */ | |
336 | val = ((1 << 16) | /* enable BCH */ | |
337 | (bch_type << 12) | /* BCH4/BCH8/BCH16 */ | |
338 | (wr_mode << 8) | /* wrap mode */ | |
339 | (dev_width << 7) | /* bus width */ | |
340 | (((nsectors - 1) & 0x7) << 4) | /* number of sectors */ | |
341 | (info->cs << 1) | /* ECC CS */ | |
342 | (0x1)); /* enable ECC */ | |
343 | ||
344 | writel(val, &gpmc_cfg->ecc_config); | |
345 | ||
346 | /* Clear ecc and enable bits */ | |
347 | writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); | |
348 | } | |
349 | ||
350 | /** | |
84e6fe3c | 351 | * omap_calculate_ecc_bch - Generate BCH ECC bytes for one sector |
04fcd258 RQ |
352 | * @mtd: MTD device structure |
353 | * @dat: The pointer to data on which ecc is computed | |
354 | * @ecc_code: The ecc_code buffer | |
04fcd258 RQ |
355 | * |
356 | * Support calculating of BCH4/8/16 ECC vectors for one sector | |
357 | * within a page. Sector number is in @sector. | |
358 | */ | |
84e6fe3c RQ |
359 | static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd, const u8 *dat, |
360 | u8 *ecc_code) | |
c3754e9c | 361 | { |
17cb4b8f SW |
362 | struct nand_chip *chip = mtd_to_nand(mtd); |
363 | struct omap_nand_info *info = nand_get_controller_data(chip); | |
0568dd06 LM |
364 | const uint32_t *ptr; |
365 | uint32_t val = 0; | |
c3754e9c MA |
366 | int8_t i = 0, j; |
367 | ||
9233279f | 368 | switch (info->ecc_scheme) { |
71a7f956 | 369 | #ifdef CONFIG_BCH |
370 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
371 | #endif | |
372 | case OMAP_ECC_BCH8_CODE_HW: | |
84e6fe3c | 373 | ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3]; |
71a7f956 | 374 | val = readl(ptr); |
375 | ecc_code[i++] = (val >> 0) & 0xFF; | |
c3754e9c MA |
376 | ptr--; |
377 | for (j = 0; j < 3; j++) { | |
71a7f956 | 378 | val = readl(ptr); |
379 | ecc_code[i++] = (val >> 24) & 0xFF; | |
380 | ecc_code[i++] = (val >> 16) & 0xFF; | |
381 | ecc_code[i++] = (val >> 8) & 0xFF; | |
382 | ecc_code[i++] = (val >> 0) & 0xFF; | |
c3754e9c MA |
383 | ptr--; |
384 | } | |
04fcd258 | 385 | |
71a7f956 | 386 | break; |
46840f66 | 387 | case OMAP_ECC_BCH16_CODE_HW: |
84e6fe3c | 388 | val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]); |
46840f66 | 389 | ecc_code[i++] = (val >> 8) & 0xFF; |
390 | ecc_code[i++] = (val >> 0) & 0xFF; | |
84e6fe3c | 391 | val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]); |
46840f66 | 392 | ecc_code[i++] = (val >> 24) & 0xFF; |
393 | ecc_code[i++] = (val >> 16) & 0xFF; | |
394 | ecc_code[i++] = (val >> 8) & 0xFF; | |
395 | ecc_code[i++] = (val >> 0) & 0xFF; | |
84e6fe3c | 396 | val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]); |
46840f66 | 397 | ecc_code[i++] = (val >> 24) & 0xFF; |
398 | ecc_code[i++] = (val >> 16) & 0xFF; | |
399 | ecc_code[i++] = (val >> 8) & 0xFF; | |
400 | ecc_code[i++] = (val >> 0) & 0xFF; | |
401 | for (j = 3; j >= 0; j--) { | |
84e6fe3c | 402 | val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j] |
46840f66 | 403 | ); |
404 | ecc_code[i++] = (val >> 24) & 0xFF; | |
405 | ecc_code[i++] = (val >> 16) & 0xFF; | |
406 | ecc_code[i++] = (val >> 8) & 0xFF; | |
407 | ecc_code[i++] = (val >> 0) & 0xFF; | |
408 | } | |
409 | break; | |
71a7f956 | 410 | default: |
411 | return -EINVAL; | |
412 | } | |
413 | /* ECC scheme specific syndrome customizations */ | |
9233279f | 414 | switch (info->ecc_scheme) { |
71a7f956 | 415 | #ifdef CONFIG_BCH |
416 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
04fcd258 RQ |
417 | /* Add constant polynomial to remainder, so that |
418 | * ECC of blank pages results in 0x0 on reading back | |
419 | */ | |
71a7f956 | 420 | for (i = 0; i < chip->ecc.bytes; i++) |
04fcd258 | 421 | ecc_code[i] ^= bch8_polynomial[i]; |
71a7f956 | 422 | break; |
423 | #endif | |
424 | case OMAP_ECC_BCH8_CODE_HW: | |
04fcd258 RQ |
425 | /* Set 14th ECC byte as 0x0 for ROM compatibility */ |
426 | ecc_code[chip->ecc.bytes - 1] = 0x0; | |
71a7f956 | 427 | break; |
46840f66 | 428 | case OMAP_ECC_BCH16_CODE_HW: |
429 | break; | |
71a7f956 | 430 | default: |
431 | return -EINVAL; | |
c3754e9c | 432 | } |
71a7f956 | 433 | return 0; |
c3754e9c MA |
434 | } |
435 | ||
cd72a950 RQ |
436 | static inline void omap_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
437 | { | |
438 | struct nand_chip *chip = mtd_to_nand(mtd); | |
439 | struct omap_nand_info *info = nand_get_controller_data(chip); | |
440 | u32 alignment = ((uintptr_t)buf | len) & 3; | |
441 | ||
442 | if (alignment & 1) | |
443 | readsb(info->fifo, buf, len); | |
444 | else if (alignment & 3) | |
445 | readsw(info->fifo, buf, len >> 1); | |
446 | else | |
447 | readsl(info->fifo, buf, len >> 2); | |
448 | } | |
449 | ||
c0736114 JH |
450 | #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH |
451 | ||
452 | #define PREFETCH_CONFIG1_CS_SHIFT 24 | |
453 | #define PREFETCH_FIFOTHRESHOLD_MAX 0x40 | |
454 | #define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) | |
455 | #define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) | |
456 | #define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) | |
457 | #define ENABLE_PREFETCH (1 << 7) | |
458 | ||
459 | /** | |
460 | * omap_prefetch_enable - configures and starts prefetch transfer | |
461 | * @fifo_th: fifo threshold to be used for read/ write | |
462 | * @count: number of bytes to be transferred | |
463 | * @is_write: prefetch read(0) or write post(1) mode | |
464 | * @cs: chip select to use | |
465 | */ | |
466 | static int omap_prefetch_enable(int fifo_th, unsigned int count, int is_write, int cs) | |
467 | { | |
468 | uint32_t val; | |
469 | ||
470 | if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) | |
471 | return -EINVAL; | |
472 | ||
473 | if (readl(&gpmc_cfg->prefetch_control)) | |
474 | return -EBUSY; | |
475 | ||
476 | /* Set the amount of bytes to be prefetched */ | |
477 | writel(count, &gpmc_cfg->prefetch_config2); | |
478 | ||
479 | val = (cs << PREFETCH_CONFIG1_CS_SHIFT) | (is_write & 1) | | |
480 | PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH; | |
481 | writel(val, &gpmc_cfg->prefetch_config1); | |
482 | ||
483 | /* Start the prefetch engine */ | |
484 | writel(1, &gpmc_cfg->prefetch_control); | |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
489 | /** | |
490 | * omap_prefetch_reset - disables and stops the prefetch engine | |
491 | */ | |
492 | static void omap_prefetch_reset(void) | |
493 | { | |
494 | writel(0, &gpmc_cfg->prefetch_control); | |
495 | writel(0, &gpmc_cfg->prefetch_config1); | |
496 | } | |
497 | ||
498 | static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int len) | |
499 | { | |
500 | int ret; | |
501 | uint32_t cnt; | |
17cb4b8f | 502 | struct omap_nand_info *info = nand_get_controller_data(chip); |
c0736114 JH |
503 | |
504 | ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs); | |
505 | if (ret < 0) | |
506 | return ret; | |
507 | ||
508 | do { | |
509 | int i; | |
510 | ||
511 | cnt = readl(&gpmc_cfg->prefetch_status); | |
512 | cnt = PREFETCH_STATUS_FIFO_CNT(cnt); | |
513 | ||
514 | for (i = 0; i < cnt / 4; i++) { | |
cd72a950 | 515 | *buf++ = readl(info->fifo); |
c0736114 JH |
516 | len -= 4; |
517 | } | |
518 | } while (len); | |
519 | ||
520 | omap_prefetch_reset(); | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
cb2fc338 | 525 | static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len) |
c0736114 JH |
526 | { |
527 | int ret; | |
7e4a494c | 528 | uintptr_t head, tail; |
17cb4b8f | 529 | struct nand_chip *chip = mtd_to_nand(mtd); |
c0736114 JH |
530 | |
531 | /* | |
532 | * If the destination buffer is unaligned, start with reading | |
533 | * the overlap byte-wise. | |
534 | */ | |
7e4a494c | 535 | head = ((uintptr_t)buf) % 4; |
c0736114 | 536 | if (head) { |
cd72a950 | 537 | omap_nand_read_buf(mtd, buf, head); |
c0736114 JH |
538 | buf += head; |
539 | len -= head; | |
540 | } | |
541 | ||
542 | /* | |
543 | * Only transfer multiples of 4 bytes in a pre-fetched fashion. | |
544 | * If there's a residue, care for it byte-wise afterwards. | |
545 | */ | |
546 | tail = len % 4; | |
547 | ||
cb2fc338 | 548 | ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail); |
c0736114 JH |
549 | if (ret < 0) { |
550 | /* fallback in case the prefetch engine is busy */ | |
cd72a950 | 551 | omap_nand_read_buf(mtd, buf, len); |
c0736114 JH |
552 | } else if (tail) { |
553 | buf += len - tail; | |
cd72a950 | 554 | omap_nand_read_buf(mtd, buf, tail); |
c0736114 JH |
555 | } |
556 | } | |
557 | #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */ | |
558 | ||
71a7f956 | 559 | #ifdef CONFIG_NAND_OMAP_ELM |
04fcd258 | 560 | |
44152979 JH |
561 | /* |
562 | * omap_reverse_list - re-orders list elements in reverse order [internal] | |
563 | * @list: pointer to start of list | |
564 | * @length: length of list | |
565 | */ | |
566 | static void omap_reverse_list(u8 *list, unsigned int length) | |
567 | { | |
568 | unsigned int i, j; | |
569 | unsigned int half_length = length / 2; | |
570 | u8 tmp; | |
571 | for (i = 0, j = length - 1; i < half_length; i++, j--) { | |
572 | tmp = list[i]; | |
573 | list[i] = list[j]; | |
574 | list[j] = tmp; | |
575 | } | |
576 | } | |
577 | ||
c3754e9c MA |
578 | /* |
579 | * omap_correct_data_bch - Compares the ecc read from nand spare area | |
eae4b2b6 | 580 | * with ECC registers values and corrects one bit error if it has occurred |
c3754e9c MA |
581 | * |
582 | * @mtd: MTD device structure | |
583 | * @dat: page data | |
584 | * @read_ecc: ecc read from nand flash (ignored) | |
585 | * @calc_ecc: ecc read from ECC registers | |
586 | * | |
185f812c | 587 | * Return: 0 if data is OK or corrected, else returns -1 |
c3754e9c MA |
588 | */ |
589 | static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, | |
590 | uint8_t *read_ecc, uint8_t *calc_ecc) | |
591 | { | |
17cb4b8f SW |
592 | struct nand_chip *chip = mtd_to_nand(mtd); |
593 | struct omap_nand_info *info = nand_get_controller_data(chip); | |
a09431da | 594 | struct nand_ecc_ctrl *ecc = &chip->ecc; |
6e562b11 | 595 | uint32_t error_count = 0, error_max; |
46840f66 | 596 | uint32_t error_loc[ELM_MAX_ERROR_COUNT]; |
d21e77ff | 597 | enum bch_level bch_type; |
6e562b11 | 598 | uint32_t i, ecc_flag = 0; |
eb54d2c7 | 599 | uint8_t count; |
6e562b11 | 600 | uint32_t byte_pos, bit_pos; |
eb54d2c7 | 601 | int err = 0; |
6e562b11 | 602 | |
603 | /* check calculated ecc */ | |
a09431da | 604 | for (i = 0; i < ecc->bytes && !ecc_flag; i++) { |
6e562b11 | 605 | if (calc_ecc[i] != 0x00) |
f44bcb9f | 606 | goto not_ecc_match; |
6e562b11 | 607 | } |
f44bcb9f DR |
608 | return 0; |
609 | not_ecc_match: | |
c3754e9c | 610 | |
f44bcb9f DR |
611 | /* check for whether it's an erased-page */ |
612 | for (i = 0; i < ecc->bytes; i++) { | |
c3754e9c | 613 | if (read_ecc[i] != 0xff) |
f44bcb9f DR |
614 | goto not_erased; |
615 | } | |
616 | for (i = 0; i < SECTOR_BYTES; i++) { | |
617 | if (dat[i] != 0xff) | |
618 | goto not_erased; | |
619 | } | |
620 | return 0; | |
621 | not_erased: | |
622 | ||
623 | /* | |
624 | * Check for whether it's an erased page with a correctable | |
625 | * number of bitflips. Erased pages have all 1's in the data, | |
626 | * so we just compute the number of 0 bits in the data and | |
627 | * see if it's under the correction threshold. | |
628 | * | |
629 | * NOTE: The check for a perfect erased page above is faster for | |
630 | * the more common case, even though it's logically redundant. | |
631 | */ | |
632 | for (i = 0; i < ecc->bytes; i++) | |
633 | error_count += hweight8(~read_ecc[i]); | |
634 | ||
635 | for (i = 0; i < SECTOR_BYTES; i++) | |
636 | error_count += hweight8(~dat[i]); | |
637 | ||
638 | if (error_count <= ecc->strength) { | |
639 | memset(read_ecc, 0xFF, ecc->bytes); | |
640 | memset(dat, 0xFF, SECTOR_BYTES); | |
641 | debug("nand: %u bit-flip(s) corrected in erased page\n", | |
642 | error_count); | |
643 | return error_count; | |
6e562b11 | 644 | } |
c3754e9c | 645 | |
c3754e9c MA |
646 | /* |
647 | * while reading ECC result we read it in big endian. | |
648 | * Hence while loading to ELM we have rotate to get the right endian. | |
649 | */ | |
9233279f | 650 | switch (info->ecc_scheme) { |
6e562b11 | 651 | case OMAP_ECC_BCH8_CODE_HW: |
d21e77ff | 652 | bch_type = BCH_8_BIT; |
a09431da | 653 | omap_reverse_list(calc_ecc, ecc->bytes - 1); |
6e562b11 | 654 | break; |
46840f66 | 655 | case OMAP_ECC_BCH16_CODE_HW: |
656 | bch_type = BCH_16_BIT; | |
657 | omap_reverse_list(calc_ecc, ecc->bytes); | |
658 | break; | |
6e562b11 | 659 | default: |
660 | return -EINVAL; | |
661 | } | |
c3754e9c | 662 | /* use elm module to check for errors */ |
d21e77ff | 663 | elm_config(bch_type); |
f44bcb9f | 664 | error_count = 0; |
3f990dc8 | 665 | err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc); |
666 | if (err) | |
667 | return err; | |
668 | ||
c3754e9c | 669 | /* correct bch error */ |
6e562b11 | 670 | for (count = 0; count < error_count; count++) { |
9233279f | 671 | switch (info->ecc_scheme) { |
d21e77ff | 672 | case OMAP_ECC_BCH8_CODE_HW: |
6e562b11 | 673 | /* 14th byte in ECC is reserved to match ROM layout */ |
a09431da | 674 | error_max = SECTOR_BYTES + (ecc->bytes - 1); |
6e562b11 | 675 | break; |
46840f66 | 676 | case OMAP_ECC_BCH16_CODE_HW: |
677 | error_max = SECTOR_BYTES + ecc->bytes; | |
678 | break; | |
6e562b11 | 679 | default: |
680 | return -EINVAL; | |
681 | } | |
682 | byte_pos = error_max - (error_loc[count] / 8) - 1; | |
683 | bit_pos = error_loc[count] % 8; | |
684 | if (byte_pos < SECTOR_BYTES) { | |
685 | dat[byte_pos] ^= 1 << bit_pos; | |
d1d01676 | 686 | debug("nand: bit-flip corrected @data=%d\n", byte_pos); |
6e562b11 | 687 | } else if (byte_pos < error_max) { |
97eeae1a | 688 | read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos; |
d1d01676 | 689 | debug("nand: bit-flip corrected @oob=%d\n", byte_pos - |
6e562b11 | 690 | SECTOR_BYTES); |
691 | } else { | |
692 | err = -EBADMSG; | |
693 | printf("nand: error: invalid bit-flip location\n"); | |
694 | } | |
695 | } | |
696 | return (err) ? err : error_count; | |
c3754e9c | 697 | } |
c3754e9c MA |
698 | |
699 | /** | |
700 | * omap_read_page_bch - hardware ecc based page read function | |
701 | * @mtd: mtd info structure | |
702 | * @chip: nand chip info structure | |
703 | * @buf: buffer to store read data | |
dfe64e2c | 704 | * @oob_required: caller expects OOB data read to chip->oob_poi |
c3754e9c MA |
705 | * @page: page number to read |
706 | * | |
707 | */ | |
708 | static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, | |
dfe64e2c | 709 | uint8_t *buf, int oob_required, int page) |
c3754e9c MA |
710 | { |
711 | int i, eccsize = chip->ecc.size; | |
712 | int eccbytes = chip->ecc.bytes; | |
713 | int eccsteps = chip->ecc.steps; | |
714 | uint8_t *p = buf; | |
715 | uint8_t *ecc_calc = chip->buffers->ecccalc; | |
716 | uint8_t *ecc_code = chip->buffers->ecccode; | |
717 | uint32_t *eccpos = chip->ecc.layout->eccpos; | |
718 | uint8_t *oob = chip->oob_poi; | |
c3754e9c | 719 | uint32_t oob_pos; |
84e6fe3c | 720 | u32 data_pos = 0; |
c3754e9c | 721 | |
c3754e9c MA |
722 | /* oob area start */ |
723 | oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0]; | |
724 | oob += chip->ecc.layout->eccpos[0]; | |
725 | ||
84e6fe3c RQ |
726 | for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize, |
727 | oob += eccbytes) { | |
728 | /* Enable ECC engine */ | |
729 | chip->ecc.hwctl(mtd, NAND_ECC_READ); | |
04fcd258 | 730 | |
84e6fe3c RQ |
731 | /* read data */ |
732 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1); | |
733 | chip->read_buf(mtd, p, eccsize); | |
04fcd258 | 734 | |
84e6fe3c RQ |
735 | /* read respective ecc from oob area */ |
736 | chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1); | |
737 | chip->read_buf(mtd, oob, eccbytes); | |
738 | /* read syndrome */ | |
739 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); | |
04fcd258 | 740 | |
84e6fe3c RQ |
741 | data_pos += eccsize; |
742 | oob_pos += eccbytes; | |
743 | } | |
c3754e9c MA |
744 | |
745 | for (i = 0; i < chip->ecc.total; i++) | |
746 | ecc_code[i] = chip->oob_poi[eccpos[i]]; | |
747 | ||
04fcd258 | 748 | /* error detect & correct */ |
c3754e9c MA |
749 | eccsteps = chip->ecc.steps; |
750 | p = buf; | |
751 | ||
752 | for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { | |
753 | int stat; | |
c3754e9c MA |
754 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
755 | if (stat < 0) | |
756 | mtd->ecc_stats.failed++; | |
757 | else | |
758 | mtd->ecc_stats.corrected += stat; | |
759 | } | |
04fcd258 | 760 | |
c3754e9c MA |
761 | return 0; |
762 | } | |
d016dc42 | 763 | #endif /* CONFIG_NAND_OMAP_ELM */ |
c3754e9c | 764 | |
4a093006 AB |
765 | /* |
766 | * OMAP3 BCH8 support (with BCH library) | |
767 | */ | |
d016dc42 | 768 | #ifdef CONFIG_BCH |
4a093006 | 769 | /** |
d016dc42 | 770 | * omap_correct_data_bch_sw - Decode received data and correct errors |
4a093006 AB |
771 | * @mtd: MTD device structure |
772 | * @data: page data | |
773 | * @read_ecc: ecc read from nand flash | |
774 | * @calc_ecc: ecc read from HW ECC registers | |
775 | */ | |
d016dc42 | 776 | static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data, |
4a093006 AB |
777 | u_char *read_ecc, u_char *calc_ecc) |
778 | { | |
779 | int i, count; | |
780 | /* cannot correct more than 8 errors */ | |
781 | unsigned int errloc[8]; | |
17cb4b8f SW |
782 | struct nand_chip *chip = mtd_to_nand(mtd); |
783 | struct omap_nand_info *info = nand_get_controller_data(chip); | |
4a093006 | 784 | |
6fe7fe12 LM |
785 | count = decode_bch(info->control, NULL, SECTOR_BYTES, |
786 | read_ecc, calc_ecc, NULL, errloc); | |
4a093006 AB |
787 | if (count > 0) { |
788 | /* correct errors */ | |
789 | for (i = 0; i < count; i++) { | |
790 | /* correct data only, not ecc bytes */ | |
6fe7fe12 LM |
791 | if (errloc[i] < SECTOR_BYTES << 3) |
792 | data[errloc[i] >> 3] ^= 1 << (errloc[i] & 7); | |
d1d01676 | 793 | debug("corrected bitflip %u\n", errloc[i]); |
4a093006 AB |
794 | #ifdef DEBUG |
795 | puts("read_ecc: "); | |
796 | /* | |
797 | * BCH8 have 13 bytes of ECC; BCH4 needs adoption | |
798 | * here! | |
799 | */ | |
800 | for (i = 0; i < 13; i++) | |
801 | printf("%02x ", read_ecc[i]); | |
802 | puts("\n"); | |
803 | puts("calc_ecc: "); | |
804 | for (i = 0; i < 13; i++) | |
805 | printf("%02x ", calc_ecc[i]); | |
806 | puts("\n"); | |
807 | #endif | |
808 | } | |
809 | } else if (count < 0) { | |
810 | puts("ecc unrecoverable error\n"); | |
811 | } | |
812 | return count; | |
813 | } | |
814 | ||
815 | /** | |
816 | * omap_free_bch - Release BCH ecc resources | |
817 | * @mtd: MTD device structure | |
818 | */ | |
819 | static void __maybe_unused omap_free_bch(struct mtd_info *mtd) | |
820 | { | |
17cb4b8f SW |
821 | struct nand_chip *chip = mtd_to_nand(mtd); |
822 | struct omap_nand_info *info = nand_get_controller_data(chip); | |
4a093006 | 823 | |
9233279f | 824 | if (info->control) { |
825 | free_bch(info->control); | |
826 | info->control = NULL; | |
4a093006 AB |
827 | } |
828 | } | |
d016dc42 | 829 | #endif /* CONFIG_BCH */ |
830 | ||
831 | /** | |
832 | * omap_select_ecc_scheme - configures driver for particular ecc-scheme | |
833 | * @nand: NAND chip device structure | |
834 | * @ecc_scheme: ecc scheme to configure | |
835 | * @pagesize: number of main-area bytes per page of NAND device | |
836 | * @oobsize: number of OOB/spare bytes per page of NAND device | |
837 | */ | |
838 | static int omap_select_ecc_scheme(struct nand_chip *nand, | |
839 | enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) { | |
17cb4b8f | 840 | struct omap_nand_info *info = nand_get_controller_data(nand); |
ec2c9240 | 841 | struct nand_ecclayout *ecclayout = nand->ecc.layout; |
d016dc42 | 842 | int eccsteps = pagesize / SECTOR_BYTES; |
843 | int i; | |
844 | ||
845 | switch (ecc_scheme) { | |
846 | case OMAP_ECC_HAM1_CODE_SW: | |
847 | debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n"); | |
848 | /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are | |
849 | * initialized in nand_scan_tail(), so just set ecc.mode */ | |
9233279f | 850 | info->control = NULL; |
d016dc42 | 851 | nand->ecc.mode = NAND_ECC_SOFT; |
852 | nand->ecc.layout = NULL; | |
2528460c | 853 | nand->ecc.size = 0; |
d016dc42 | 854 | break; |
855 | ||
856 | case OMAP_ECC_HAM1_CODE_HW: | |
857 | debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n"); | |
858 | /* check ecc-scheme requirements before updating ecc info */ | |
859 | if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { | |
860 | printf("nand: error: insufficient OOB: require=%d\n", ( | |
861 | (3 * eccsteps) + BADBLOCK_MARKER_LENGTH)); | |
862 | return -EINVAL; | |
863 | } | |
9233279f | 864 | info->control = NULL; |
d016dc42 | 865 | /* populate ecc specific fields */ |
fcd05245 | 866 | memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); |
d016dc42 | 867 | nand->ecc.mode = NAND_ECC_HW; |
868 | nand->ecc.strength = 1; | |
869 | nand->ecc.size = SECTOR_BYTES; | |
870 | nand->ecc.bytes = 3; | |
871 | nand->ecc.hwctl = omap_enable_hwecc; | |
872 | nand->ecc.correct = omap_correct_data; | |
873 | nand->ecc.calculate = omap_calculate_ecc; | |
874 | /* define ecc-layout */ | |
875 | ecclayout->eccbytes = nand->ecc.bytes * eccsteps; | |
69cc97f8 | 876 | for (i = 0; i < ecclayout->eccbytes; i++) { |
877 | if (nand->options & NAND_BUSWIDTH_16) | |
878 | ecclayout->eccpos[i] = i + 2; | |
879 | else | |
880 | ecclayout->eccpos[i] = i + 1; | |
881 | } | |
d016dc42 | 882 | ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; |
883 | ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - | |
884 | BADBLOCK_MARKER_LENGTH; | |
d016dc42 | 885 | break; |
886 | ||
887 | case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: | |
888 | #ifdef CONFIG_BCH | |
889 | debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); | |
890 | /* check ecc-scheme requirements before updating ecc info */ | |
891 | if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { | |
892 | printf("nand: error: insufficient OOB: require=%d\n", ( | |
893 | (13 * eccsteps) + BADBLOCK_MARKER_LENGTH)); | |
894 | return -EINVAL; | |
895 | } | |
896 | /* check if BCH S/W library can be used for error detection */ | |
9233279f | 897 | info->control = init_bch(13, 8, 0x201b); |
898 | if (!info->control) { | |
d016dc42 | 899 | printf("nand: error: could not init_bch()\n"); |
900 | return -ENODEV; | |
901 | } | |
d016dc42 | 902 | /* populate ecc specific fields */ |
fcd05245 | 903 | memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); |
d016dc42 | 904 | nand->ecc.mode = NAND_ECC_HW; |
905 | nand->ecc.strength = 8; | |
906 | nand->ecc.size = SECTOR_BYTES; | |
907 | nand->ecc.bytes = 13; | |
04fcd258 | 908 | nand->ecc.hwctl = omap_enable_hwecc_bch; |
d016dc42 | 909 | nand->ecc.correct = omap_correct_data_bch_sw; |
04fcd258 | 910 | nand->ecc.calculate = omap_calculate_ecc_bch; |
84e6fe3c | 911 | nand->ecc.steps = eccsteps; |
d016dc42 | 912 | /* define ecc-layout */ |
913 | ecclayout->eccbytes = nand->ecc.bytes * eccsteps; | |
914 | ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; | |
915 | for (i = 1; i < ecclayout->eccbytes; i++) { | |
916 | if (i % nand->ecc.bytes) | |
917 | ecclayout->eccpos[i] = | |
918 | ecclayout->eccpos[i - 1] + 1; | |
919 | else | |
920 | ecclayout->eccpos[i] = | |
921 | ecclayout->eccpos[i - 1] + 2; | |
922 | } | |
923 | ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; | |
924 | ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - | |
925 | BADBLOCK_MARKER_LENGTH; | |
d016dc42 | 926 | break; |
927 | #else | |
928 | printf("nand: error: CONFIG_BCH required for ECC\n"); | |
929 | return -EINVAL; | |
930 | #endif | |
931 | ||
932 | case OMAP_ECC_BCH8_CODE_HW: | |
933 | #ifdef CONFIG_NAND_OMAP_ELM | |
934 | debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n"); | |
935 | /* check ecc-scheme requirements before updating ecc info */ | |
936 | if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { | |
937 | printf("nand: error: insufficient OOB: require=%d\n", ( | |
938 | (14 * eccsteps) + BADBLOCK_MARKER_LENGTH)); | |
939 | return -EINVAL; | |
940 | } | |
941 | /* intialize ELM for ECC error detection */ | |
942 | elm_init(); | |
9233279f | 943 | info->control = NULL; |
d016dc42 | 944 | /* populate ecc specific fields */ |
fcd05245 | 945 | memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl)); |
d016dc42 | 946 | nand->ecc.mode = NAND_ECC_HW; |
947 | nand->ecc.strength = 8; | |
948 | nand->ecc.size = SECTOR_BYTES; | |
949 | nand->ecc.bytes = 14; | |
04fcd258 | 950 | nand->ecc.hwctl = omap_enable_hwecc_bch; |
d016dc42 | 951 | nand->ecc.correct = omap_correct_data_bch; |
04fcd258 | 952 | nand->ecc.calculate = omap_calculate_ecc_bch; |
d016dc42 | 953 | nand->ecc.read_page = omap_read_page_bch; |
84e6fe3c | 954 | nand->ecc.steps = eccsteps; |
d016dc42 | 955 | /* define ecc-layout */ |
956 | ecclayout->eccbytes = nand->ecc.bytes * eccsteps; | |
957 | for (i = 0; i < ecclayout->eccbytes; i++) | |
958 | ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; | |
959 | ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; | |
960 | ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - | |
961 | BADBLOCK_MARKER_LENGTH; | |
d016dc42 | 962 | break; |
963 | #else | |
964 | printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n"); | |
965 | return -EINVAL; | |
966 | #endif | |
967 | ||
46840f66 | 968 | case OMAP_ECC_BCH16_CODE_HW: |
969 | #ifdef CONFIG_NAND_OMAP_ELM | |
970 | debug("nand: using OMAP_ECC_BCH16_CODE_HW\n"); | |
971 | /* check ecc-scheme requirements before updating ecc info */ | |
972 | if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { | |
973 | printf("nand: error: insufficient OOB: require=%d\n", ( | |
974 | (26 * eccsteps) + BADBLOCK_MARKER_LENGTH)); | |
975 | return -EINVAL; | |
976 | } | |
977 | /* intialize ELM for ECC error detection */ | |
978 | elm_init(); | |
979 | /* populate ecc specific fields */ | |
980 | nand->ecc.mode = NAND_ECC_HW; | |
981 | nand->ecc.size = SECTOR_BYTES; | |
982 | nand->ecc.bytes = 26; | |
983 | nand->ecc.strength = 16; | |
04fcd258 | 984 | nand->ecc.hwctl = omap_enable_hwecc_bch; |
46840f66 | 985 | nand->ecc.correct = omap_correct_data_bch; |
04fcd258 | 986 | nand->ecc.calculate = omap_calculate_ecc_bch; |
46840f66 | 987 | nand->ecc.read_page = omap_read_page_bch; |
84e6fe3c | 988 | nand->ecc.steps = eccsteps; |
46840f66 | 989 | /* define ecc-layout */ |
990 | ecclayout->eccbytes = nand->ecc.bytes * eccsteps; | |
991 | for (i = 0; i < ecclayout->eccbytes; i++) | |
992 | ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; | |
993 | ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; | |
994 | ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes - | |
995 | BADBLOCK_MARKER_LENGTH; | |
996 | break; | |
997 | #else | |
998 | printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n"); | |
999 | return -EINVAL; | |
1000 | #endif | |
d016dc42 | 1001 | default: |
1002 | debug("nand: error: ecc scheme not enabled or supported\n"); | |
1003 | return -EINVAL; | |
1004 | } | |
eb237a15 NK |
1005 | |
1006 | /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */ | |
1007 | if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW) | |
1008 | nand->ecc.layout = ecclayout; | |
1009 | ||
9233279f | 1010 | info->ecc_scheme = ecc_scheme; |
d016dc42 | 1011 | return 0; |
1012 | } | |
4a093006 | 1013 | |
12c2f1ee | 1014 | #ifndef CONFIG_SPL_BUILD |
12201a13 | 1015 | /* |
da634ae3 AB |
1016 | * omap_nand_switch_ecc - switch the ECC operation between different engines |
1017 | * (h/w and s/w) and different algorithms (hamming and BCHx) | |
12201a13 | 1018 | * |
da634ae3 AB |
1019 | * @hardware - true if one of the HW engines should be used |
1020 | * @eccstrength - the number of bits that could be corrected | |
1021 | * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16) | |
12201a13 | 1022 | */ |
d016dc42 | 1023 | int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) |
12201a13 DB |
1024 | { |
1025 | struct nand_chip *nand; | |
ad92dff2 | 1026 | struct mtd_info *mtd = get_nand_dev_by_index(nand_curr_device); |
d016dc42 | 1027 | int err = 0; |
12201a13 | 1028 | |
ad92dff2 | 1029 | if (!mtd) { |
d016dc42 | 1030 | printf("nand: error: no NAND devices found\n"); |
1031 | return -ENODEV; | |
12201a13 DB |
1032 | } |
1033 | ||
17cb4b8f | 1034 | nand = mtd_to_nand(mtd); |
12201a13 | 1035 | nand->options |= NAND_OWN_BUFFERS; |
13fbde6e | 1036 | nand->options &= ~NAND_SUBPAGE_READ; |
12201a13 | 1037 | /* Setup the ecc configurations again */ |
da634ae3 AB |
1038 | if (hardware) { |
1039 | if (eccstrength == 1) { | |
d016dc42 | 1040 | err = omap_select_ecc_scheme(nand, |
1041 | OMAP_ECC_HAM1_CODE_HW, | |
1042 | mtd->writesize, mtd->oobsize); | |
1043 | } else if (eccstrength == 8) { | |
1044 | err = omap_select_ecc_scheme(nand, | |
1045 | OMAP_ECC_BCH8_CODE_HW, | |
1046 | mtd->writesize, mtd->oobsize); | |
3a504d96 HS |
1047 | } else if (eccstrength == 16) { |
1048 | err = omap_select_ecc_scheme(nand, | |
1049 | OMAP_ECC_BCH16_CODE_HW, | |
1050 | mtd->writesize, mtd->oobsize); | |
d016dc42 | 1051 | } else { |
1052 | printf("nand: error: unsupported ECC scheme\n"); | |
1053 | return -EINVAL; | |
da634ae3 | 1054 | } |
12201a13 | 1055 | } else { |
b050898e AC |
1056 | if (eccstrength == 1) { |
1057 | err = omap_select_ecc_scheme(nand, | |
1058 | OMAP_ECC_HAM1_CODE_SW, | |
1059 | mtd->writesize, mtd->oobsize); | |
1060 | } else if (eccstrength == 8) { | |
1061 | err = omap_select_ecc_scheme(nand, | |
1062 | OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, | |
d016dc42 | 1063 | mtd->writesize, mtd->oobsize); |
b050898e AC |
1064 | } else { |
1065 | printf("nand: error: unsupported ECC scheme\n"); | |
1066 | return -EINVAL; | |
1067 | } | |
12201a13 DB |
1068 | } |
1069 | ||
1070 | /* Update NAND handling after ECC mode switch */ | |
d016dc42 | 1071 | if (!err) |
1072 | err = nand_scan_tail(mtd); | |
1073 | return err; | |
12201a13 | 1074 | } |
12c2f1ee | 1075 | #endif /* CONFIG_SPL_BUILD */ |
12201a13 DB |
1076 | |
1077 | /* | |
1078 | * Board-specific NAND initialization. The following members of the | |
1079 | * argument are board-specific: | |
1080 | * - IO_ADDR_R: address to read the 8 I/O lines of the flash device | |
1081 | * - IO_ADDR_W: address to write the 8 I/O lines of the flash device | |
1082 | * - cmd_ctrl: hardwarespecific function for accesing control-lines | |
1083 | * - waitfunc: hardwarespecific function for accesing device ready/busy line | |
1084 | * - ecc.hwctl: function to enable (reset) hardware ecc generator | |
1085 | * - ecc.mode: mode of ecc, see defines | |
1086 | * - chip_delay: chip dependent delay for transfering data from array to | |
1087 | * read regs (tR) | |
1088 | * - options: various chip options. They can partly be set to inform | |
1089 | * nand_scan about special functionality. See the defines for further | |
1090 | * explanation | |
1091 | */ | |
dd01a229 | 1092 | int gpmc_nand_init(struct nand_chip *nand, void __iomem *nand_base) |
12201a13 DB |
1093 | { |
1094 | int32_t gpmc_config = 0; | |
5c3f7e0e | 1095 | int cs = cs_next++; |
d016dc42 | 1096 | int err = 0; |
cd72a950 RQ |
1097 | struct omap_nand_info *info; |
1098 | ||
12201a13 DB |
1099 | /* |
1100 | * xloader/Uboot's gpmc configuration would have configured GPMC for | |
1101 | * nand type of memory. The following logic scans and latches on to the | |
1102 | * first CS with NAND type memory. | |
1103 | * TBD: need to make this logic generic to handle multiple CS NAND | |
1104 | * devices. | |
1105 | */ | |
1106 | while (cs < GPMC_MAX_CS) { | |
12201a13 | 1107 | /* Check if NAND type is set */ |
89411352 | 1108 | if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) { |
12201a13 DB |
1109 | /* Found it!! */ |
1110 | break; | |
1111 | } | |
1112 | cs++; | |
1113 | } | |
1114 | if (cs >= GPMC_MAX_CS) { | |
d016dc42 | 1115 | printf("nand: error: Unable to find NAND settings in " |
12201a13 DB |
1116 | "GPMC Configuration - quitting\n"); |
1117 | return -ENODEV; | |
1118 | } | |
1119 | ||
89411352 | 1120 | gpmc_config = readl(&gpmc_cfg->config); |
12201a13 DB |
1121 | /* Disable Write protect */ |
1122 | gpmc_config |= 0x10; | |
89411352 | 1123 | writel(gpmc_config, &gpmc_cfg->config); |
12201a13 | 1124 | |
89411352 DB |
1125 | nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; |
1126 | nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; | |
cd72a950 RQ |
1127 | |
1128 | info = &omap_nand_info[cs]; | |
1129 | info->control = NULL; | |
1130 | info->cs = cs; | |
1131 | info->ws = wscfg[cs]; | |
dd01a229 | 1132 | info->fifo = nand_base; |
17cb4b8f | 1133 | nand_set_controller_data(nand, &omap_nand_info[cs]); |
d016dc42 | 1134 | nand->cmd_ctrl = omap_nand_hwcontrol; |
1135 | nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; | |
12201a13 | 1136 | nand->chip_delay = 100; |
ec2c9240 RQ |
1137 | nand->ecc.layout = kzalloc(sizeof(*nand->ecc.layout), GFP_KERNEL); |
1138 | if (!nand->ecc.layout) | |
1139 | return -ENOMEM; | |
d016dc42 | 1140 | |
b80a6603 | 1141 | /* configure driver and controller based on NAND device bus-width */ |
1142 | gpmc_config = readl(&gpmc_cfg->cs[cs].config1); | |
1143 | #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT) | |
1144 | nand->options |= NAND_BUSWIDTH_16; | |
1145 | writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1); | |
1146 | #else | |
1147 | nand->options &= ~NAND_BUSWIDTH_16; | |
1148 | writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1); | |
1149 | #endif | |
d016dc42 | 1150 | /* select ECC scheme */ |
3f719069 | 1151 | #if defined(CONFIG_NAND_OMAP_ECCSCHEME) |
1152 | err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME, | |
d016dc42 | 1153 | CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); |
3f719069 | 1154 | #else |
1155 | /* pagesize and oobsize are not required to configure sw ecc-scheme */ | |
d016dc42 | 1156 | err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, |
1157 | 0, 0); | |
c3754e9c | 1158 | #endif |
d016dc42 | 1159 | if (err) |
1160 | return err; | |
12c2f1ee | 1161 | |
89831112 | 1162 | #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH |
cb2fc338 | 1163 | nand->read_buf = omap_nand_read_prefetch; |
89831112 | 1164 | #else |
cd72a950 | 1165 | nand->read_buf = omap_nand_read_buf; |
12c2f1ee | 1166 | #endif |
fb384c47 SR |
1167 | |
1168 | nand->dev_ready = omap_dev_ready; | |
1169 | ||
12201a13 DB |
1170 | return 0; |
1171 | } | |
ff0d0789 RQ |
1172 | |
1173 | /* First NAND chip for SPL use only */ | |
1174 | static __maybe_unused struct nand_chip *nand_chip; | |
1175 | ||
1176 | #if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT) | |
1177 | ||
1178 | static int gpmc_nand_probe(struct udevice *dev) | |
1179 | { | |
1180 | struct nand_chip *nand = dev_get_priv(dev); | |
1181 | struct mtd_info *mtd = nand_to_mtd(nand); | |
dd01a229 RQ |
1182 | struct resource res; |
1183 | void __iomem *base; | |
ff0d0789 RQ |
1184 | int ret; |
1185 | ||
dd01a229 RQ |
1186 | ret = dev_read_resource(dev, 0, &res); |
1187 | if (ret) | |
1188 | return ret; | |
1189 | ||
1190 | base = devm_ioremap(dev, res.start, resource_size(&res)); | |
1191 | gpmc_nand_init(nand, base); | |
e76959ab RQ |
1192 | mtd->dev = dev; |
1193 | nand_set_flash_node(nand, dev_ofnode(dev)); | |
ff0d0789 RQ |
1194 | |
1195 | ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS); | |
1196 | if (ret) | |
1197 | return ret; | |
1198 | ||
1199 | ret = nand_register(0, mtd); | |
1200 | if (ret) | |
1201 | return ret; | |
1202 | ||
1203 | if (!nand_chip) | |
1204 | nand_chip = nand; | |
1205 | ||
1206 | return 0; | |
1207 | } | |
1208 | ||
1209 | static const struct udevice_id gpmc_nand_ids[] = { | |
1210 | { .compatible = "ti,am64-nand" }, | |
1211 | { .compatible = "ti,omap2-nand" }, | |
1212 | { } | |
1213 | }; | |
1214 | ||
1215 | U_BOOT_DRIVER(gpmc_nand) = { | |
1216 | .name = "gpmc-nand", | |
1217 | .id = UCLASS_MTD, | |
1218 | .of_match = gpmc_nand_ids, | |
1219 | .probe = gpmc_nand_probe, | |
1220 | .priv_auto = sizeof(struct nand_chip), | |
1221 | }; | |
1222 | ||
1223 | void board_nand_init(void) | |
1224 | { | |
1225 | struct udevice *dev; | |
1226 | int ret; | |
1227 | ||
7363cf05 RQ |
1228 | #ifdef CONFIG_NAND_OMAP_ELM |
1229 | ret = uclass_get_device_by_driver(UCLASS_MTD, | |
1230 | DM_DRIVER_GET(gpmc_elm), &dev); | |
1231 | if (ret && ret != -ENODEV) { | |
1232 | pr_err("%s: Failed to get ELM device: %d\n", __func__, ret); | |
1233 | return; | |
1234 | } | |
1235 | #endif | |
1236 | ||
ff0d0789 RQ |
1237 | ret = uclass_get_device_by_driver(UCLASS_MTD, |
1238 | DM_DRIVER_GET(gpmc_nand), &dev); | |
1239 | if (ret && ret != -ENODEV) | |
1240 | pr_err("%s: Failed to get GPMC device: %d\n", __func__, ret); | |
1241 | } | |
1242 | ||
1243 | #else | |
1244 | ||
1245 | int board_nand_init(struct nand_chip *nand) | |
1246 | { | |
dd01a229 | 1247 | return gpmc_nand_init(nand, (void __iomem *)CFG_SYS_NAND_BASE); |
ff0d0789 RQ |
1248 | } |
1249 | ||
1250 | #endif /* CONFIG_SYS_NAND_SELF_INIT */ | |
b7470907 RQ |
1251 | |
1252 | #if defined(CONFIG_SPL_NAND_INIT) | |
1253 | ||
1254 | /* nand_init() is provided by nand.c */ | |
1255 | ||
1256 | /* Unselect after operation */ | |
1257 | void nand_deselect(void) | |
1258 | { | |
1259 | struct mtd_info *mtd = nand_to_mtd(nand_chip); | |
1260 | ||
1261 | if (nand_chip->select_chip) | |
1262 | nand_chip->select_chip(mtd, -1); | |
1263 | } | |
1264 | ||
1265 | static int nand_is_bad_block(int block) | |
1266 | { | |
1267 | struct mtd_info *mtd = nand_to_mtd(nand_chip); | |
1268 | ||
1269 | loff_t ofs = block * CONFIG_SYS_NAND_BLOCK_SIZE; | |
1270 | ||
1271 | return nand_chip->block_bad(mtd, ofs); | |
1272 | } | |
1273 | ||
1274 | static int nand_read_page(int block, int page, uchar *dst) | |
1275 | { | |
601b8901 | 1276 | int page_addr = block * SYS_NAND_BLOCK_PAGES + page; |
b7470907 RQ |
1277 | loff_t ofs = page_addr * CONFIG_SYS_NAND_PAGE_SIZE; |
1278 | int ret; | |
1279 | size_t len = CONFIG_SYS_NAND_PAGE_SIZE; | |
1280 | struct mtd_info *mtd = nand_to_mtd(nand_chip); | |
1281 | ||
1282 | ret = nand_read(mtd, ofs, &len, dst); | |
1283 | if (ret) | |
1284 | printf("nand_read failed %d\n", ret); | |
1285 | ||
1286 | return ret; | |
1287 | } | |
1288 | ||
1289 | #include "nand_spl_loaders.c" | |
1290 | #endif /* CONFIG_SPL_NAND_INIT */ |