]> git.ipfire.org Git - people/ms/u-boot.git/blame - drivers/mtd/spi/macronix.c
sf: macronix: disable write protection when initializing
[people/ms/u-boot.git] / drivers / mtd / spi / macronix.c
CommitLineData
7ce6031a
PW
1/*
2 * Copyright 2009(C) Marvell International Ltd. and its affiliates
3 * Prafulla Wadaskar <prafulla@marvell.com>
4 *
5 * Based on drivers/mtd/spi/stmicro.c
6 *
7 * Copyright 2008, Network Appliance Inc.
8 * Jason McMullan <mcmullan@netapp.com>
9 *
10 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
11 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
29 * MA 02110-1301 USA
30 */
31
32#include <common.h>
33#include <malloc.h>
34#include <spi_flash.h>
35
36#include "spi_flash_internal.h"
37
38/* MX25xx-specific commands */
39#define CMD_MX25XX_WREN 0x06 /* Write Enable */
40#define CMD_MX25XX_WRDI 0x04 /* Write Disable */
41#define CMD_MX25XX_RDSR 0x05 /* Read Status Register */
42#define CMD_MX25XX_WRSR 0x01 /* Write Status Register */
43#define CMD_MX25XX_READ 0x03 /* Read Data Bytes */
44#define CMD_MX25XX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
45#define CMD_MX25XX_PP 0x02 /* Page Program */
46#define CMD_MX25XX_SE 0x20 /* Sector Erase */
47#define CMD_MX25XX_BE 0xD8 /* Block Erase */
48#define CMD_MX25XX_CE 0xc7 /* Chip Erase */
49#define CMD_MX25XX_DP 0xb9 /* Deep Power-down */
50#define CMD_MX25XX_RES 0xab /* Release from DP, and Read Signature */
51
7ce6031a 52struct macronix_spi_flash_params {
2efee52b 53 u16 idcode;
7ce6031a
PW
54 u16 page_size;
55 u16 pages_per_sector;
56 u16 sectors_per_block;
57 u16 nr_blocks;
58 const char *name;
59};
60
7ce6031a 61static const struct macronix_spi_flash_params macronix_spi_flash_table[] = {
2d722e05
ML
62 {
63 .idcode = 0x2013,
64 .page_size = 256,
65 .pages_per_sector = 16,
66 .sectors_per_block = 16,
67 .nr_blocks = 8,
68 .name = "MX25L4005",
69 },
70 {
71 .idcode = 0x2014,
72 .page_size = 256,
73 .pages_per_sector = 16,
74 .sectors_per_block = 16,
75 .nr_blocks = 16,
76 .name = "MX25L8005",
77 },
7ce6031a 78 {
2efee52b
PW
79 .idcode = 0x2015,
80 .page_size = 256,
81 .pages_per_sector = 16,
82 .sectors_per_block = 16,
83 .nr_blocks = 32,
84 .name = "MX25L1605D",
85 },
86 {
87 .idcode = 0x2016,
88 .page_size = 256,
89 .pages_per_sector = 16,
90 .sectors_per_block = 16,
91 .nr_blocks = 64,
92 .name = "MX25L3205D",
93 },
94 {
95 .idcode = 0x2017,
96 .page_size = 256,
97 .pages_per_sector = 16,
98 .sectors_per_block = 16,
99 .nr_blocks = 128,
100 .name = "MX25L6405D",
101 },
102 {
103 .idcode = 0x2018,
7ce6031a
PW
104 .page_size = 256,
105 .pages_per_sector = 16,
106 .sectors_per_block = 16,
107 .nr_blocks = 256,
108 .name = "MX25L12805D",
109 },
2efee52b
PW
110 {
111 .idcode = 0x2618,
112 .page_size = 256,
113 .pages_per_sector = 16,
114 .sectors_per_block = 16,
115 .nr_blocks = 256,
116 .name = "MX25L12855E",
117 },
7ce6031a
PW
118};
119
7432ed05
SG
120static int macronix_write_status(struct spi_flash *flash, u8 sr)
121{
122 u8 cmd;
123 int ret;
124
125 ret = spi_flash_cmd_write_enable(flash);
126 if (ret < 0) {
127 debug("SF: enabling write failed\n");
128 return ret;
129 }
130
131 cmd = CMD_MX25XX_WRSR;
132 ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &sr, 1);
133 if (ret) {
134 debug("SF: fail to write status register\n");
135 return ret;
136 }
137
138 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
139 if (ret < 0) {
140 debug("SF: write status register timed out\n");
141 return ret;
142 }
143
144 return 0;
145}
146
147static int macronix_unlock(struct spi_flash *flash)
148{
149 int ret;
150
151 /* Enable status register writing and clear BP# bits */
152 ret = macronix_write_status(flash, 0);
153 if (ret)
154 debug("SF: fail to disable write protection\n");
155
156 return ret;
157}
158
f8f0757d 159static int macronix_erase(struct spi_flash *flash, u32 offset, size_t len)
7ce6031a 160{
4e6a5158 161 return spi_flash_cmd_erase(flash, CMD_MX25XX_BE, offset, len);
7ce6031a
PW
162}
163
164struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode)
165{
166 const struct macronix_spi_flash_params *params;
b06afa75 167 struct spi_flash *flash;
7ce6031a 168 unsigned int i;
2efee52b 169 u16 id = idcode[2] | idcode[1] << 8;
7ce6031a
PW
170
171 for (i = 0; i < ARRAY_SIZE(macronix_spi_flash_table); i++) {
172 params = &macronix_spi_flash_table[i];
2efee52b 173 if (params->idcode == id)
7ce6031a
PW
174 break;
175 }
176
177 if (i == ARRAY_SIZE(macronix_spi_flash_table)) {
2efee52b 178 debug("SF: Unsupported Macronix ID %04x\n", id);
7ce6031a
PW
179 return NULL;
180 }
181
b06afa75
MF
182 flash = malloc(sizeof(*flash));
183 if (!flash) {
7ce6031a
PW
184 debug("SF: Failed to allocate memory\n");
185 return NULL;
186 }
187
b06afa75
MF
188 flash->spi = spi;
189 flash->name = params->name;
7ce6031a 190
b06afa75
MF
191 flash->write = spi_flash_cmd_write_multi;
192 flash->erase = macronix_erase;
193 flash->read = spi_flash_cmd_read_fast;
194 flash->page_size = params->page_size;
195 flash->sector_size = params->page_size * params->pages_per_sector
4e6a5158 196 * params->sectors_per_block;
b06afa75 197 flash->size = flash->sector_size * params->nr_blocks;
7ce6031a 198
7432ed05
SG
199 /* Clear BP# bits for read-only flash */
200 macronix_unlock(flash);
201
b06afa75 202 return flash;
7ce6031a 203}