[people/ms/u-boot.git] / drivers / net / dm9000x.c

/*
  dm9000.c: Version 1.2 12/15/2003

	A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
	Copyright (C) 1997  Sten Wang

	This program is free software; you can redistribute it and/or
	modify it under the terms of the GNU General Public License
	as published by the Free Software Foundation; either version 2
	of the License, or (at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
	GNU General Public License for more details.

  (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.

V0.11	06/20/2001	REG_0A bit3=1, default enable BP with DA match
	06/22/2001	Support DM9801 progrmming
			E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
			E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
		R17 = (R17 & 0xfff0) | NF + 3
			E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
		R17 = (R17 & 0xfff0) | NF

v1.00			modify by simon 2001.9.5
	                change for kernel 2.4.x

v1.1   11/09/2001	fix force mode bug

v1.2   03/18/2003       Weilun Huang <weilun_huang@davicom.com.tw>:
			Fixed phy reset.
			Added tx/rx 32 bit mode.
			Cleaned up for kernel merge.

--------------------------------------

       12/15/2003       Initial port to u-boot by
       			Sascha Hauer <saschahauer@web.de>

       06/03/2008	Remy Bohmer <linux@bohmer.net>
			- Fixed the driver to work with DM9000A.
			  (check on ISR receive status bit before reading the
			  FIFO as described in DM9000 programming guide and
			  application notes)
			- Added autodetect of databus width.
			- Made debug code compile again.
			- Adapt eth_send such that it matches the DM9000*
			  application notes. Needed to make it work properly
			  for DM9000A.
			- Adapted reset procedure to match DM9000 application
			  notes (i.e. double reset)
			- some minor code cleanups
			These changes are tested with DM9000{A,EP,E} together
			with a 200MHz Atmel AT91SAM92161 core

TODO: external MII is not functional, only internal at the moment.
*/

#include <common.h>
#include <command.h>
#include <net.h>
#include <asm/io.h>

#include "dm9000x.h"

/* Board/System/Debug information/definition ---------------- */

/* #define CONFIG_DM9000_DEBUG */

#ifdef CONFIG_DM9000_DEBUG
#define DM9000_DBG(fmt,args...) printf(fmt, ##args)
#define DM9000_DMP_PACKET(func,packet,length)  \
	do { \
		int i; 							\
		printf(func ": length: %d\n", length);			\
		for (i = 0; i < length; i++) {				\
			if (i % 8 == 0)					\
				printf("\n%s: %02x: ", func, i);	\
			printf("%02x ", ((unsigned char *) packet)[i]);	\
		} printf("\n");						\
	} while(0)
#else
#define DM9000_DBG(fmt,args...)
#define DM9000_DMP_PACKET(func,packet,length)
#endif

/* Structure/enum declaration ------------------------------- */
typedef struct board_info {
	u32 runt_length_counter;	/* counter: RX length < 64byte */
	u32 long_length_counter;	/* counter: RX length > 1514byte */
	u32 reset_counter;	/* counter: RESET */
	u32 reset_tx_timeout;	/* RESET caused by TX Timeout */
	u32 reset_rx_status;	/* RESET caused by RX Statsus wrong */
	u16 tx_pkt_cnt;
	u16 queue_start_addr;
	u16 dbug_cnt;
	u8 phy_addr;
	u8 device_wait_reset;	/* device state */
	unsigned char srom[128];
	void (*outblk)(volatile void *data_ptr, int count);
	void (*inblk)(void *data_ptr, int count);
	void (*rx_status)(u16 *RxStatus, u16 *RxLen);
} board_info_t;
static board_info_t dm9000_info;

/* function declaration ------------------------------------- */
int eth_init(bd_t * bd);
int eth_send(volatile void *, int);
int eth_rx(void);
void eth_halt(void);
static int dm9000_probe(void);
static u16 phy_read(int);
static void phy_write(int, u16);
u16 read_srom_word(int);
static u8 DM9000_ior(int);
static void DM9000_iow(int reg, u8 value);

/* DM9000 network board routine ---------------------------- */

#define DM9000_outb(d,r) ( *(volatile u8 *)r = d )
#define DM9000_outw(d,r) ( *(volatile u16 *)r = d )
#define DM9000_outl(d,r) ( *(volatile u32 *)r = d )
#define DM9000_inb(r) (*(volatile u8 *)r)
#define DM9000_inw(r) (*(volatile u16 *)r)
#define DM9000_inl(r) (*(volatile u32 *)r)

#ifdef CONFIG_DM9000_DEBUG
static void
dump_regs(void)
{
	DM9000_DBG("\n");
	DM9000_DBG("NCR   (0x00): %02x\n", DM9000_ior(0));
	DM9000_DBG("NSR   (0x01): %02x\n", DM9000_ior(1));
	DM9000_DBG("TCR   (0x02): %02x\n", DM9000_ior(2));
	DM9000_DBG("TSRI  (0x03): %02x\n", DM9000_ior(3));
	DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
	DM9000_DBG("RCR   (0x05): %02x\n", DM9000_ior(5));
	DM9000_DBG("RSR   (0x06): %02x\n", DM9000_ior(6));
	DM9000_DBG("ISR   (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
	DM9000_DBG("\n");
}
#endif

static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
{
	int i;
	for (i = 0; i < count; i++)
		DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
}

static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
{
	int i;
	u32 tmplen = (count + 1) / 2;

	for (i = 0; i < tmplen; i++)
		DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
}
static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
{
	int i;
	u32 tmplen = (count + 3) / 4;

	for (i = 0; i < tmplen; i++)
		DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
}

static void dm9000_inblk_8bit(void *data_ptr, int count)
{
	int i;
	for (i = 0; i < count; i++)
		((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
}

static void dm9000_inblk_16bit(void *data_ptr, int count)
{
	int i;
	u32 tmplen = (count + 1) / 2;

	for (i = 0; i < tmplen; i++)
		((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
}
static void dm9000_inblk_32bit(void *data_ptr, int count)
{
	int i;
	u32 tmplen = (count + 3) / 4;

	for (i = 0; i < tmplen; i++)
		((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
}

static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
{
	u32 tmpdata;

	DM9000_outb(DM9000_MRCMD, DM9000_IO);

	tmpdata = DM9000_inl(DM9000_DATA);
	*RxStatus = __le16_to_cpu(tmpdata);
	*RxLen = __le16_to_cpu(tmpdata >> 16);
}

static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
{
	DM9000_outb(DM9000_MRCMD, DM9000_IO);

	*RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA));
	*RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA));
}

static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
{
	DM9000_outb(DM9000_MRCMD, DM9000_IO);

	*RxStatus =
	    __le16_to_cpu(DM9000_inb(DM9000_DATA) +
			  (DM9000_inb(DM9000_DATA) << 8));
	*RxLen =
	    __le16_to_cpu(DM9000_inb(DM9000_DATA) +
			  (DM9000_inb(DM9000_DATA) << 8));
}

/*
  Search DM9000 board, allocate space and register it
*/
int
dm9000_probe(void)
{
	u32 id_val;
	id_val = DM9000_ior(DM9000_VIDL);
	id_val |= DM9000_ior(DM9000_VIDH) << 8;
	id_val |= DM9000_ior(DM9000_PIDL) << 16;
	id_val |= DM9000_ior(DM9000_PIDH) << 24;
	if (id_val == DM9000_ID) {
		printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
		       id_val);
		return 0;
	} else {
		printf("dm9000 not found at 0x%08x id: 0x%08x\n",
		       CONFIG_DM9000_BASE, id_val);
		return -1;
	}
}

/* General Purpose dm9000 reset routine */
static void
dm9000_reset(void)
{
	DM9000_DBG("resetting DM9000\n");

	/* Reset DM9000,
	   see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */

	/* DEBUG: Make all GPIO0 outputs, all others inputs */
	DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
	/* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
	DM9000_iow(DM9000_GPR, 0);
	/* Step 2: Software reset */
	DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));

	do {
		DM9000_DBG("resetting the DM9000, 1st reset\n");
		udelay(25); /* Wait at least 20 us */
	} while (DM9000_ior(DM9000_NCR) & 1);

	DM9000_iow(DM9000_NCR, 0);
	DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */

	do {
		DM9000_DBG("resetting the DM9000, 2nd reset\n");
		udelay(25); /* Wait at least 20 us */
	} while (DM9000_ior(DM9000_NCR) & 1);

	/* Check whether the ethernet controller is present */
	if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
	    (DM9000_ior(DM9000_PIDH) != 0x90))
		printf("ERROR: resetting DM9000 -> not responding\n");
}

/* Initilize dm9000 board
*/
int
eth_init(bd_t * bd)
{
	int i, oft, lnk;
	u8 io_mode;
	struct board_info *db = &dm9000_info;

	DM9000_DBG("eth_init()\n");

	/* RESET device */
	dm9000_reset();

	if (dm9000_probe() < 0)
		return -1;

	/* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
	io_mode = DM9000_ior(DM9000_ISR) >> 6;

	switch (io_mode) {
	case 0x0:  /* 16-bit mode */
		printf("DM9000: running in 16 bit mode\n");
		db->outblk    = dm9000_outblk_16bit;
		db->inblk     = dm9000_inblk_16bit;
		db->rx_status = dm9000_rx_status_16bit;
		break;
	case 0x01:  /* 32-bit mode */
		printf("DM9000: running in 32 bit mode\n");
		db->outblk    = dm9000_outblk_32bit;
		db->inblk     = dm9000_inblk_32bit;
		db->rx_status = dm9000_rx_status_32bit;
		break;
	case 0x02: /* 8 bit mode */
		printf("DM9000: running in 8 bit mode\n");
		db->outblk    = dm9000_outblk_8bit;
		db->inblk     = dm9000_inblk_8bit;
		db->rx_status = dm9000_rx_status_8bit;
		break;
	default:
		/* Assume 8 bit mode, will probably not work anyway */
		printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
		db->outblk    = dm9000_outblk_8bit;
		db->inblk     = dm9000_inblk_8bit;
		db->rx_status = dm9000_rx_status_8bit;
		break;
	}

	/* Program operating register, only internal phy supported */
	DM9000_iow(DM9000_NCR, 0x0);
	/* TX Polling clear */
	DM9000_iow(DM9000_TCR, 0);
	/* Less 3Kb, 200us */
	DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
	/* Flow Control : High/Low Water */
	DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
	/* SH FIXME: This looks strange! Flow Control */
	DM9000_iow(DM9000_FCR, 0x0);
	/* Special Mode */
	DM9000_iow(DM9000_SMCR, 0);
	/* clear TX status */
	DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
	/* Clear interrupt status */
	DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);

	/* Set Node address */
#if !defined(CONFIG_AT91SAM9261EK)
	for (i = 0; i < 6; i++)
		((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
#endif

	if (is_zero_ether_addr(bd->bi_enetaddr) ||
	    is_multicast_ether_addr(bd->bi_enetaddr)) {
		/* try reading from environment */
		u8 i;
		char *s, *e;
		s = getenv ("ethaddr");
		for (i = 0; i < 6; ++i) {
			bd->bi_enetaddr[i] = s ?
				simple_strtoul (s, &e, 16) : 0;
			if (s)
				s = (*e) ? e + 1 : e;
		}
	}

	printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
	       bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
	       bd->bi_enetaddr[4], bd->bi_enetaddr[5]);

	/* fill device MAC address registers */
	for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
		DM9000_iow(oft, bd->bi_enetaddr[i]);
	for (i = 0, oft = 0x16; i < 8; i++, oft++)
		DM9000_iow(oft, 0xff);

	/* read back mac, just to be sure */
	for (i = 0, oft = 0x10; i < 6; i++, oft++)
		DM9000_DBG("%02x:", DM9000_ior(oft));
	DM9000_DBG("\n");

	/* Activate DM9000 */
	/* RX enable */
	DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
	/* Enable TX/RX interrupt mask */
	DM9000_iow(DM9000_IMR, IMR_PAR);

	i = 0;
	while (!(phy_read(1) & 0x20)) {	/* autonegation complete bit */
		udelay(1000);
		i++;
		if (i == 10000) {
			printf("could not establish link\n");
			return 0;
		}
	}

	/* see what we've got */
	lnk = phy_read(17) >> 12;
	printf("operating at ");
	switch (lnk) {
	case 1:
		printf("10M half duplex ");
		break;
	case 2:
		printf("10M full duplex ");
		break;
	case 4:
		printf("100M half duplex ");
		break;
	case 8:
		printf("100M full duplex ");
		break;
	default:
		printf("unknown: %d ", lnk);
		break;
	}
	printf("mode\n");
	return 0;
}

/*
  Hardware start transmission.
  Send a packet to media from the upper layer.
*/
int
eth_send(volatile void *packet, int length)
{
	int tmo;
	struct board_info *db = &dm9000_info;

	DM9000_DMP_PACKET("eth_send", packet, length);

	DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */

	/* Move data to DM9000 TX RAM */
	DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */

	/* push the data to the TX-fifo */
	(db->outblk)(packet, length);

	/* Set TX length to DM9000 */
	DM9000_iow(DM9000_TXPLL, length & 0xff);
	DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);

	/* Issue TX polling command */
	DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */

	/* wait for end of transmission */
	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
	while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
		!(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
		if (get_timer(0) >= tmo) {
			printf("transmission timeout\n");
			break;
		}
	}
	DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */

	DM9000_DBG("transmit done\n\n");
	return 0;
}

/*
  Stop the interface.
  The interface is stopped when it is brought.
*/
void
eth_halt(void)
{
	DM9000_DBG("eth_halt\n");

	/* RESET devie */
	phy_write(0, 0x8000);	/* PHY RESET */
	DM9000_iow(DM9000_GPR, 0x01);	/* Power-Down PHY */
	DM9000_iow(DM9000_IMR, 0x80);	/* Disable all interrupt */
	DM9000_iow(DM9000_RCR, 0x00);	/* Disable RX */
}

/*
  Received a packet and pass to upper layer
*/
int
eth_rx(void)
{
	u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
	u16 RxStatus, RxLen = 0;
	struct board_info *db = &dm9000_info;

	/* Check packet ready or not, we must check
	   the ISR status first for DM9000A */
	if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
		return 0;

	DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */

	/* There is _at least_ 1 package in the fifo, read them all */
	for (;;) {
		DM9000_ior(DM9000_MRCMDX);	/* Dummy read */

		/* Get most updated data,
		   only look at bits 0:1, See application notes DM9000 */
		rxbyte = DM9000_inb(DM9000_DATA) & 0x03;

		/* Status check: this byte must be 0 or 1 */
		if (rxbyte > DM9000_PKT_RDY) {
			DM9000_iow(DM9000_RCR, 0x00);	/* Stop Device */
			DM9000_iow(DM9000_ISR, 0x80);	/* Stop INT request */
			printf("DM9000 error: status check fail: 0x%x\n",
				rxbyte);
			return 0;
		}

		if (rxbyte != DM9000_PKT_RDY)
			return 0; /* No packet received, ignore */

		DM9000_DBG("receiving packet\n");

		/* A packet ready now  & Get status/length */
		(db->rx_status)(&RxStatus, &RxLen);

		DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);

		/* Move data from DM9000 */
		/* Read received packet from RX SRAM */
		(db->inblk)(rdptr, RxLen);

		if ((RxStatus & 0xbf00) || (RxLen < 0x40)
			|| (RxLen > DM9000_PKT_MAX)) {
			if (RxStatus & 0x100) {
				printf("rx fifo error\n");
			}
			if (RxStatus & 0x200) {
				printf("rx crc error\n");
			}
			if (RxStatus & 0x8000) {
				printf("rx length error\n");
			}
			if (RxLen > DM9000_PKT_MAX) {
				printf("rx length too big\n");
				dm9000_reset();
			}
		} else {
			DM9000_DMP_PACKET("eth_rx", rdptr, RxLen);

			DM9000_DBG("passing packet to upper layer\n");
			NetReceive(NetRxPackets[0], RxLen);
		}
	}
	return 0;
}

/*
  Read a word data from SROM
*/
u16
read_srom_word(int offset)
{
	DM9000_iow(DM9000_EPAR, offset);
	DM9000_iow(DM9000_EPCR, 0x4);
	udelay(8000);
	DM9000_iow(DM9000_EPCR, 0x0);
	return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
}

void
write_srom_word(int offset, u16 val)
{
	DM9000_iow(DM9000_EPAR, offset);
	DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
	DM9000_iow(DM9000_EPDRL, (val & 0xff));
	DM9000_iow(DM9000_EPCR, 0x12);
	udelay(8000);
	DM9000_iow(DM9000_EPCR, 0);
}


/*
   Read a byte from I/O port
*/
static u8
DM9000_ior(int reg)
{
	DM9000_outb(reg, DM9000_IO);
	return DM9000_inb(DM9000_DATA);
}

/*
   Write a byte to I/O port
*/
static void
DM9000_iow(int reg, u8 value)
{
	DM9000_outb(reg, DM9000_IO);
	DM9000_outb(value, DM9000_DATA);
}

/*
   Read a word from phyxcer
*/
static u16
phy_read(int reg)
{
	u16 val;

	/* Fill the phyxcer register into REG_0C */
	DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
	DM9000_iow(DM9000_EPCR, 0xc);	/* Issue phyxcer read command */
	udelay(100);			/* Wait read complete */
	DM9000_iow(DM9000_EPCR, 0x0);	/* Clear phyxcer read command */
	val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);

	/* The read data keeps on REG_0D & REG_0E */
	DM9000_DBG("phy_read(0x%x): 0x%x\n", reg, val);
	return val;
}

/*
   Write a word to phyxcer
*/
static void
phy_write(int reg, u16 value)
{

	/* Fill the phyxcer register into REG_0C */
	DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);

	/* Fill the written data into REG_0D & REG_0E */
	DM9000_iow(DM9000_EPDRL, (value & 0xff));
	DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
	DM9000_iow(DM9000_EPCR, 0xa);	/* Issue phyxcer write command */
	udelay(500);			/* Wait write complete */
	DM9000_iow(DM9000_EPCR, 0x0);	/* Clear phyxcer write command */
	DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value);
}
Commit	Line	Data
281e00a3 WD	1	/*
	2	dm9000.c: Version 1.2 12/15/2003
	3
	4	A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
	5	Copyright (C) 1997 Sten Wang
	6
	7	This program is free software; you can redistribute it and/or
	8	modify it under the terms of the GNU General Public License
	9	as published by the Free Software Foundation; either version 2
	10	of the License, or (at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	(C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
	18
	19	V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
53677ef1 WD	20	06/22/2001 Support DM9801 progrmming
	21	E3: R25 = ((R24 + NF) & 0x00ff) \| 0xf000
	22	E4: R25 = ((R24 + NF) & 0x00ff) \| 0xc200
	23	R17 = (R17 & 0xfff0) \| NF + 3
	24	E5: R25 = ((R24 + NF - 3) & 0x00ff) \| 0xc200
	25	R17 = (R17 & 0xfff0) \| NF
	26
	27	v1.00 modify by simon 2001.9.5
281e00a3 WD	28	change for kernel 2.4.x
281e00a3 WD	29
53677ef1	30	v1.1 11/09/2001 fix force mode bug
281e00a3 WD	31
	32	v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
	33	Fixed phy reset.
	34	Added tx/rx 32 bit mode.
	35	Cleaned up for kernel merge.
	36
	37	--------------------------------------
	38
a101361b RB	39	12/15/2003 Initial port to u-boot by
	40	Sascha Hauer <saschahauer@web.de>
	41
	42	06/03/2008 Remy Bohmer <linux@bohmer.net>
850ba755 RB	43	- Fixed the driver to work with DM9000A.
	44	(check on ISR receive status bit before reading the
	45	FIFO as described in DM9000 programming guide and
	46	application notes)
a101361b	47	- Added autodetect of databus width.
134e2662	48	- Made debug code compile again.
acba3184 RB	49	- Adapt eth_send such that it matches the DM9000*
	50	application notes. Needed to make it work properly
	51	for DM9000A.
fbcb7ece RB	52	- Adapted reset procedure to match DM9000 application
fbcb7ece RB	53	notes (i.e. double reset)
98291e2e	54	- some minor code cleanups
a101361b RB	55	These changes are tested with DM9000{A,EP,E} together
a101361b RB	56	with a 200MHz Atmel AT91SAM92161 core
281e00a3	57
d26b739a	58	TODO: external MII is not functional, only internal at the moment.
281e00a3 WD	59	*/
	60
	61	#include <common.h>
	62	#include <command.h>
	63	#include <net.h>
	64	#include <asm/io.h>
	65
281e00a3 WD	66	#include "dm9000x.h"
	67
	68	/* Board/System/Debug information/definition ---------------- */
	69
281e00a3 WD	70	/* #define CONFIG_DM9000_DEBUG */
	71
	72	#ifdef CONFIG_DM9000_DEBUG
134e2662 RB	73	#define DM9000_DBG(fmt,args...) printf(fmt, ##args)
	74	#define DM9000_DMP_PACKET(func,packet,length) \
	75	do { \
	76	int i; \
	77	printf(func ": length: %d\n", length); \
	78	for (i = 0; i < length; i++) { \
	79	if (i % 8 == 0) \
	80	printf("\n%s: %02x: ", func, i); \
	81	printf("%02x ", ((unsigned char *) packet)[i]); \
	82	} printf("\n"); \
	83	} while(0)
	84	#else
281e00a3	85	#define DM9000_DBG(fmt,args...)
134e2662 RB	86	#define DM9000_DMP_PACKET(func,packet,length)
	87	#endif
	88
281e00a3 WD	89	/* Structure/enum declaration ------------------------------- */
	90	typedef struct board_info {
	91	u32 runt_length_counter; /* counter: RX length < 64byte */
	92	u32 long_length_counter; /* counter: RX length > 1514byte */
	93	u32 reset_counter; /* counter: RESET */
	94	u32 reset_tx_timeout; /* RESET caused by TX Timeout */
	95	u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
	96	u16 tx_pkt_cnt;
	97	u16 queue_start_addr;
	98	u16 dbug_cnt;
	99	u8 phy_addr;
	100	u8 device_wait_reset; /* device state */
281e00a3	101	unsigned char srom[128];
0e38c938	102	void (outblk)(volatile void data_ptr, int count);
a101361b RB	103	void (inblk)(void data_ptr, int count);
a101361b RB	104	void (rx_status)(u16 RxStatus, u16 *RxLen);
98291e2e	105	} board_info_t;
a101361b	106	static board_info_t dm9000_info;
281e00a3	107
281e00a3 WD	108	/* function declaration ------------------------------------- */
	109	int eth_init(bd_t * bd);
	110	int eth_send(volatile void *, int);
	111	int eth_rx(void);
	112	void eth_halt(void);
	113	static int dm9000_probe(void);
	114	static u16 phy_read(int);
	115	static void phy_write(int, u16);
5e5803e1	116	u16 read_srom_word(int);
281e00a3 WD	117	static u8 DM9000_ior(int);
	118	static void DM9000_iow(int reg, u8 value);
	119
	120	/* DM9000 network board routine ---------------------------- */
	121
	122	#define DM9000_outb(d,r) ( (volatile u8 )r = d )
	123	#define DM9000_outw(d,r) ( (volatile u16 )r = d )
	124	#define DM9000_outl(d,r) ( (volatile u32 )r = d )
	125	#define DM9000_inb(r) ((volatile u8 )r)
	126	#define DM9000_inw(r) ((volatile u16 )r)
	127	#define DM9000_inl(r) ((volatile u32 )r)
	128
	129	#ifdef CONFIG_DM9000_DEBUG
	130	static void
	131	dump_regs(void)
	132	{
	133	DM9000_DBG("\n");
	134	DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
	135	DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
	136	DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
	137	DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
	138	DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
	139	DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
	140	DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
134e2662	141	DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
281e00a3 WD	142	DM9000_DBG("\n");
281e00a3 WD	143	}
a101361b RB	144	#endif
a101361b RB	145
0e38c938	146	static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
a101361b RB	147	{
	148	int i;
	149	for (i = 0; i < count; i++)
	150	DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
	151	}
	152
0e38c938	153	static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
a101361b RB	154	{
	155	int i;
	156	u32 tmplen = (count + 1) / 2;
	157
	158	for (i = 0; i < tmplen; i++)
	159	DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
	160	}
0e38c938	161	static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
a101361b RB	162	{
	163	int i;
	164	u32 tmplen = (count + 3) / 4;
	165
	166	for (i = 0; i < tmplen; i++)
	167	DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
	168	}
	169
	170	static void dm9000_inblk_8bit(void *data_ptr, int count)
	171	{
	172	int i;
	173	for (i = 0; i < count; i++)
	174	((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
	175	}
	176
	177	static void dm9000_inblk_16bit(void *data_ptr, int count)
	178	{
	179	int i;
	180	u32 tmplen = (count + 1) / 2;
	181
	182	for (i = 0; i < tmplen; i++)
	183	((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
	184	}
	185	static void dm9000_inblk_32bit(void *data_ptr, int count)
	186	{
	187	int i;
	188	u32 tmplen = (count + 3) / 4;
	189
	190	for (i = 0; i < tmplen; i++)
	191	((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
	192	}
	193
	194	static void dm9000_rx_status_32bit(u16 RxStatus, u16 RxLen)
	195	{
d6ee5fa4	196	u32 tmpdata;
a101361b RB	197
	198	DM9000_outb(DM9000_MRCMD, DM9000_IO);
	199
d6ee5fa4	200	tmpdata = DM9000_inl(DM9000_DATA);
943b825b TL	201	*RxStatus = __le16_to_cpu(tmpdata);
943b825b TL	202	*RxLen = __le16_to_cpu(tmpdata >> 16);
a101361b RB	203	}
	204
	205	static void dm9000_rx_status_16bit(u16 RxStatus, u16 RxLen)
	206	{
	207	DM9000_outb(DM9000_MRCMD, DM9000_IO);
	208
943b825b TL	209	*RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA));
943b825b TL	210	*RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA));
a101361b RB	211	}
	212
	213	static void dm9000_rx_status_8bit(u16 RxStatus, u16 RxLen)
	214	{
	215	DM9000_outb(DM9000_MRCMD, DM9000_IO);
	216
943b825b TL	217	*RxStatus =
	218	__le16_to_cpu(DM9000_inb(DM9000_DATA) +
	219	(DM9000_inb(DM9000_DATA) << 8));
	220	*RxLen =
	221	__le16_to_cpu(DM9000_inb(DM9000_DATA) +
	222	(DM9000_inb(DM9000_DATA) << 8));
a101361b	223	}
281e00a3 WD	224
	225	/*
	226	Search DM9000 board, allocate space and register it
	227	*/
	228	int
	229	dm9000_probe(void)
	230	{
	231	u32 id_val;
	232	id_val = DM9000_ior(DM9000_VIDL);
	233	id_val \|= DM9000_ior(DM9000_VIDH) << 8;
	234	id_val \|= DM9000_ior(DM9000_PIDL) << 16;
	235	id_val \|= DM9000_ior(DM9000_PIDH) << 24;
	236	if (id_val == DM9000_ID) {
	237	printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
	238	id_val);
	239	return 0;
	240	} else {
	241	printf("dm9000 not found at 0x%08x id: 0x%08x\n",
	242	CONFIG_DM9000_BASE, id_val);
	243	return -1;
	244	}
	245	}
	246
281e00a3 WD	247	/* General Purpose dm9000 reset routine */
	248	static void
	249	dm9000_reset(void)
	250	{
fbcb7ece RB	251	DM9000_DBG("resetting DM9000\n");
	252
	253	/* Reset DM9000,
	254	see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
	255
d26b739a AD	256	/* DEBUG: Make all GPIO0 outputs, all others inputs */
d26b739a AD	257	DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
fbcb7ece RB	258	/* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
	259	DM9000_iow(DM9000_GPR, 0);
	260	/* Step 2: Software reset */
d26b739a	261	DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC \| NCR_RST));
fbcb7ece RB	262
	263	do {
	264	DM9000_DBG("resetting the DM9000, 1st reset\n");
	265	udelay(25); /* Wait at least 20 us */
	266	} while (DM9000_ior(DM9000_NCR) & 1);
	267
	268	DM9000_iow(DM9000_NCR, 0);
d26b739a	269	DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC \| NCR_RST)); /* Issue a second reset */
fbcb7ece RB	270
	271	do {
	272	DM9000_DBG("resetting the DM9000, 2nd reset\n");
	273	udelay(25); /* Wait at least 20 us */
	274	} while (DM9000_ior(DM9000_NCR) & 1);
	275
	276	/* Check whether the ethernet controller is present */
	277	if ((DM9000_ior(DM9000_PIDL) != 0x0) \|\|
	278	(DM9000_ior(DM9000_PIDH) != 0x90))
	279	printf("ERROR: resetting DM9000 -> not responding\n");
281e00a3 WD	280	}
	281
	282	/* Initilize dm9000 board
	283	*/
	284	int
	285	eth_init(bd_t * bd)
	286	{
	287	int i, oft, lnk;
a101361b RB	288	u8 io_mode;
	289	struct board_info *db = &dm9000_info;
	290
281e00a3 WD	291	DM9000_DBG("eth_init()\n");
	292
	293	/* RESET device */
	294	dm9000_reset();
d26b739a AD	295
	296	if (dm9000_probe() < 0)
	297	return -1;
281e00a3	298
a101361b RB	299	/* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
	300	io_mode = DM9000_ior(DM9000_ISR) >> 6;
	301
	302	switch (io_mode) {
	303	case 0x0: /* 16-bit mode */
	304	printf("DM9000: running in 16 bit mode\n");
	305	db->outblk = dm9000_outblk_16bit;
	306	db->inblk = dm9000_inblk_16bit;
	307	db->rx_status = dm9000_rx_status_16bit;
	308	break;
	309	case 0x01: /* 32-bit mode */
	310	printf("DM9000: running in 32 bit mode\n");
	311	db->outblk = dm9000_outblk_32bit;
	312	db->inblk = dm9000_inblk_32bit;
	313	db->rx_status = dm9000_rx_status_32bit;
	314	break;
	315	case 0x02: /* 8 bit mode */
	316	printf("DM9000: running in 8 bit mode\n");
	317	db->outblk = dm9000_outblk_8bit;
	318	db->inblk = dm9000_inblk_8bit;
	319	db->rx_status = dm9000_rx_status_8bit;
	320	break;
	321	default:
	322	/* Assume 8 bit mode, will probably not work anyway */
	323	printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
	324	db->outblk = dm9000_outblk_8bit;
	325	db->inblk = dm9000_inblk_8bit;
	326	db->rx_status = dm9000_rx_status_8bit;
	327	break;
	328	}
	329
d26b739a	330	/* Program operating register, only internal phy supported */
98291e2e RB	331	DM9000_iow(DM9000_NCR, 0x0);
	332	/* TX Polling clear */
	333	DM9000_iow(DM9000_TCR, 0);
	334	/* Less 3Kb, 200us */
d26b739a	335	DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) \| BPTR_JPT_600US);
98291e2e RB	336	/* Flow Control : High/Low Water */
	337	DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) \| FCTR_LWOT(8));
	338	/* SH FIXME: This looks strange! Flow Control */
	339	DM9000_iow(DM9000_FCR, 0x0);
	340	/* Special Mode */
	341	DM9000_iow(DM9000_SMCR, 0);
	342	/* clear TX status */
	343	DM9000_iow(DM9000_NSR, NSR_WAKEST \| NSR_TX2END \| NSR_TX1END);
	344	/* Clear interrupt status */
d26b739a	345	DM9000_iow(DM9000_ISR, ISR_ROOS \| ISR_ROS \| ISR_PTS \| ISR_PRS);
281e00a3 WD	346
281e00a3 WD	347	/* Set Node address */
d26b739a	348	#if !defined(CONFIG_AT91SAM9261EK)
281e00a3 WD	349	for (i = 0; i < 6; i++)
281e00a3 WD	350	((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
d99a8ff6	351	#endif
50cca8b9	352
5f470948 SB	353	if (is_zero_ether_addr(bd->bi_enetaddr) \|\|
5f470948 SB	354	is_multicast_ether_addr(bd->bi_enetaddr)) {
50cca8b9 MR	355	/* try reading from environment */
	356	u8 i;
	357	char s, e;
	358	s = getenv ("ethaddr");
	359	for (i = 0; i < 6; ++i) {
	360	bd->bi_enetaddr[i] = s ?
	361	simple_strtoul (s, &e, 16) : 0;
	362	if (s)
	363	s = (*e) ? e + 1 : e;
	364	}
	365	}
	366
281e00a3 WD	367	printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", bd->bi_enetaddr[0],
	368	bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
	369	bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
d26b739a AD	370
	371	/* fill device MAC address registers */
	372	for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
281e00a3 WD	373	DM9000_iow(oft, bd->bi_enetaddr[i]);
	374	for (i = 0, oft = 0x16; i < 8; i++, oft++)
	375	DM9000_iow(oft, 0xff);
	376
	377	/* read back mac, just to be sure */
	378	for (i = 0, oft = 0x10; i < 6; i++, oft++)
	379	DM9000_DBG("%02x:", DM9000_ior(oft));
	380	DM9000_DBG("\n");
	381
	382	/* Activate DM9000 */
98291e2e RB	383	/* RX enable */
	384	DM9000_iow(DM9000_RCR, RCR_DIS_LONG \| RCR_DIS_CRC \| RCR_RXEN);
	385	/* Enable TX/RX interrupt mask */
	386	DM9000_iow(DM9000_IMR, IMR_PAR);
	387
281e00a3 WD	388	i = 0;
	389	while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
	390	udelay(1000);
	391	i++;
	392	if (i == 10000) {
	393	printf("could not establish link\n");
	394	return 0;
	395	}
	396	}
	397
	398	/* see what we've got */
	399	lnk = phy_read(17) >> 12;
	400	printf("operating at ");
	401	switch (lnk) {
	402	case 1:
	403	printf("10M half duplex ");
	404	break;
	405	case 2:
	406	printf("10M full duplex ");
	407	break;
	408	case 4:
	409	printf("100M half duplex ");
	410	break;
	411	case 8:
	412	printf("100M full duplex ");
	413	break;
	414	default:
	415	printf("unknown: %d ", lnk);
	416	break;
	417	}
	418	printf("mode\n");
	419	return 0;
	420	}
	421
	422	/*
	423	Hardware start transmission.
	424	Send a packet to media from the upper layer.
	425	*/
	426	int
	427	eth_send(volatile void *packet, int length)
	428	{
281e00a3	429	int tmo;
a101361b RB	430	struct board_info *db = &dm9000_info;
a101361b RB	431
134e2662	432	DM9000_DMP_PACKET("eth_send", packet, length);
281e00a3	433
acba3184 RB	434	DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
acba3184 RB	435
281e00a3	436	/* Move data to DM9000 TX RAM */
acba3184	437	DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
281e00a3	438
a101361b	439	/* push the data to the TX-fifo */
0e38c938	440	(db->outblk)(packet, length);
281e00a3 WD	441
	442	/* Set TX length to DM9000 */
	443	DM9000_iow(DM9000_TXPLL, length & 0xff);
	444	DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
	445
	446	/* Issue TX polling command */
acba3184	447	DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
281e00a3 WD	448
281e00a3 WD	449	/* wait for end of transmission */
6d0f6bcf	450	tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
acba3184 RB	451	while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END \| NSR_TX2END)) \|\|
acba3184 RB	452	!(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
281e00a3 WD	453	if (get_timer(0) >= tmo) {
	454	printf("transmission timeout\n");
	455	break;
	456	}
	457	}
acba3184 RB	458	DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
acba3184 RB	459
281e00a3 WD	460	DM9000_DBG("transmit done\n\n");
	461	return 0;
	462	}
	463
	464	/*
	465	Stop the interface.
	466	The interface is stopped when it is brought.
	467	*/
	468	void
	469	eth_halt(void)
	470	{
	471	DM9000_DBG("eth_halt\n");
	472
	473	/* RESET devie */
	474	phy_write(0, 0x8000); /* PHY RESET */
	475	DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
	476	DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
	477	DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
	478	}
	479
	480	/*
	481	Received a packet and pass to upper layer
	482	*/
	483	int
	484	eth_rx(void)
	485	{
	486	u8 rxbyte, rdptr = (u8 ) NetRxPackets[0];
	487	u16 RxStatus, RxLen = 0;
a101361b	488	struct board_info *db = &dm9000_info;
281e00a3	489
850ba755 RB	490	/* Check packet ready or not, we must check
	491	the ISR status first for DM9000A */
	492	if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
281e00a3 WD	493	return 0;
281e00a3 WD	494
850ba755	495	DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
281e00a3	496
850ba755 RB	497	/* There is _at least_ 1 package in the fifo, read them all */
	498	for (;;) {
	499	DM9000_ior(DM9000_MRCMDX); /* Dummy read */
281e00a3	500
0e38c938 RB	501	/* Get most updated data,
	502	only look at bits 0:1, See application notes DM9000 */
	503	rxbyte = DM9000_inb(DM9000_DATA) & 0x03;
281e00a3	504
850ba755 RB	505	/* Status check: this byte must be 0 or 1 */
	506	if (rxbyte > DM9000_PKT_RDY) {
	507	DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
	508	DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
	509	printf("DM9000 error: status check fail: 0x%x\n",
	510	rxbyte);
	511	return 0;
	512	}
281e00a3	513
850ba755 RB	514	if (rxbyte != DM9000_PKT_RDY)
	515	return 0; /* No packet received, ignore */
	516
	517	DM9000_DBG("receiving packet\n");
	518
	519	/* A packet ready now & Get status/length */
	520	(db->rx_status)(&RxStatus, &RxLen);
	521
	522	DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
	523
	524	/* Move data from DM9000 */
	525	/* Read received packet from RX SRAM */
	526	(db->inblk)(rdptr, RxLen);
	527
	528	if ((RxStatus & 0xbf00) \|\| (RxLen < 0x40)
	529	\|\| (RxLen > DM9000_PKT_MAX)) {
	530	if (RxStatus & 0x100) {
	531	printf("rx fifo error\n");
	532	}
	533	if (RxStatus & 0x200) {
	534	printf("rx crc error\n");
	535	}
	536	if (RxStatus & 0x8000) {
	537	printf("rx length error\n");
	538	}
	539	if (RxLen > DM9000_PKT_MAX) {
	540	printf("rx length too big\n");
	541	dm9000_reset();
	542	}
	543	} else {
	544	DM9000_DMP_PACKET("eth_rx", rdptr, RxLen);
281e00a3	545
850ba755 RB	546	DM9000_DBG("passing packet to upper layer\n");
850ba755 RB	547	NetReceive(NetRxPackets[0], RxLen);
281e00a3	548	}
281e00a3 WD	549	}
	550	return 0;
	551	}
	552
	553	/*
	554	Read a word data from SROM
	555	*/
5e5803e1	556	u16
281e00a3 WD	557	read_srom_word(int offset)
	558	{
	559	DM9000_iow(DM9000_EPAR, offset);
	560	DM9000_iow(DM9000_EPCR, 0x4);
5f470948	561	udelay(8000);
281e00a3 WD	562	DM9000_iow(DM9000_EPCR, 0x0);
	563	return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
	564	}
	565
5e5803e1 SB	566	void
	567	write_srom_word(int offset, u16 val)
	568	{
	569	DM9000_iow(DM9000_EPAR, offset);
	570	DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
	571	DM9000_iow(DM9000_EPDRL, (val & 0xff));
	572	DM9000_iow(DM9000_EPCR, 0x12);
	573	udelay(8000);
	574	DM9000_iow(DM9000_EPCR, 0);
	575	}
	576
	577
281e00a3 WD	578	/*
	579	Read a byte from I/O port
	580	*/
	581	static u8
	582	DM9000_ior(int reg)
	583	{
	584	DM9000_outb(reg, DM9000_IO);
	585	return DM9000_inb(DM9000_DATA);
	586	}
	587
	588	/*
	589	Write a byte to I/O port
	590	*/
	591	static void
	592	DM9000_iow(int reg, u8 value)
	593	{
	594	DM9000_outb(reg, DM9000_IO);
	595	DM9000_outb(value, DM9000_DATA);
	596	}
	597
	598	/*
	599	Read a word from phyxcer
	600	*/
	601	static u16
	602	phy_read(int reg)
	603	{
	604	u16 val;
	605
	606	/* Fill the phyxcer register into REG_0C */
	607	DM9000_iow(DM9000_EPAR, DM9000_PHY \| reg);
	608	DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
98291e2e	609	udelay(100); /* Wait read complete */
281e00a3 WD	610	DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
	611	val = (DM9000_ior(DM9000_EPDRH) << 8) \| DM9000_ior(DM9000_EPDRL);
	612
	613	/* The read data keeps on REG_0D & REG_0E */
134e2662	614	DM9000_DBG("phy_read(0x%x): 0x%x\n", reg, val);
281e00a3 WD	615	return val;
	616	}
	617
	618	/*
	619	Write a word to phyxcer
	620	*/
	621	static void
	622	phy_write(int reg, u16 value)
	623	{
	624
	625	/* Fill the phyxcer register into REG_0C */
	626	DM9000_iow(DM9000_EPAR, DM9000_PHY \| reg);
	627
	628	/* Fill the written data into REG_0D & REG_0E */
	629	DM9000_iow(DM9000_EPDRL, (value & 0xff));
	630	DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
	631	DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
98291e2e	632	udelay(500); /* Wait write complete */
281e00a3	633	DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
134e2662	634	DM9000_DBG("phy_write(reg:0x%x, value:0x%x)\n", reg, value);
281e00a3	635	}