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1df49e27 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <malloc.h> | |
26 | #include <net.h> | |
10efa024 | 27 | #include <netdev.h> |
1df49e27 WD |
28 | #include <asm/io.h> |
29 | #include <pci.h> | |
63ff004c | 30 | #include <miiphy.h> |
1df49e27 WD |
31 | |
32 | #undef DEBUG | |
33 | ||
1df49e27 WD |
34 | /* Ethernet chip registers. |
35 | */ | |
c570b2fd WD |
36 | #define SCBStatus 0 /* Rx/Command Unit Status *Word* */ |
37 | #define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */ | |
38 | #define SCBCmd 2 /* Rx/Command Unit Command *Word* */ | |
39 | #define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */ | |
40 | #define SCBPointer 4 /* General purpose pointer. */ | |
41 | #define SCBPort 8 /* Misc. commands and operands. */ | |
42 | #define SCBflash 12 /* Flash memory control. */ | |
43 | #define SCBeeprom 14 /* EEPROM memory control. */ | |
44 | #define SCBCtrlMDI 16 /* MDI interface control. */ | |
45 | #define SCBEarlyRx 20 /* Early receive byte count. */ | |
46 | #define SCBGenControl 28 /* 82559 General Control Register */ | |
47 | #define SCBGenStatus 29 /* 82559 General Status register */ | |
1df49e27 WD |
48 | |
49 | /* 82559 SCB status word defnitions | |
50 | */ | |
c570b2fd WD |
51 | #define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */ |
52 | #define SCB_STATUS_FR 0x4000 /* frame received */ | |
53 | #define SCB_STATUS_CNA 0x2000 /* CU left active state */ | |
54 | #define SCB_STATUS_RNR 0x1000 /* receiver left ready state */ | |
55 | #define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */ | |
56 | #define SCB_STATUS_SWI 0x0400 /* software generated interrupt */ | |
57 | #define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */ | |
1df49e27 | 58 | |
c570b2fd | 59 | #define SCB_INTACK_MASK 0xFD00 /* all the above */ |
1df49e27 | 60 | |
c570b2fd WD |
61 | #define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA) |
62 | #define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR) | |
1df49e27 WD |
63 | |
64 | /* System control block commands | |
65 | */ | |
66 | /* CU Commands */ | |
c570b2fd WD |
67 | #define CU_NOP 0x0000 |
68 | #define CU_START 0x0010 | |
69 | #define CU_RESUME 0x0020 | |
70 | #define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */ | |
71 | #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */ | |
72 | #define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */ | |
73 | #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */ | |
1df49e27 WD |
74 | |
75 | /* RUC Commands */ | |
c570b2fd WD |
76 | #define RUC_NOP 0x0000 |
77 | #define RUC_START 0x0001 | |
78 | #define RUC_RESUME 0x0002 | |
79 | #define RUC_ABORT 0x0004 | |
80 | #define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */ | |
81 | #define RUC_RESUMENR 0x0007 | |
82 | ||
83 | #define CU_CMD_MASK 0x00f0 | |
84 | #define RU_CMD_MASK 0x0007 | |
85 | ||
86 | #define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */ | |
87 | #define SCB_SWI 0x0200 /* 1 - cause device to interrupt */ | |
88 | ||
89 | #define CU_STATUS_MASK 0x00C0 | |
90 | #define RU_STATUS_MASK 0x003C | |
91 | ||
92 | #define RU_STATUS_IDLE (0<<2) | |
93 | #define RU_STATUS_SUS (1<<2) | |
94 | #define RU_STATUS_NORES (2<<2) | |
95 | #define RU_STATUS_READY (4<<2) | |
96 | #define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2)) | |
1df49e27 WD |
97 | #define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2)) |
98 | #define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2)) | |
99 | ||
100 | /* 82559 Port interface commands. | |
101 | */ | |
102 | #define I82559_RESET 0x00000000 /* Software reset */ | |
103 | #define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */ | |
104 | #define I82559_SELECTIVE_RESET 0x00000002 | |
105 | #define I82559_DUMP 0x00000003 | |
106 | #define I82559_DUMP_WAKEUP 0x00000007 | |
107 | ||
108 | /* 82559 Eeprom interface. | |
109 | */ | |
110 | #define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ | |
111 | #define EE_CS 0x02 /* EEPROM chip select. */ | |
112 | #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ | |
113 | #define EE_WRITE_0 0x01 | |
114 | #define EE_WRITE_1 0x05 | |
115 | #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ | |
116 | #define EE_ENB (0x4800 | EE_CS) | |
117 | #define EE_CMD_BITS 3 | |
118 | #define EE_DATA_BITS 16 | |
119 | ||
120 | /* The EEPROM commands include the alway-set leading bit. | |
121 | */ | |
122 | #define EE_EWENB_CMD (4 << addr_len) | |
123 | #define EE_WRITE_CMD (5 << addr_len) | |
124 | #define EE_READ_CMD (6 << addr_len) | |
125 | #define EE_ERASE_CMD (7 << addr_len) | |
126 | ||
127 | /* Receive frame descriptors. | |
128 | */ | |
129 | struct RxFD { | |
130 | volatile u16 status; | |
131 | volatile u16 control; | |
132 | volatile u32 link; /* struct RxFD * */ | |
133 | volatile u32 rx_buf_addr; /* void * */ | |
134 | volatile u32 count; | |
135 | ||
136 | volatile u8 data[PKTSIZE_ALIGN]; | |
137 | }; | |
138 | ||
139 | #define RFD_STATUS_C 0x8000 /* completion of received frame */ | |
c570b2fd WD |
140 | #define RFD_STATUS_OK 0x2000 /* frame received with no errors */ |
141 | ||
142 | #define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */ | |
143 | #define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */ | |
144 | #define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */ | |
145 | #define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */ | |
146 | ||
147 | #define RFD_COUNT_MASK 0x3fff | |
148 | #define RFD_COUNT_F 0x4000 | |
149 | #define RFD_COUNT_EOF 0x8000 | |
150 | ||
151 | #define RFD_RX_CRC 0x0800 /* crc error */ | |
152 | #define RFD_RX_ALIGNMENT 0x0400 /* alignment error */ | |
153 | #define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */ | |
154 | #define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */ | |
155 | #define RFD_RX_SHORT 0x0080 /* short frame error */ | |
156 | #define RFD_RX_LENGTH 0x0020 | |
157 | #define RFD_RX_ERROR 0x0010 /* receive error */ | |
158 | #define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */ | |
159 | #define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */ | |
160 | #define RFD_RX_TCO 0x0001 /* TCO indication */ | |
1df49e27 WD |
161 | |
162 | /* Transmit frame descriptors | |
163 | */ | |
164 | struct TxFD { /* Transmit frame descriptor set. */ | |
165 | volatile u16 status; | |
166 | volatile u16 command; | |
167 | volatile u32 link; /* void * */ | |
168 | volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */ | |
169 | volatile s32 count; | |
170 | ||
171 | volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */ | |
172 | volatile s32 tx_buf_size0; /* Length of Tx frame. */ | |
173 | volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */ | |
174 | volatile s32 tx_buf_size1; /* Length of Tx frame. */ | |
175 | }; | |
176 | ||
177 | #define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */ | |
c570b2fd WD |
178 | #define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */ |
179 | #define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */ | |
180 | #define TxCB_CMD_I 0x2000 /* generate interrupt on completion */ | |
181 | #define TxCB_CMD_S 0x4000 /* suspend on completion */ | |
182 | #define TxCB_CMD_EL 0x8000 /* last command block in CBL */ | |
1df49e27 | 183 | |
c570b2fd WD |
184 | #define TxCB_COUNT_MASK 0x3fff |
185 | #define TxCB_COUNT_EOF 0x8000 | |
1df49e27 WD |
186 | |
187 | /* The Speedo3 Rx and Tx frame/buffer descriptors. | |
188 | */ | |
189 | struct descriptor { /* A generic descriptor. */ | |
190 | volatile u16 status; | |
191 | volatile u16 command; | |
c570b2fd | 192 | volatile u32 link; /* struct descriptor * */ |
1df49e27 WD |
193 | |
194 | unsigned char params[0]; | |
195 | }; | |
196 | ||
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_CMD_EL 0x8000 |
198 | #define CONFIG_SYS_CMD_SUSPEND 0x4000 | |
199 | #define CONFIG_SYS_CMD_INT 0x2000 | |
200 | #define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */ | |
201 | #define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */ | |
1df49e27 | 202 | |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_STATUS_C 0x8000 |
204 | #define CONFIG_SYS_STATUS_OK 0x2000 | |
1df49e27 WD |
205 | |
206 | /* Misc. | |
207 | */ | |
c570b2fd WD |
208 | #define NUM_RX_DESC PKTBUFSRX |
209 | #define NUM_TX_DESC 1 /* Number of TX descriptors */ | |
1df49e27 WD |
210 | |
211 | #define TOUT_LOOP 1000000 | |
212 | ||
213 | #define ETH_ALEN 6 | |
214 | ||
c570b2fd WD |
215 | static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */ |
216 | static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */ | |
1df49e27 WD |
217 | static int rx_next; /* RX descriptor ring pointer */ |
218 | static int tx_next; /* TX descriptor ring pointer */ | |
219 | static int tx_threshold; | |
220 | ||
221 | /* | |
222 | * The parameters for a CmdConfigure operation. | |
223 | * There are so many options that it would be difficult to document | |
224 | * each bit. We mostly use the default or recommended settings. | |
225 | */ | |
226 | static const char i82557_config_cmd[] = { | |
227 | 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */ | |
228 | 0, 0x2E, 0, 0x60, 0, | |
229 | 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */ | |
230 | 0x3f, 0x05, | |
231 | }; | |
232 | static const char i82558_config_cmd[] = { | |
233 | 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */ | |
234 | 0, 0x2E, 0, 0x60, 0x08, 0x88, | |
235 | 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */ | |
236 | 0x31, 0x05, | |
237 | }; | |
238 | ||
239 | static void init_rx_ring (struct eth_device *dev); | |
240 | static void purge_tx_ring (struct eth_device *dev); | |
241 | ||
242 | static void read_hw_addr (struct eth_device *dev, bd_t * bis); | |
243 | ||
244 | static int eepro100_init (struct eth_device *dev, bd_t * bis); | |
245 | static int eepro100_send (struct eth_device *dev, volatile void *packet, | |
246 | int length); | |
247 | static int eepro100_recv (struct eth_device *dev); | |
248 | static void eepro100_halt (struct eth_device *dev); | |
249 | ||
3a473b2a | 250 | #if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460) |
42d1f039 WD |
251 | #define bus_to_phys(a) (a) |
252 | #define phys_to_bus(a) (a) | |
253 | #else | |
1df49e27 WD |
254 | #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) |
255 | #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) | |
42d1f039 | 256 | #endif |
1df49e27 WD |
257 | |
258 | static inline int INW (struct eth_device *dev, u_long addr) | |
259 | { | |
260 | return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase)); | |
261 | } | |
262 | ||
263 | static inline void OUTW (struct eth_device *dev, int command, u_long addr) | |
264 | { | |
265 | *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command); | |
266 | } | |
267 | ||
268 | static inline void OUTL (struct eth_device *dev, int command, u_long addr) | |
269 | { | |
270 | *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command); | |
271 | } | |
272 | ||
07d38a17 | 273 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
a912733e WD |
274 | static inline int INL (struct eth_device *dev, u_long addr) |
275 | { | |
276 | return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase)); | |
277 | } | |
278 | ||
63ff004c MB |
279 | static int get_phyreg (struct eth_device *dev, unsigned char addr, |
280 | unsigned char reg, unsigned short *value) | |
a912733e | 281 | { |
63ff004c MB |
282 | int cmd; |
283 | int timeout = 50; | |
a912733e | 284 | |
63ff004c MB |
285 | /* read requested data */ |
286 | cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); | |
a912733e | 287 | OUTL (dev, cmd, SCBCtrlMDI); |
c570b2fd | 288 | |
a912733e | 289 | do { |
63ff004c | 290 | udelay(1000); |
a912733e | 291 | cmd = INL (dev, SCBCtrlMDI); |
63ff004c MB |
292 | } while (!(cmd & (1 << 28)) && (--timeout)); |
293 | ||
294 | if (timeout == 0) | |
295 | return -1; | |
a912733e WD |
296 | |
297 | *value = (unsigned short) (cmd & 0xffff); | |
c570b2fd | 298 | |
a912733e WD |
299 | return 0; |
300 | } | |
301 | ||
63ff004c MB |
302 | static int set_phyreg (struct eth_device *dev, unsigned char addr, |
303 | unsigned char reg, unsigned short value) | |
a912733e | 304 | { |
63ff004c MB |
305 | int cmd; |
306 | int timeout = 50; | |
a912733e | 307 | |
63ff004c MB |
308 | /* write requested data */ |
309 | cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16); | |
a912733e WD |
310 | OUTL (dev, cmd | value, SCBCtrlMDI); |
311 | ||
63ff004c MB |
312 | while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout)) |
313 | udelay(1000); | |
314 | ||
315 | if (timeout == 0) | |
316 | return -1; | |
a912733e WD |
317 | |
318 | return 0; | |
319 | } | |
a912733e | 320 | |
63ff004c MB |
321 | /* Check if given phyaddr is valid, i.e. there is a PHY connected. |
322 | * Do this by checking model value field from ID2 register. | |
323 | */ | |
324 | static struct eth_device* verify_phyaddr (char *devname, unsigned char addr) | |
325 | { | |
326 | struct eth_device *dev; | |
327 | unsigned short value; | |
328 | unsigned char model; | |
329 | ||
330 | dev = eth_get_dev_by_name(devname); | |
331 | if (dev == NULL) { | |
332 | printf("%s: no such device\n", devname); | |
333 | return NULL; | |
334 | } | |
335 | ||
336 | /* read id2 register */ | |
337 | if (get_phyreg(dev, addr, PHY_PHYIDR2, &value) != 0) { | |
338 | printf("%s: mii read timeout!\n", devname); | |
339 | return NULL; | |
340 | } | |
341 | ||
342 | /* get model */ | |
343 | model = (unsigned char)((value >> 4) & 0x003f); | |
344 | ||
345 | if (model == 0) { | |
346 | printf("%s: no PHY at address %d\n", devname, addr); | |
347 | return NULL; | |
348 | } | |
349 | ||
350 | return dev; | |
351 | } | |
352 | ||
353 | static int eepro100_miiphy_read (char *devname, unsigned char addr, | |
354 | unsigned char reg, unsigned short *value) | |
355 | { | |
356 | struct eth_device *dev; | |
357 | ||
358 | dev = verify_phyaddr(devname, addr); | |
359 | if (dev == NULL) | |
360 | return -1; | |
361 | ||
362 | if (get_phyreg(dev, addr, reg, value) != 0) { | |
363 | printf("%s: mii read timeout!\n", devname); | |
364 | return -1; | |
365 | } | |
366 | ||
367 | return 0; | |
368 | } | |
369 | ||
370 | static int eepro100_miiphy_write (char *devname, unsigned char addr, | |
371 | unsigned char reg, unsigned short value) | |
372 | { | |
373 | struct eth_device *dev; | |
374 | ||
375 | dev = verify_phyaddr(devname, addr); | |
376 | if (dev == NULL) | |
377 | return -1; | |
378 | ||
379 | if (set_phyreg(dev, addr, reg, value) != 0) { | |
380 | printf("%s: mii write timeout!\n", devname); | |
381 | return -1; | |
382 | } | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
07d38a17 | 387 | #endif |
63ff004c MB |
388 | |
389 | /* Wait for the chip get the command. | |
390 | */ | |
1df49e27 WD |
391 | static int wait_for_eepro100 (struct eth_device *dev) |
392 | { | |
393 | int i; | |
394 | ||
395 | for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) { | |
396 | if (i >= TOUT_LOOP) { | |
397 | return 0; | |
398 | } | |
399 | } | |
400 | ||
401 | return 1; | |
402 | } | |
403 | ||
404 | static struct pci_device_id supported[] = { | |
405 | {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557}, | |
406 | {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559}, | |
407 | {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER}, | |
408 | {} | |
409 | }; | |
410 | ||
411 | int eepro100_initialize (bd_t * bis) | |
412 | { | |
413 | pci_dev_t devno; | |
414 | int card_number = 0; | |
415 | struct eth_device *dev; | |
416 | u32 iobase, status; | |
417 | int idx = 0; | |
418 | ||
419 | while (1) { | |
420 | /* Find PCI device | |
421 | */ | |
422 | if ((devno = pci_find_devices (supported, idx++)) < 0) { | |
423 | break; | |
424 | } | |
425 | ||
426 | pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase); | |
427 | iobase &= ~0xf; | |
428 | ||
429 | #ifdef DEBUG | |
430 | printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n", | |
431 | iobase); | |
432 | #endif | |
433 | ||
434 | pci_write_config_dword (devno, | |
435 | PCI_COMMAND, | |
436 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
437 | ||
438 | /* Check if I/O accesses and Bus Mastering are enabled. | |
439 | */ | |
440 | pci_read_config_dword (devno, PCI_COMMAND, &status); | |
441 | if (!(status & PCI_COMMAND_MEMORY)) { | |
442 | printf ("Error: Can not enable MEM access.\n"); | |
443 | continue; | |
444 | } | |
445 | ||
446 | if (!(status & PCI_COMMAND_MASTER)) { | |
447 | printf ("Error: Can not enable Bus Mastering.\n"); | |
448 | continue; | |
449 | } | |
450 | ||
451 | dev = (struct eth_device *) malloc (sizeof *dev); | |
452 | ||
453 | sprintf (dev->name, "i82559#%d", card_number); | |
7a8e9bed | 454 | dev->priv = (void *) devno; /* this have to come before bus_to_phys() */ |
1df49e27 | 455 | dev->iobase = bus_to_phys (iobase); |
1df49e27 WD |
456 | dev->init = eepro100_init; |
457 | dev->halt = eepro100_halt; | |
458 | dev->send = eepro100_send; | |
459 | dev->recv = eepro100_recv; | |
460 | ||
461 | eth_register (dev); | |
462 | ||
07d38a17 | 463 | #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII) |
63ff004c MB |
464 | /* register mii command access routines */ |
465 | miiphy_register(dev->name, | |
466 | eepro100_miiphy_read, eepro100_miiphy_write); | |
467 | #endif | |
468 | ||
1df49e27 WD |
469 | card_number++; |
470 | ||
471 | /* Set the latency timer for value. | |
472 | */ | |
473 | pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); | |
474 | ||
475 | udelay (10 * 1000); | |
476 | ||
477 | read_hw_addr (dev, bis); | |
478 | } | |
479 | ||
480 | return card_number; | |
481 | } | |
482 | ||
483 | ||
484 | static int eepro100_init (struct eth_device *dev, bd_t * bis) | |
485 | { | |
422b1a01 | 486 | int i, status = -1; |
1df49e27 WD |
487 | int tx_cur; |
488 | struct descriptor *ias_cmd, *cfg_cmd; | |
489 | ||
490 | /* Reset the ethernet controller | |
491 | */ | |
492 | OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); | |
493 | udelay (20); | |
494 | ||
495 | OUTL (dev, I82559_RESET, SCBPort); | |
496 | udelay (20); | |
497 | ||
498 | if (!wait_for_eepro100 (dev)) { | |
499 | printf ("Error: Can not reset ethernet controller.\n"); | |
500 | goto Done; | |
501 | } | |
502 | OUTL (dev, 0, SCBPointer); | |
503 | OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); | |
504 | ||
505 | if (!wait_for_eepro100 (dev)) { | |
506 | printf ("Error: Can not reset ethernet controller.\n"); | |
507 | goto Done; | |
508 | } | |
509 | OUTL (dev, 0, SCBPointer); | |
510 | OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); | |
511 | ||
512 | /* Initialize Rx and Tx rings. | |
513 | */ | |
514 | init_rx_ring (dev); | |
515 | purge_tx_ring (dev); | |
516 | ||
517 | /* Tell the adapter where the RX ring is located. | |
518 | */ | |
519 | if (!wait_for_eepro100 (dev)) { | |
520 | printf ("Error: Can not reset ethernet controller.\n"); | |
521 | goto Done; | |
522 | } | |
523 | ||
524 | OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); | |
525 | OUTW (dev, SCB_M | RUC_START, SCBCmd); | |
526 | ||
527 | /* Send the Configure frame */ | |
528 | tx_cur = tx_next; | |
529 | tx_next = ((tx_next + 1) % NUM_TX_DESC); | |
530 | ||
531 | cfg_cmd = (struct descriptor *) &tx_ring[tx_cur]; | |
6d0f6bcf | 532 | cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE)); |
1df49e27 WD |
533 | cfg_cmd->status = 0; |
534 | cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); | |
535 | ||
536 | memcpy (cfg_cmd->params, i82558_config_cmd, | |
537 | sizeof (i82558_config_cmd)); | |
538 | ||
539 | if (!wait_for_eepro100 (dev)) { | |
6d0f6bcf | 540 | printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n"); |
1df49e27 WD |
541 | goto Done; |
542 | } | |
543 | ||
544 | OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); | |
545 | OUTW (dev, SCB_M | CU_START, SCBCmd); | |
546 | ||
547 | for (i = 0; | |
6d0f6bcf | 548 | !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); |
1df49e27 WD |
549 | i++) { |
550 | if (i >= TOUT_LOOP) { | |
551 | printf ("%s: Tx error buffer not ready\n", dev->name); | |
552 | goto Done; | |
553 | } | |
554 | } | |
555 | ||
6d0f6bcf | 556 | if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { |
1df49e27 WD |
557 | printf ("TX error status = 0x%08X\n", |
558 | le16_to_cpu (tx_ring[tx_cur].status)); | |
559 | goto Done; | |
560 | } | |
561 | ||
562 | /* Send the Individual Address Setup frame | |
563 | */ | |
564 | tx_cur = tx_next; | |
565 | tx_next = ((tx_next + 1) % NUM_TX_DESC); | |
566 | ||
567 | ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; | |
6d0f6bcf | 568 | ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS)); |
1df49e27 WD |
569 | ias_cmd->status = 0; |
570 | ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); | |
571 | ||
572 | memcpy (ias_cmd->params, dev->enetaddr, 6); | |
573 | ||
574 | /* Tell the adapter where the TX ring is located. | |
575 | */ | |
576 | if (!wait_for_eepro100 (dev)) { | |
577 | printf ("Error: Can not reset ethernet controller.\n"); | |
578 | goto Done; | |
579 | } | |
580 | ||
581 | OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); | |
582 | OUTW (dev, SCB_M | CU_START, SCBCmd); | |
583 | ||
6d0f6bcf | 584 | for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); |
1df49e27 WD |
585 | i++) { |
586 | if (i >= TOUT_LOOP) { | |
587 | printf ("%s: Tx error buffer not ready\n", | |
588 | dev->name); | |
589 | goto Done; | |
590 | } | |
591 | } | |
592 | ||
6d0f6bcf | 593 | if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { |
1df49e27 WD |
594 | printf ("TX error status = 0x%08X\n", |
595 | le16_to_cpu (tx_ring[tx_cur].status)); | |
596 | goto Done; | |
597 | } | |
598 | ||
422b1a01 | 599 | status = 0; |
1df49e27 WD |
600 | |
601 | Done: | |
602 | return status; | |
603 | } | |
604 | ||
605 | static int eepro100_send (struct eth_device *dev, volatile void *packet, int length) | |
606 | { | |
607 | int i, status = -1; | |
608 | int tx_cur; | |
609 | ||
610 | if (length <= 0) { | |
611 | printf ("%s: bad packet size: %d\n", dev->name, length); | |
612 | goto Done; | |
613 | } | |
614 | ||
615 | tx_cur = tx_next; | |
616 | tx_next = (tx_next + 1) % NUM_TX_DESC; | |
617 | ||
618 | tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT | | |
619 | TxCB_CMD_SF | | |
620 | TxCB_CMD_S | | |
621 | TxCB_CMD_EL ); | |
622 | tx_ring[tx_cur].status = 0; | |
623 | tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold); | |
624 | tx_ring[tx_cur].link = | |
625 | cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next])); | |
626 | tx_ring[tx_cur].tx_desc_addr = | |
627 | cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0)); | |
628 | tx_ring[tx_cur].tx_buf_addr0 = | |
629 | cpu_to_le32 (phys_to_bus ((u_long) packet)); | |
630 | tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length); | |
631 | ||
632 | if (!wait_for_eepro100 (dev)) { | |
633 | printf ("%s: Tx error ethernet controller not ready.\n", | |
634 | dev->name); | |
635 | goto Done; | |
636 | } | |
637 | ||
638 | /* Send the packet. | |
639 | */ | |
640 | OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer); | |
641 | OUTW (dev, SCB_M | CU_START, SCBCmd); | |
642 | ||
6d0f6bcf | 643 | for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C); |
1df49e27 WD |
644 | i++) { |
645 | if (i >= TOUT_LOOP) { | |
646 | printf ("%s: Tx error buffer not ready\n", dev->name); | |
647 | goto Done; | |
648 | } | |
649 | } | |
650 | ||
6d0f6bcf | 651 | if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) { |
1df49e27 WD |
652 | printf ("TX error status = 0x%08X\n", |
653 | le16_to_cpu (tx_ring[tx_cur].status)); | |
654 | goto Done; | |
655 | } | |
656 | ||
657 | status = length; | |
658 | ||
659 | Done: | |
660 | return status; | |
661 | } | |
662 | ||
663 | static int eepro100_recv (struct eth_device *dev) | |
664 | { | |
665 | u16 status, stat; | |
666 | int rx_prev, length = 0; | |
667 | ||
668 | stat = INW (dev, SCBStatus); | |
669 | OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus); | |
670 | ||
671 | for (;;) { | |
672 | status = le16_to_cpu (rx_ring[rx_next].status); | |
673 | ||
674 | if (!(status & RFD_STATUS_C)) { | |
675 | break; | |
676 | } | |
677 | ||
678 | /* Valid frame status. | |
679 | */ | |
680 | if ((status & RFD_STATUS_OK)) { | |
681 | /* A valid frame received. | |
682 | */ | |
683 | length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff; | |
684 | ||
685 | /* Pass the packet up to the protocol | |
686 | * layers. | |
687 | */ | |
688 | NetReceive (rx_ring[rx_next].data, length); | |
689 | } else { | |
690 | /* There was an error. | |
691 | */ | |
692 | printf ("RX error status = 0x%08X\n", status); | |
693 | } | |
694 | ||
695 | rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S); | |
696 | rx_ring[rx_next].status = 0; | |
697 | rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); | |
698 | ||
699 | rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC; | |
700 | rx_ring[rx_prev].control = 0; | |
701 | ||
702 | /* Update entry information. | |
703 | */ | |
704 | rx_next = (rx_next + 1) % NUM_RX_DESC; | |
705 | } | |
706 | ||
707 | if (stat & SCB_STATUS_RNR) { | |
708 | ||
709 | printf ("%s: Receiver is not ready, restart it !\n", dev->name); | |
710 | ||
711 | /* Reinitialize Rx ring. | |
712 | */ | |
713 | init_rx_ring (dev); | |
714 | ||
715 | if (!wait_for_eepro100 (dev)) { | |
716 | printf ("Error: Can not restart ethernet controller.\n"); | |
717 | goto Done; | |
718 | } | |
719 | ||
720 | OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer); | |
721 | OUTW (dev, SCB_M | RUC_START, SCBCmd); | |
722 | } | |
723 | ||
724 | Done: | |
725 | return length; | |
726 | } | |
727 | ||
728 | static void eepro100_halt (struct eth_device *dev) | |
729 | { | |
730 | /* Reset the ethernet controller | |
731 | */ | |
732 | OUTL (dev, I82559_SELECTIVE_RESET, SCBPort); | |
733 | udelay (20); | |
734 | ||
735 | OUTL (dev, I82559_RESET, SCBPort); | |
736 | udelay (20); | |
737 | ||
738 | if (!wait_for_eepro100 (dev)) { | |
739 | printf ("Error: Can not reset ethernet controller.\n"); | |
740 | goto Done; | |
741 | } | |
742 | OUTL (dev, 0, SCBPointer); | |
743 | OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd); | |
744 | ||
745 | if (!wait_for_eepro100 (dev)) { | |
746 | printf ("Error: Can not reset ethernet controller.\n"); | |
747 | goto Done; | |
748 | } | |
749 | OUTL (dev, 0, SCBPointer); | |
750 | OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd); | |
751 | ||
752 | Done: | |
753 | return; | |
754 | } | |
755 | ||
756 | /* SROM Read. | |
757 | */ | |
758 | static int read_eeprom (struct eth_device *dev, int location, int addr_len) | |
759 | { | |
760 | unsigned short retval = 0; | |
761 | int read_cmd = location | EE_READ_CMD; | |
762 | int i; | |
763 | ||
764 | OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); | |
765 | OUTW (dev, EE_ENB, SCBeeprom); | |
766 | ||
767 | /* Shift the read command bits out. */ | |
768 | for (i = 12; i >= 0; i--) { | |
769 | short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; | |
770 | ||
771 | OUTW (dev, EE_ENB | dataval, SCBeeprom); | |
772 | udelay (1); | |
773 | OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); | |
774 | udelay (1); | |
775 | } | |
776 | OUTW (dev, EE_ENB, SCBeeprom); | |
777 | ||
778 | for (i = 15; i >= 0; i--) { | |
779 | OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom); | |
780 | udelay (1); | |
781 | retval = (retval << 1) | | |
782 | ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0); | |
783 | OUTW (dev, EE_ENB, SCBeeprom); | |
784 | udelay (1); | |
785 | } | |
786 | ||
787 | /* Terminate the EEPROM access. */ | |
788 | OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom); | |
789 | return retval; | |
790 | } | |
791 | ||
792 | #ifdef CONFIG_EEPRO100_SROM_WRITE | |
793 | int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data) | |
794 | { | |
795 | unsigned short dataval; | |
796 | int enable_cmd = 0x3f | EE_EWENB_CMD; | |
797 | int write_cmd = location | EE_WRITE_CMD; | |
798 | int i; | |
799 | unsigned long datalong, tmplong; | |
800 | ||
801 | OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); | |
802 | udelay(1); | |
803 | OUTW(dev, EE_ENB, SCBeeprom); | |
804 | ||
805 | /* Shift the enable command bits out. */ | |
806 | for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) | |
807 | { | |
8bde7f77 WD |
808 | dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0; |
809 | OUTW(dev, EE_ENB | dataval, SCBeeprom); | |
810 | udelay(1); | |
811 | OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); | |
812 | udelay(1); | |
1df49e27 WD |
813 | } |
814 | ||
815 | OUTW(dev, EE_ENB, SCBeeprom); | |
816 | udelay(1); | |
817 | OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); | |
818 | udelay(1); | |
819 | OUTW(dev, EE_ENB, SCBeeprom); | |
820 | ||
821 | ||
822 | /* Shift the write command bits out. */ | |
823 | for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) | |
824 | { | |
8bde7f77 WD |
825 | dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0; |
826 | OUTW(dev, EE_ENB | dataval, SCBeeprom); | |
827 | udelay(1); | |
828 | OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); | |
829 | udelay(1); | |
1df49e27 WD |
830 | } |
831 | ||
832 | /* Write the data */ | |
833 | datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8)); | |
834 | ||
835 | for (i = 0; i< EE_DATA_BITS; i++) | |
836 | { | |
837 | /* Extract and move data bit to bit DI */ | |
838 | dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0; | |
839 | ||
840 | OUTW(dev, EE_ENB | dataval, SCBeeprom); | |
841 | udelay(1); | |
842 | OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); | |
843 | udelay(1); | |
844 | OUTW(dev, EE_ENB | dataval, SCBeeprom); | |
845 | udelay(1); | |
846 | ||
c570b2fd | 847 | datalong = datalong << 1; /* Adjust significant data bit*/ |
1df49e27 WD |
848 | } |
849 | ||
850 | /* Finish up command (toggle CS) */ | |
851 | OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); | |
c570b2fd | 852 | udelay(1); /* delay for more than 250 ns */ |
1df49e27 WD |
853 | OUTW(dev, EE_ENB, SCBeeprom); |
854 | ||
855 | /* Wait for programming ready (D0 = 1) */ | |
856 | tmplong = 10; | |
857 | do | |
858 | { | |
8bde7f77 WD |
859 | dataval = INW(dev, SCBeeprom); |
860 | if (dataval & EE_DATA_READ) | |
861 | break; | |
862 | udelay(10000); | |
1df49e27 WD |
863 | } |
864 | while (-- tmplong); | |
865 | ||
866 | if (tmplong == 0) | |
867 | { | |
8bde7f77 WD |
868 | printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n"); |
869 | return -1; | |
1df49e27 WD |
870 | } |
871 | ||
872 | /* Terminate the EEPROM access. */ | |
873 | OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom); | |
874 | ||
875 | return 0; | |
876 | } | |
877 | #endif | |
878 | ||
879 | static void init_rx_ring (struct eth_device *dev) | |
880 | { | |
881 | int i; | |
882 | ||
883 | for (i = 0; i < NUM_RX_DESC; i++) { | |
884 | rx_ring[i].status = 0; | |
885 | rx_ring[i].control = | |
886 | (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0; | |
887 | rx_ring[i].link = | |
888 | cpu_to_le32 (phys_to_bus | |
889 | ((u32) & rx_ring[(i + 1) % NUM_RX_DESC])); | |
890 | rx_ring[i].rx_buf_addr = 0xffffffff; | |
891 | rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16); | |
892 | } | |
893 | ||
894 | rx_next = 0; | |
895 | } | |
896 | ||
897 | static void purge_tx_ring (struct eth_device *dev) | |
898 | { | |
899 | int i; | |
900 | ||
901 | tx_next = 0; | |
902 | tx_threshold = 0x01208000; | |
903 | ||
904 | for (i = 0; i < NUM_TX_DESC; i++) { | |
905 | tx_ring[i].status = 0; | |
906 | tx_ring[i].command = 0; | |
907 | tx_ring[i].link = 0; | |
908 | tx_ring[i].tx_desc_addr = 0; | |
909 | tx_ring[i].count = 0; | |
910 | ||
911 | tx_ring[i].tx_buf_addr0 = 0; | |
912 | tx_ring[i].tx_buf_size0 = 0; | |
913 | tx_ring[i].tx_buf_addr1 = 0; | |
914 | tx_ring[i].tx_buf_size1 = 0; | |
915 | } | |
916 | } | |
917 | ||
918 | static void read_hw_addr (struct eth_device *dev, bd_t * bis) | |
919 | { | |
920 | u16 eeprom[0x40]; | |
921 | u16 sum = 0; | |
922 | int i, j; | |
923 | int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6; | |
924 | ||
925 | for (j = 0, i = 0; i < 0x40; i++) { | |
926 | u16 value = read_eeprom (dev, i, addr_len); | |
927 | ||
928 | eeprom[i] = value; | |
929 | sum += value; | |
930 | if (i < 3) { | |
931 | dev->enetaddr[j++] = value; | |
932 | dev->enetaddr[j++] = value >> 8; | |
933 | } | |
934 | } | |
935 | ||
936 | if (sum != 0xBABA) { | |
937 | memset (dev->enetaddr, 0, ETH_ALEN); | |
938 | #ifdef DEBUG | |
939 | printf ("%s: Invalid EEPROM checksum %#4.4x, " | |
940 | "check settings before activating this device!\n", | |
941 | dev->name, sum); | |
942 | #endif | |
943 | } | |
944 | } |