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0b23fb36 IY |
1 | /* |
2 | * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> | |
3 | * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> | |
4 | * (C) Copyright 2008 Armadeus Systems nc | |
5 | * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
6 | * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
0b23fb36 IY |
9 | */ |
10 | ||
11 | #include <common.h> | |
12 | #include <malloc.h> | |
13 | #include <net.h> | |
84f64c8b | 14 | #include <netdev.h> |
0b23fb36 IY |
15 | #include <miiphy.h> |
16 | #include "fec_mxc.h" | |
17 | ||
18 | #include <asm/arch/clock.h> | |
19 | #include <asm/arch/imx-regs.h> | |
fbecbaa1 | 20 | #include <asm/imx-common/sys_proto.h> |
0b23fb36 IY |
21 | #include <asm/io.h> |
22 | #include <asm/errno.h> | |
e2a66e60 | 23 | #include <linux/compiler.h> |
0b23fb36 IY |
24 | |
25 | DECLARE_GLOBAL_DATA_PTR; | |
26 | ||
bc1ce150 MV |
27 | /* |
28 | * Timeout the transfer after 5 mS. This is usually a bit more, since | |
29 | * the code in the tightloops this timeout is used in adds some overhead. | |
30 | */ | |
31 | #define FEC_XFER_TIMEOUT 5000 | |
32 | ||
db5b7f56 FE |
33 | /* |
34 | * The standard 32-byte DMA alignment does not work on mx6solox, which requires | |
35 | * 64-byte alignment in the DMA RX FEC buffer. | |
36 | * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also | |
37 | * satisfies the alignment on other SoCs (32-bytes) | |
38 | */ | |
39 | #define FEC_DMA_RX_MINALIGN 64 | |
40 | ||
0b23fb36 IY |
41 | #ifndef CONFIG_MII |
42 | #error "CONFIG_MII has to be defined!" | |
43 | #endif | |
44 | ||
5c1ad3e6 EN |
45 | #ifndef CONFIG_FEC_XCV_TYPE |
46 | #define CONFIG_FEC_XCV_TYPE MII100 | |
392b8502 MV |
47 | #endif |
48 | ||
be7e87e2 MV |
49 | /* |
50 | * The i.MX28 operates with packets in big endian. We need to swap them before | |
51 | * sending and after receiving. | |
52 | */ | |
5c1ad3e6 EN |
53 | #ifdef CONFIG_MX28 |
54 | #define CONFIG_FEC_MXC_SWAP_PACKET | |
55 | #endif | |
56 | ||
57 | #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) | |
58 | ||
59 | /* Check various alignment issues at compile time */ | |
60 | #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) | |
61 | #error "ARCH_DMA_MINALIGN must be multiple of 16!" | |
62 | #endif | |
63 | ||
64 | #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ | |
65 | (PKTALIGN % ARCH_DMA_MINALIGN != 0)) | |
66 | #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" | |
be7e87e2 MV |
67 | #endif |
68 | ||
0b23fb36 IY |
69 | #undef DEBUG |
70 | ||
5c1ad3e6 | 71 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
72 | static void swap_packet(uint32_t *packet, int length) |
73 | { | |
74 | int i; | |
75 | ||
76 | for (i = 0; i < DIV_ROUND_UP(length, 4); i++) | |
77 | packet[i] = __swab32(packet[i]); | |
78 | } | |
79 | #endif | |
80 | ||
0b23fb36 IY |
81 | /* |
82 | * MII-interface related functions | |
83 | */ | |
13947f43 TK |
84 | static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, |
85 | uint8_t regAddr) | |
0b23fb36 | 86 | { |
0b23fb36 IY |
87 | uint32_t reg; /* convenient holder for the PHY register */ |
88 | uint32_t phy; /* convenient holder for the PHY */ | |
89 | uint32_t start; | |
13947f43 | 90 | int val; |
0b23fb36 IY |
91 | |
92 | /* | |
93 | * reading from any PHY's register is done by properly | |
94 | * programming the FEC's MII data register. | |
95 | */ | |
d133b881 | 96 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
97 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; |
98 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
99 | ||
100 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | | |
d133b881 | 101 | phy | reg, ð->mii_data); |
0b23fb36 IY |
102 | |
103 | /* | |
104 | * wait for the related interrupt | |
105 | */ | |
a60d1e5b | 106 | start = get_timer(0); |
d133b881 | 107 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
108 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
109 | printf("Read MDIO failed...\n"); | |
110 | return -1; | |
111 | } | |
112 | } | |
113 | ||
114 | /* | |
115 | * clear mii interrupt bit | |
116 | */ | |
d133b881 | 117 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
118 | |
119 | /* | |
120 | * it's now safe to read the PHY's register | |
121 | */ | |
13947f43 TK |
122 | val = (unsigned short)readl(ð->mii_data); |
123 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, | |
124 | regAddr, val); | |
125 | return val; | |
0b23fb36 IY |
126 | } |
127 | ||
575c5cc0 | 128 | static void fec_mii_setspeed(struct ethernet_regs *eth) |
4294b248 SB |
129 | { |
130 | /* | |
131 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock | |
132 | * and do not drop the Preamble. | |
133 | */ | |
6ba45cc0 MN |
134 | register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000); |
135 | #ifdef FEC_QUIRK_ENET_MAC | |
136 | speed--; | |
137 | #endif | |
138 | speed <<= 1; | |
139 | writel(speed, ð->mii_speed); | |
575c5cc0 | 140 | debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); |
4294b248 | 141 | } |
0b23fb36 | 142 | |
13947f43 TK |
143 | static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, |
144 | uint8_t regAddr, uint16_t data) | |
145 | { | |
0b23fb36 IY |
146 | uint32_t reg; /* convenient holder for the PHY register */ |
147 | uint32_t phy; /* convenient holder for the PHY */ | |
148 | uint32_t start; | |
149 | ||
150 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; | |
151 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
152 | ||
153 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | | |
d133b881 | 154 | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); |
0b23fb36 IY |
155 | |
156 | /* | |
157 | * wait for the MII interrupt | |
158 | */ | |
a60d1e5b | 159 | start = get_timer(0); |
d133b881 | 160 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
161 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
162 | printf("Write MDIO failed...\n"); | |
163 | return -1; | |
164 | } | |
165 | } | |
166 | ||
167 | /* | |
168 | * clear MII interrupt bit | |
169 | */ | |
d133b881 | 170 | writel(FEC_IEVENT_MII, ð->ievent); |
13947f43 | 171 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, |
0b23fb36 IY |
172 | regAddr, data); |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
84f64c8b JH |
177 | static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, |
178 | int regAddr) | |
13947f43 TK |
179 | { |
180 | return fec_mdio_read(bus->priv, phyAddr, regAddr); | |
181 | } | |
182 | ||
84f64c8b JH |
183 | static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, |
184 | int regAddr, u16 data) | |
13947f43 TK |
185 | { |
186 | return fec_mdio_write(bus->priv, phyAddr, regAddr, data); | |
187 | } | |
188 | ||
189 | #ifndef CONFIG_PHYLIB | |
0b23fb36 IY |
190 | static int miiphy_restart_aneg(struct eth_device *dev) |
191 | { | |
b774fe9d SB |
192 | int ret = 0; |
193 | #if !defined(CONFIG_FEC_MXC_NO_ANEG) | |
9e27e9dc | 194 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 195 | struct ethernet_regs *eth = fec->bus->priv; |
9e27e9dc | 196 | |
0b23fb36 IY |
197 | /* |
198 | * Wake up from sleep if necessary | |
199 | * Reset PHY, then delay 300ns | |
200 | */ | |
cb17b92d | 201 | #ifdef CONFIG_MX27 |
13947f43 | 202 | fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); |
cb17b92d | 203 | #endif |
13947f43 | 204 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); |
0b23fb36 IY |
205 | udelay(1000); |
206 | ||
207 | /* | |
208 | * Set the auto-negotiation advertisement register bits | |
209 | */ | |
13947f43 | 210 | fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, |
8ef583a0 MF |
211 | LPA_100FULL | LPA_100HALF | LPA_10FULL | |
212 | LPA_10HALF | PHY_ANLPAR_PSB_802_3); | |
13947f43 | 213 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, |
8ef583a0 | 214 | BMCR_ANENABLE | BMCR_ANRESTART); |
2e5f4421 MV |
215 | |
216 | if (fec->mii_postcall) | |
217 | ret = fec->mii_postcall(fec->phy_id); | |
218 | ||
b774fe9d | 219 | #endif |
2e5f4421 | 220 | return ret; |
0b23fb36 IY |
221 | } |
222 | ||
223 | static int miiphy_wait_aneg(struct eth_device *dev) | |
224 | { | |
225 | uint32_t start; | |
13947f43 | 226 | int status; |
9e27e9dc | 227 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 228 | struct ethernet_regs *eth = fec->bus->priv; |
0b23fb36 IY |
229 | |
230 | /* | |
231 | * Wait for AN completion | |
232 | */ | |
a60d1e5b | 233 | start = get_timer(0); |
0b23fb36 IY |
234 | do { |
235 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
236 | printf("%s: Autonegotiation timeout\n", dev->name); | |
237 | return -1; | |
238 | } | |
239 | ||
13947f43 TK |
240 | status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); |
241 | if (status < 0) { | |
242 | printf("%s: Autonegotiation failed. status: %d\n", | |
0b23fb36 IY |
243 | dev->name, status); |
244 | return -1; | |
245 | } | |
8ef583a0 | 246 | } while (!(status & BMSR_LSTATUS)); |
0b23fb36 IY |
247 | |
248 | return 0; | |
249 | } | |
13947f43 TK |
250 | #endif |
251 | ||
0b23fb36 IY |
252 | static int fec_rx_task_enable(struct fec_priv *fec) |
253 | { | |
c0b5a3bb | 254 | writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active); |
0b23fb36 IY |
255 | return 0; |
256 | } | |
257 | ||
258 | static int fec_rx_task_disable(struct fec_priv *fec) | |
259 | { | |
260 | return 0; | |
261 | } | |
262 | ||
263 | static int fec_tx_task_enable(struct fec_priv *fec) | |
264 | { | |
c0b5a3bb | 265 | writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active); |
0b23fb36 IY |
266 | return 0; |
267 | } | |
268 | ||
269 | static int fec_tx_task_disable(struct fec_priv *fec) | |
270 | { | |
271 | return 0; | |
272 | } | |
273 | ||
274 | /** | |
275 | * Initialize receive task's buffer descriptors | |
276 | * @param[in] fec all we know about the device yet | |
277 | * @param[in] count receive buffer count to be allocated | |
5c1ad3e6 | 278 | * @param[in] dsize desired size of each receive buffer |
0b23fb36 IY |
279 | * @return 0 on success |
280 | * | |
79e5f27b | 281 | * Init all RX descriptors to default values. |
0b23fb36 | 282 | */ |
79e5f27b | 283 | static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) |
0b23fb36 | 284 | { |
5c1ad3e6 | 285 | uint32_t size; |
79e5f27b | 286 | uint8_t *data; |
5c1ad3e6 EN |
287 | int i; |
288 | ||
0b23fb36 | 289 | /* |
79e5f27b MV |
290 | * Reload the RX descriptors with default values and wipe |
291 | * the RX buffers. | |
0b23fb36 | 292 | */ |
5c1ad3e6 EN |
293 | size = roundup(dsize, ARCH_DMA_MINALIGN); |
294 | for (i = 0; i < count; i++) { | |
79e5f27b MV |
295 | data = (uint8_t *)fec->rbd_base[i].data_pointer; |
296 | memset(data, 0, dsize); | |
297 | flush_dcache_range((uint32_t)data, (uint32_t)data + size); | |
298 | ||
299 | fec->rbd_base[i].status = FEC_RBD_EMPTY; | |
300 | fec->rbd_base[i].data_length = 0; | |
5c1ad3e6 EN |
301 | } |
302 | ||
303 | /* Mark the last RBD to close the ring. */ | |
79e5f27b | 304 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; |
0b23fb36 IY |
305 | fec->rbd_index = 0; |
306 | ||
79e5f27b MV |
307 | flush_dcache_range((unsigned)fec->rbd_base, |
308 | (unsigned)fec->rbd_base + size); | |
0b23fb36 IY |
309 | } |
310 | ||
311 | /** | |
312 | * Initialize transmit task's buffer descriptors | |
313 | * @param[in] fec all we know about the device yet | |
314 | * | |
315 | * Transmit buffers are created externally. We only have to init the BDs here.\n | |
316 | * Note: There is a race condition in the hardware. When only one BD is in | |
317 | * use it must be marked with the WRAP bit to use it for every transmitt. | |
318 | * This bit in combination with the READY bit results into double transmit | |
319 | * of each data buffer. It seems the state machine checks READY earlier then | |
320 | * resetting it after the first transfer. | |
321 | * Using two BDs solves this issue. | |
322 | */ | |
323 | static void fec_tbd_init(struct fec_priv *fec) | |
324 | { | |
5c1ad3e6 EN |
325 | unsigned addr = (unsigned)fec->tbd_base; |
326 | unsigned size = roundup(2 * sizeof(struct fec_bd), | |
327 | ARCH_DMA_MINALIGN); | |
79e5f27b MV |
328 | |
329 | memset(fec->tbd_base, 0, size); | |
330 | fec->tbd_base[0].status = 0; | |
331 | fec->tbd_base[1].status = FEC_TBD_WRAP; | |
0b23fb36 | 332 | fec->tbd_index = 0; |
79e5f27b | 333 | flush_dcache_range(addr, addr + size); |
0b23fb36 IY |
334 | } |
335 | ||
336 | /** | |
337 | * Mark the given read buffer descriptor as free | |
338 | * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 | |
339 | * @param[in] pRbd buffer descriptor to mark free again | |
340 | */ | |
341 | static void fec_rbd_clean(int last, struct fec_bd *pRbd) | |
342 | { | |
5c1ad3e6 | 343 | unsigned short flags = FEC_RBD_EMPTY; |
0b23fb36 | 344 | if (last) |
5c1ad3e6 EN |
345 | flags |= FEC_RBD_WRAP; |
346 | writew(flags, &pRbd->status); | |
0b23fb36 IY |
347 | writew(0, &pRbd->data_length); |
348 | } | |
349 | ||
be252b65 FE |
350 | static int fec_get_hwaddr(struct eth_device *dev, int dev_id, |
351 | unsigned char *mac) | |
0b23fb36 | 352 | { |
be252b65 | 353 | imx_get_mac_from_fuse(dev_id, mac); |
0adb5b76 | 354 | return !is_valid_ethaddr(mac); |
0b23fb36 IY |
355 | } |
356 | ||
4294b248 | 357 | static int fec_set_hwaddr(struct eth_device *dev) |
0b23fb36 | 358 | { |
4294b248 | 359 | uchar *mac = dev->enetaddr; |
0b23fb36 IY |
360 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
361 | ||
362 | writel(0, &fec->eth->iaddr1); | |
363 | writel(0, &fec->eth->iaddr2); | |
364 | writel(0, &fec->eth->gaddr1); | |
365 | writel(0, &fec->eth->gaddr2); | |
366 | ||
367 | /* | |
368 | * Set physical address | |
369 | */ | |
370 | writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], | |
371 | &fec->eth->paddr1); | |
372 | writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
a5990b26 MV |
377 | /* |
378 | * Do initial configuration of the FEC registers | |
379 | */ | |
380 | static void fec_reg_setup(struct fec_priv *fec) | |
381 | { | |
382 | uint32_t rcntrl; | |
383 | ||
384 | /* | |
385 | * Set interrupt mask register | |
386 | */ | |
387 | writel(0x00000000, &fec->eth->imask); | |
388 | ||
389 | /* | |
390 | * Clear FEC-Lite interrupt event register(IEVENT) | |
391 | */ | |
392 | writel(0xffffffff, &fec->eth->ievent); | |
393 | ||
394 | ||
395 | /* | |
396 | * Set FEC-Lite receive control register(R_CNTRL): | |
397 | */ | |
398 | ||
399 | /* Start with frame length = 1518, common for all modes. */ | |
400 | rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; | |
9d2d924a | 401 | if (fec->xcv_type != SEVENWIRE) /* xMII modes */ |
402 | rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; | |
403 | if (fec->xcv_type == RGMII) | |
a5990b26 MV |
404 | rcntrl |= FEC_RCNTRL_RGMII; |
405 | else if (fec->xcv_type == RMII) | |
406 | rcntrl |= FEC_RCNTRL_RMII; | |
a5990b26 MV |
407 | |
408 | writel(rcntrl, &fec->eth->r_cntrl); | |
409 | } | |
410 | ||
0b23fb36 IY |
411 | /** |
412 | * Start the FEC engine | |
413 | * @param[in] dev Our device to handle | |
414 | */ | |
415 | static int fec_open(struct eth_device *edev) | |
416 | { | |
417 | struct fec_priv *fec = (struct fec_priv *)edev->priv; | |
28774cba | 418 | int speed; |
5c1ad3e6 EN |
419 | uint32_t addr, size; |
420 | int i; | |
0b23fb36 IY |
421 | |
422 | debug("fec_open: fec_open(dev)\n"); | |
423 | /* full-duplex, heartbeat disabled */ | |
424 | writel(1 << 2, &fec->eth->x_cntrl); | |
425 | fec->rbd_index = 0; | |
426 | ||
5c1ad3e6 EN |
427 | /* Invalidate all descriptors */ |
428 | for (i = 0; i < FEC_RBD_NUM - 1; i++) | |
429 | fec_rbd_clean(0, &fec->rbd_base[i]); | |
430 | fec_rbd_clean(1, &fec->rbd_base[i]); | |
431 | ||
432 | /* Flush the descriptors into RAM */ | |
433 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
434 | ARCH_DMA_MINALIGN); | |
435 | addr = (uint32_t)fec->rbd_base; | |
436 | flush_dcache_range(addr, addr + size); | |
437 | ||
28774cba | 438 | #ifdef FEC_QUIRK_ENET_MAC |
2ef2b950 JL |
439 | /* Enable ENET HW endian SWAP */ |
440 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, | |
441 | &fec->eth->ecntrl); | |
442 | /* Enable ENET store and forward mode */ | |
443 | writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, | |
444 | &fec->eth->x_wmrk); | |
445 | #endif | |
0b23fb36 IY |
446 | /* |
447 | * Enable FEC-Lite controller | |
448 | */ | |
cb17b92d JR |
449 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, |
450 | &fec->eth->ecntrl); | |
7df51fd8 | 451 | #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) |
740d6ae5 JR |
452 | udelay(100); |
453 | /* | |
454 | * setup the MII gasket for RMII mode | |
455 | */ | |
456 | ||
457 | /* disable the gasket */ | |
458 | writew(0, &fec->eth->miigsk_enr); | |
459 | ||
460 | /* wait for the gasket to be disabled */ | |
461 | while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) | |
462 | udelay(2); | |
463 | ||
464 | /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ | |
465 | writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); | |
466 | ||
467 | /* re-enable the gasket */ | |
468 | writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); | |
469 | ||
470 | /* wait until MII gasket is ready */ | |
471 | int max_loops = 10; | |
472 | while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { | |
473 | if (--max_loops <= 0) { | |
474 | printf("WAIT for MII Gasket ready timed out\n"); | |
475 | break; | |
476 | } | |
477 | } | |
478 | #endif | |
0b23fb36 | 479 | |
13947f43 | 480 | #ifdef CONFIG_PHYLIB |
4dc27eed | 481 | { |
13947f43 | 482 | /* Start up the PHY */ |
11af8d65 TT |
483 | int ret = phy_startup(fec->phydev); |
484 | ||
485 | if (ret) { | |
486 | printf("Could not initialize PHY %s\n", | |
487 | fec->phydev->dev->name); | |
488 | return ret; | |
489 | } | |
13947f43 | 490 | speed = fec->phydev->speed; |
13947f43 TK |
491 | } |
492 | #else | |
0b23fb36 | 493 | miiphy_wait_aneg(edev); |
28774cba | 494 | speed = miiphy_speed(edev->name, fec->phy_id); |
9e27e9dc | 495 | miiphy_duplex(edev->name, fec->phy_id); |
13947f43 | 496 | #endif |
0b23fb36 | 497 | |
28774cba TK |
498 | #ifdef FEC_QUIRK_ENET_MAC |
499 | { | |
500 | u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; | |
bcb6e902 | 501 | u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; |
28774cba TK |
502 | if (speed == _1000BASET) |
503 | ecr |= FEC_ECNTRL_SPEED; | |
504 | else if (speed != _100BASET) | |
505 | rcr |= FEC_RCNTRL_RMII_10T; | |
506 | writel(ecr, &fec->eth->ecntrl); | |
507 | writel(rcr, &fec->eth->r_cntrl); | |
508 | } | |
509 | #endif | |
510 | debug("%s:Speed=%i\n", __func__, speed); | |
511 | ||
0b23fb36 IY |
512 | /* |
513 | * Enable SmartDMA receive task | |
514 | */ | |
515 | fec_rx_task_enable(fec); | |
516 | ||
517 | udelay(100000); | |
518 | return 0; | |
519 | } | |
520 | ||
521 | static int fec_init(struct eth_device *dev, bd_t* bd) | |
522 | { | |
0b23fb36 | 523 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
9e27e9dc | 524 | uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; |
79e5f27b | 525 | int i; |
0b23fb36 | 526 | |
e9319f11 JR |
527 | /* Initialize MAC address */ |
528 | fec_set_hwaddr(dev); | |
529 | ||
0b23fb36 | 530 | /* |
79e5f27b | 531 | * Setup transmit descriptors, there are two in total. |
0b23fb36 | 532 | */ |
79e5f27b | 533 | fec_tbd_init(fec); |
0b23fb36 | 534 | |
79e5f27b MV |
535 | /* Setup receive descriptors. */ |
536 | fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); | |
0b23fb36 | 537 | |
a5990b26 | 538 | fec_reg_setup(fec); |
9eb3770b | 539 | |
f41471e6 | 540 | if (fec->xcv_type != SEVENWIRE) |
575c5cc0 | 541 | fec_mii_setspeed(fec->bus->priv); |
9eb3770b | 542 | |
0b23fb36 IY |
543 | /* |
544 | * Set Opcode/Pause Duration Register | |
545 | */ | |
546 | writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ | |
547 | writel(0x2, &fec->eth->x_wmrk); | |
548 | /* | |
549 | * Set multicast address filter | |
550 | */ | |
551 | writel(0x00000000, &fec->eth->gaddr1); | |
552 | writel(0x00000000, &fec->eth->gaddr2); | |
553 | ||
554 | ||
fbecbaa1 PF |
555 | /* Do not access reserved register for i.MX6UL */ |
556 | if (!is_cpu_type(MXC_CPU_MX6UL)) { | |
557 | /* clear MIB RAM */ | |
558 | for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) | |
559 | writel(0, i); | |
0b23fb36 | 560 | |
fbecbaa1 PF |
561 | /* FIFO receive start register */ |
562 | writel(0x520, &fec->eth->r_fstart); | |
563 | } | |
0b23fb36 IY |
564 | |
565 | /* size and address of each buffer */ | |
566 | writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); | |
567 | writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); | |
568 | writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); | |
569 | ||
13947f43 | 570 | #ifndef CONFIG_PHYLIB |
0b23fb36 IY |
571 | if (fec->xcv_type != SEVENWIRE) |
572 | miiphy_restart_aneg(dev); | |
13947f43 | 573 | #endif |
0b23fb36 IY |
574 | fec_open(dev); |
575 | return 0; | |
576 | } | |
577 | ||
578 | /** | |
579 | * Halt the FEC engine | |
580 | * @param[in] dev Our device to handle | |
581 | */ | |
582 | static void fec_halt(struct eth_device *dev) | |
583 | { | |
9e27e9dc | 584 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
0b23fb36 IY |
585 | int counter = 0xffff; |
586 | ||
587 | /* | |
588 | * issue graceful stop command to the FEC transmitter if necessary | |
589 | */ | |
cb17b92d | 590 | writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), |
0b23fb36 IY |
591 | &fec->eth->x_cntrl); |
592 | ||
593 | debug("eth_halt: wait for stop regs\n"); | |
594 | /* | |
595 | * wait for graceful stop to register | |
596 | */ | |
597 | while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) | |
cb17b92d | 598 | udelay(1); |
0b23fb36 IY |
599 | |
600 | /* | |
601 | * Disable SmartDMA tasks | |
602 | */ | |
603 | fec_tx_task_disable(fec); | |
604 | fec_rx_task_disable(fec); | |
605 | ||
606 | /* | |
607 | * Disable the Ethernet Controller | |
608 | * Note: this will also reset the BD index counter! | |
609 | */ | |
740d6ae5 JR |
610 | writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, |
611 | &fec->eth->ecntrl); | |
0b23fb36 IY |
612 | fec->rbd_index = 0; |
613 | fec->tbd_index = 0; | |
0b23fb36 IY |
614 | debug("eth_halt: done\n"); |
615 | } | |
616 | ||
617 | /** | |
618 | * Transmit one frame | |
619 | * @param[in] dev Our ethernet device to handle | |
620 | * @param[in] packet Pointer to the data to be transmitted | |
621 | * @param[in] length Data count in bytes | |
622 | * @return 0 on success | |
623 | */ | |
442dac4c | 624 | static int fec_send(struct eth_device *dev, void *packet, int length) |
0b23fb36 IY |
625 | { |
626 | unsigned int status; | |
efe24d2e | 627 | uint32_t size, end; |
5c1ad3e6 | 628 | uint32_t addr; |
bc1ce150 MV |
629 | int timeout = FEC_XFER_TIMEOUT; |
630 | int ret = 0; | |
0b23fb36 IY |
631 | |
632 | /* | |
633 | * This routine transmits one frame. This routine only accepts | |
634 | * 6-byte Ethernet addresses. | |
635 | */ | |
636 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
637 | ||
638 | /* | |
639 | * Check for valid length of data. | |
640 | */ | |
641 | if ((length > 1500) || (length <= 0)) { | |
4294b248 | 642 | printf("Payload (%d) too large\n", length); |
0b23fb36 IY |
643 | return -1; |
644 | } | |
645 | ||
646 | /* | |
5c1ad3e6 EN |
647 | * Setup the transmit buffer. We are always using the first buffer for |
648 | * transmission, the second will be empty and only used to stop the DMA | |
649 | * engine. We also flush the packet to RAM here to avoid cache trouble. | |
0b23fb36 | 650 | */ |
5c1ad3e6 | 651 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
652 | swap_packet((uint32_t *)packet, length); |
653 | #endif | |
5c1ad3e6 EN |
654 | |
655 | addr = (uint32_t)packet; | |
efe24d2e MV |
656 | end = roundup(addr + length, ARCH_DMA_MINALIGN); |
657 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
658 | flush_dcache_range(addr, end); | |
5c1ad3e6 | 659 | |
0b23fb36 | 660 | writew(length, &fec->tbd_base[fec->tbd_index].data_length); |
5c1ad3e6 EN |
661 | writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer); |
662 | ||
0b23fb36 IY |
663 | /* |
664 | * update BD's status now | |
665 | * This block: | |
666 | * - is always the last in a chain (means no chain) | |
667 | * - should transmitt the CRC | |
668 | * - might be the last BD in the list, so the address counter should | |
669 | * wrap (-> keep the WRAP flag) | |
670 | */ | |
671 | status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; | |
672 | status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; | |
673 | writew(status, &fec->tbd_base[fec->tbd_index].status); | |
674 | ||
5c1ad3e6 EN |
675 | /* |
676 | * Flush data cache. This code flushes both TX descriptors to RAM. | |
677 | * After this code, the descriptors will be safely in RAM and we | |
678 | * can start DMA. | |
679 | */ | |
680 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
681 | addr = (uint32_t)fec->tbd_base; | |
682 | flush_dcache_range(addr, addr + size); | |
683 | ||
ab94cd49 MV |
684 | /* |
685 | * Below we read the DMA descriptor's last four bytes back from the | |
686 | * DRAM. This is important in order to make sure that all WRITE | |
687 | * operations on the bus that were triggered by previous cache FLUSH | |
688 | * have completed. | |
689 | * | |
690 | * Otherwise, on MX28, it is possible to observe a corruption of the | |
691 | * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM | |
692 | * for the bus structure of MX28. The scenario is as follows: | |
693 | * | |
694 | * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going | |
695 | * to DRAM due to flush_dcache_range() | |
696 | * 2) ARM core writes the FEC registers via AHB_ARB2 | |
697 | * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3 | |
698 | * | |
699 | * Note that 2) does sometimes finish before 1) due to reordering of | |
700 | * WRITE accesses on the AHB bus, therefore triggering 3) before the | |
701 | * DMA descriptor is fully written into DRAM. This results in occasional | |
702 | * corruption of the DMA descriptor. | |
703 | */ | |
704 | readl(addr + size - 4); | |
705 | ||
0b23fb36 IY |
706 | /* |
707 | * Enable SmartDMA transmit task | |
708 | */ | |
709 | fec_tx_task_enable(fec); | |
710 | ||
711 | /* | |
5c1ad3e6 EN |
712 | * Wait until frame is sent. On each turn of the wait cycle, we must |
713 | * invalidate data cache to see what's really in RAM. Also, we need | |
714 | * barrier here. | |
0b23fb36 | 715 | */ |
67449098 | 716 | while (--timeout) { |
c0b5a3bb | 717 | if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR)) |
bc1ce150 | 718 | break; |
0b23fb36 | 719 | } |
5c1ad3e6 | 720 | |
f599288d | 721 | if (!timeout) { |
67449098 | 722 | ret = -EINVAL; |
f599288d FE |
723 | goto out; |
724 | } | |
725 | ||
726 | /* | |
727 | * The TDAR bit is cleared when the descriptors are all out from TX | |
728 | * but on mx6solox we noticed that the READY bit is still not cleared | |
729 | * right after TDAR. | |
730 | * These are two distinct signals, and in IC simulation, we found that | |
731 | * TDAR always gets cleared prior than the READY bit of last BD becomes | |
732 | * cleared. | |
733 | * In mx6solox, we use a later version of FEC IP. It looks like that | |
734 | * this intrinsic behaviour of TDAR bit has changed in this newer FEC | |
735 | * version. | |
736 | * | |
737 | * Fix this by polling the READY bit of BD after the TDAR polling, | |
738 | * which covers the mx6solox case and does not harm the other SoCs. | |
739 | */ | |
740 | timeout = FEC_XFER_TIMEOUT; | |
741 | while (--timeout) { | |
742 | invalidate_dcache_range(addr, addr + size); | |
743 | if (!(readw(&fec->tbd_base[fec->tbd_index].status) & | |
744 | FEC_TBD_READY)) | |
745 | break; | |
746 | } | |
67449098 | 747 | |
f599288d | 748 | if (!timeout) |
67449098 MV |
749 | ret = -EINVAL; |
750 | ||
f599288d | 751 | out: |
67449098 | 752 | debug("fec_send: status 0x%x index %d ret %i\n", |
0b23fb36 | 753 | readw(&fec->tbd_base[fec->tbd_index].status), |
67449098 | 754 | fec->tbd_index, ret); |
0b23fb36 IY |
755 | /* for next transmission use the other buffer */ |
756 | if (fec->tbd_index) | |
757 | fec->tbd_index = 0; | |
758 | else | |
759 | fec->tbd_index = 1; | |
760 | ||
bc1ce150 | 761 | return ret; |
0b23fb36 IY |
762 | } |
763 | ||
764 | /** | |
765 | * Pull one frame from the card | |
766 | * @param[in] dev Our ethernet device to handle | |
767 | * @return Length of packet read | |
768 | */ | |
769 | static int fec_recv(struct eth_device *dev) | |
770 | { | |
771 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
772 | struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; | |
773 | unsigned long ievent; | |
774 | int frame_length, len = 0; | |
0b23fb36 | 775 | uint16_t bd_status; |
efe24d2e | 776 | uint32_t addr, size, end; |
5c1ad3e6 | 777 | int i; |
fd37f195 | 778 | ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); |
0b23fb36 IY |
779 | |
780 | /* | |
781 | * Check if any critical events have happened | |
782 | */ | |
783 | ievent = readl(&fec->eth->ievent); | |
784 | writel(ievent, &fec->eth->ievent); | |
eda959f3 | 785 | debug("fec_recv: ievent 0x%lx\n", ievent); |
0b23fb36 IY |
786 | if (ievent & FEC_IEVENT_BABR) { |
787 | fec_halt(dev); | |
788 | fec_init(dev, fec->bd); | |
789 | printf("some error: 0x%08lx\n", ievent); | |
790 | return 0; | |
791 | } | |
792 | if (ievent & FEC_IEVENT_HBERR) { | |
793 | /* Heartbeat error */ | |
794 | writel(0x00000001 | readl(&fec->eth->x_cntrl), | |
795 | &fec->eth->x_cntrl); | |
796 | } | |
797 | if (ievent & FEC_IEVENT_GRA) { | |
798 | /* Graceful stop complete */ | |
799 | if (readl(&fec->eth->x_cntrl) & 0x00000001) { | |
800 | fec_halt(dev); | |
801 | writel(~0x00000001 & readl(&fec->eth->x_cntrl), | |
802 | &fec->eth->x_cntrl); | |
803 | fec_init(dev, fec->bd); | |
804 | } | |
805 | } | |
806 | ||
807 | /* | |
5c1ad3e6 EN |
808 | * Read the buffer status. Before the status can be read, the data cache |
809 | * must be invalidated, because the data in RAM might have been changed | |
810 | * by DMA. The descriptors are properly aligned to cachelines so there's | |
811 | * no need to worry they'd overlap. | |
812 | * | |
813 | * WARNING: By invalidating the descriptor here, we also invalidate | |
814 | * the descriptors surrounding this one. Therefore we can NOT change the | |
815 | * contents of this descriptor nor the surrounding ones. The problem is | |
816 | * that in order to mark the descriptor as processed, we need to change | |
817 | * the descriptor. The solution is to mark the whole cache line when all | |
818 | * descriptors in the cache line are processed. | |
0b23fb36 | 819 | */ |
5c1ad3e6 EN |
820 | addr = (uint32_t)rbd; |
821 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
822 | size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
823 | invalidate_dcache_range(addr, addr + size); | |
824 | ||
0b23fb36 IY |
825 | bd_status = readw(&rbd->status); |
826 | debug("fec_recv: status 0x%x\n", bd_status); | |
827 | ||
828 | if (!(bd_status & FEC_RBD_EMPTY)) { | |
829 | if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && | |
830 | ((readw(&rbd->data_length) - 4) > 14)) { | |
831 | /* | |
832 | * Get buffer address and size | |
833 | */ | |
b189584b | 834 | addr = readl(&rbd->data_pointer); |
0b23fb36 | 835 | frame_length = readw(&rbd->data_length) - 4; |
5c1ad3e6 EN |
836 | /* |
837 | * Invalidate data cache over the buffer | |
838 | */ | |
efe24d2e MV |
839 | end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); |
840 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
841 | invalidate_dcache_range(addr, end); | |
5c1ad3e6 | 842 | |
0b23fb36 IY |
843 | /* |
844 | * Fill the buffer and pass it to upper layers | |
845 | */ | |
5c1ad3e6 | 846 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
b189584b | 847 | swap_packet((uint32_t *)addr, frame_length); |
be7e87e2 | 848 | #endif |
b189584b | 849 | memcpy(buff, (char *)addr, frame_length); |
1fd92db8 | 850 | net_process_received_packet(buff, frame_length); |
0b23fb36 IY |
851 | len = frame_length; |
852 | } else { | |
853 | if (bd_status & FEC_RBD_ERR) | |
b189584b AA |
854 | printf("error frame: 0x%08x 0x%08x\n", |
855 | addr, bd_status); | |
0b23fb36 | 856 | } |
5c1ad3e6 | 857 | |
0b23fb36 | 858 | /* |
5c1ad3e6 EN |
859 | * Free the current buffer, restart the engine and move forward |
860 | * to the next buffer. Here we check if the whole cacheline of | |
861 | * descriptors was already processed and if so, we mark it free | |
862 | * as whole. | |
0b23fb36 | 863 | */ |
5c1ad3e6 EN |
864 | size = RXDESC_PER_CACHELINE - 1; |
865 | if ((fec->rbd_index & size) == size) { | |
866 | i = fec->rbd_index - size; | |
867 | addr = (uint32_t)&fec->rbd_base[i]; | |
868 | for (; i <= fec->rbd_index ; i++) { | |
869 | fec_rbd_clean(i == (FEC_RBD_NUM - 1), | |
870 | &fec->rbd_base[i]); | |
871 | } | |
872 | flush_dcache_range(addr, | |
873 | addr + ARCH_DMA_MINALIGN); | |
874 | } | |
875 | ||
0b23fb36 IY |
876 | fec_rx_task_enable(fec); |
877 | fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; | |
878 | } | |
879 | debug("fec_recv: stop\n"); | |
880 | ||
881 | return len; | |
882 | } | |
883 | ||
ef8e3a3b TK |
884 | static void fec_set_dev_name(char *dest, int dev_id) |
885 | { | |
886 | sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); | |
887 | } | |
888 | ||
79e5f27b MV |
889 | static int fec_alloc_descs(struct fec_priv *fec) |
890 | { | |
891 | unsigned int size; | |
892 | int i; | |
893 | uint8_t *data; | |
894 | ||
895 | /* Allocate TX descriptors. */ | |
896 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
897 | fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
898 | if (!fec->tbd_base) | |
899 | goto err_tx; | |
900 | ||
901 | /* Allocate RX descriptors. */ | |
902 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
903 | fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
904 | if (!fec->rbd_base) | |
905 | goto err_rx; | |
906 | ||
907 | memset(fec->rbd_base, 0, size); | |
908 | ||
909 | /* Allocate RX buffers. */ | |
910 | ||
911 | /* Maximum RX buffer size. */ | |
db5b7f56 | 912 | size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); |
79e5f27b | 913 | for (i = 0; i < FEC_RBD_NUM; i++) { |
db5b7f56 | 914 | data = memalign(FEC_DMA_RX_MINALIGN, size); |
79e5f27b MV |
915 | if (!data) { |
916 | printf("%s: error allocating rxbuf %d\n", __func__, i); | |
917 | goto err_ring; | |
918 | } | |
919 | ||
920 | memset(data, 0, size); | |
921 | ||
922 | fec->rbd_base[i].data_pointer = (uint32_t)data; | |
923 | fec->rbd_base[i].status = FEC_RBD_EMPTY; | |
924 | fec->rbd_base[i].data_length = 0; | |
925 | /* Flush the buffer to memory. */ | |
926 | flush_dcache_range((uint32_t)data, (uint32_t)data + size); | |
927 | } | |
928 | ||
929 | /* Mark the last RBD to close the ring. */ | |
930 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; | |
931 | ||
932 | fec->rbd_index = 0; | |
933 | fec->tbd_index = 0; | |
934 | ||
935 | return 0; | |
936 | ||
937 | err_ring: | |
938 | for (; i >= 0; i--) | |
939 | free((void *)fec->rbd_base[i].data_pointer); | |
940 | free(fec->rbd_base); | |
941 | err_rx: | |
942 | free(fec->tbd_base); | |
943 | err_tx: | |
944 | return -ENOMEM; | |
945 | } | |
946 | ||
947 | static void fec_free_descs(struct fec_priv *fec) | |
948 | { | |
949 | int i; | |
950 | ||
951 | for (i = 0; i < FEC_RBD_NUM; i++) | |
952 | free((void *)fec->rbd_base[i].data_pointer); | |
953 | free(fec->rbd_base); | |
954 | free(fec->tbd_base); | |
955 | } | |
956 | ||
fe428b90 TK |
957 | #ifdef CONFIG_PHYLIB |
958 | int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
959 | struct mii_dev *bus, struct phy_device *phydev) | |
960 | #else | |
961 | static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
962 | struct mii_dev *bus, int phy_id) | |
963 | #endif | |
0b23fb36 | 964 | { |
0b23fb36 | 965 | struct eth_device *edev; |
9e27e9dc | 966 | struct fec_priv *fec; |
0b23fb36 | 967 | unsigned char ethaddr[6]; |
e382fb48 MV |
968 | uint32_t start; |
969 | int ret = 0; | |
0b23fb36 IY |
970 | |
971 | /* create and fill edev struct */ | |
972 | edev = (struct eth_device *)malloc(sizeof(struct eth_device)); | |
973 | if (!edev) { | |
9e27e9dc | 974 | puts("fec_mxc: not enough malloc memory for eth_device\n"); |
e382fb48 MV |
975 | ret = -ENOMEM; |
976 | goto err1; | |
9e27e9dc MV |
977 | } |
978 | ||
979 | fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); | |
980 | if (!fec) { | |
981 | puts("fec_mxc: not enough malloc memory for fec_priv\n"); | |
e382fb48 MV |
982 | ret = -ENOMEM; |
983 | goto err2; | |
0b23fb36 | 984 | } |
9e27e9dc | 985 | |
de0b9576 | 986 | memset(edev, 0, sizeof(*edev)); |
9e27e9dc MV |
987 | memset(fec, 0, sizeof(*fec)); |
988 | ||
79e5f27b MV |
989 | ret = fec_alloc_descs(fec); |
990 | if (ret) | |
991 | goto err3; | |
992 | ||
0b23fb36 IY |
993 | edev->priv = fec; |
994 | edev->init = fec_init; | |
995 | edev->send = fec_send; | |
996 | edev->recv = fec_recv; | |
997 | edev->halt = fec_halt; | |
fb57ec97 | 998 | edev->write_hwaddr = fec_set_hwaddr; |
0b23fb36 | 999 | |
9e27e9dc | 1000 | fec->eth = (struct ethernet_regs *)base_addr; |
0b23fb36 IY |
1001 | fec->bd = bd; |
1002 | ||
392b8502 | 1003 | fec->xcv_type = CONFIG_FEC_XCV_TYPE; |
0b23fb36 IY |
1004 | |
1005 | /* Reset chip. */ | |
cb17b92d | 1006 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); |
e382fb48 MV |
1007 | start = get_timer(0); |
1008 | while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
1009 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
1010 | printf("FEC MXC: Timeout reseting chip\n"); | |
79e5f27b | 1011 | goto err4; |
e382fb48 | 1012 | } |
0b23fb36 | 1013 | udelay(10); |
e382fb48 | 1014 | } |
0b23fb36 | 1015 | |
a5990b26 | 1016 | fec_reg_setup(fec); |
ef8e3a3b TK |
1017 | fec_set_dev_name(edev->name, dev_id); |
1018 | fec->dev_id = (dev_id == -1) ? 0 : dev_id; | |
fe428b90 TK |
1019 | fec->bus = bus; |
1020 | fec_mii_setspeed(bus->priv); | |
1021 | #ifdef CONFIG_PHYLIB | |
1022 | fec->phydev = phydev; | |
1023 | phy_connect_dev(phydev, edev); | |
1024 | /* Configure phy */ | |
1025 | phy_config(phydev); | |
1026 | #else | |
9e27e9dc | 1027 | fec->phy_id = phy_id; |
fe428b90 TK |
1028 | #endif |
1029 | eth_register(edev); | |
1030 | ||
1031 | if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { | |
1032 | debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); | |
1033 | memcpy(edev->enetaddr, ethaddr, 6); | |
ddb636bd EN |
1034 | if (!getenv("ethaddr")) |
1035 | eth_setenv_enetaddr("ethaddr", ethaddr); | |
fe428b90 TK |
1036 | } |
1037 | return ret; | |
79e5f27b MV |
1038 | err4: |
1039 | fec_free_descs(fec); | |
fe428b90 TK |
1040 | err3: |
1041 | free(fec); | |
1042 | err2: | |
1043 | free(edev); | |
1044 | err1: | |
1045 | return ret; | |
1046 | } | |
1047 | ||
1048 | struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) | |
1049 | { | |
1050 | struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; | |
1051 | struct mii_dev *bus; | |
1052 | int ret; | |
0b23fb36 | 1053 | |
13947f43 TK |
1054 | bus = mdio_alloc(); |
1055 | if (!bus) { | |
1056 | printf("mdio_alloc failed\n"); | |
fe428b90 | 1057 | return NULL; |
13947f43 TK |
1058 | } |
1059 | bus->read = fec_phy_read; | |
1060 | bus->write = fec_phy_write; | |
fe428b90 | 1061 | bus->priv = eth; |
ef8e3a3b | 1062 | fec_set_dev_name(bus->name, dev_id); |
fe428b90 TK |
1063 | |
1064 | ret = mdio_register(bus); | |
1065 | if (ret) { | |
1066 | printf("mdio_register failed\n"); | |
1067 | free(bus); | |
1068 | return NULL; | |
1069 | } | |
1070 | fec_mii_setspeed(eth); | |
1071 | return bus; | |
1072 | } | |
1073 | ||
1074 | int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) | |
1075 | { | |
1076 | uint32_t base_mii; | |
1077 | struct mii_dev *bus = NULL; | |
1078 | #ifdef CONFIG_PHYLIB | |
1079 | struct phy_device *phydev = NULL; | |
1080 | #endif | |
1081 | int ret; | |
1082 | ||
5c1ad3e6 | 1083 | #ifdef CONFIG_MX28 |
13947f43 TK |
1084 | /* |
1085 | * The i.MX28 has two ethernet interfaces, but they are not equal. | |
1086 | * Only the first one can access the MDIO bus. | |
1087 | */ | |
fe428b90 | 1088 | base_mii = MXS_ENET0_BASE; |
13947f43 | 1089 | #else |
fe428b90 | 1090 | base_mii = addr; |
13947f43 | 1091 | #endif |
fe428b90 TK |
1092 | debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); |
1093 | bus = fec_get_miibus(base_mii, dev_id); | |
1094 | if (!bus) | |
1095 | return -ENOMEM; | |
4dc27eed | 1096 | #ifdef CONFIG_PHYLIB |
fe428b90 | 1097 | phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII); |
4dc27eed TK |
1098 | if (!phydev) { |
1099 | free(bus); | |
fe428b90 | 1100 | return -ENOMEM; |
4dc27eed | 1101 | } |
fe428b90 TK |
1102 | ret = fec_probe(bd, dev_id, addr, bus, phydev); |
1103 | #else | |
1104 | ret = fec_probe(bd, dev_id, addr, bus, phy_id); | |
4dc27eed | 1105 | #endif |
fe428b90 TK |
1106 | if (ret) { |
1107 | #ifdef CONFIG_PHYLIB | |
1108 | free(phydev); | |
1109 | #endif | |
1110 | free(bus); | |
1111 | } | |
e382fb48 | 1112 | return ret; |
eef24480 | 1113 | } |
0b23fb36 | 1114 | |
eef24480 TK |
1115 | #ifdef CONFIG_FEC_MXC_PHYADDR |
1116 | int fecmxc_initialize(bd_t *bd) | |
1117 | { | |
1118 | return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR, | |
1119 | IMX_FEC_BASE); | |
0b23fb36 | 1120 | } |
eef24480 | 1121 | #endif |
2e5f4421 | 1122 | |
13947f43 | 1123 | #ifndef CONFIG_PHYLIB |
2e5f4421 MV |
1124 | int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) |
1125 | { | |
1126 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
1127 | fec->mii_postcall = cb; | |
1128 | return 0; | |
1129 | } | |
13947f43 | 1130 | #endif |