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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
0b23fb36 IY |
2 | /* |
3 | * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> | |
4 | * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> | |
5 | * (C) Copyright 2008 Armadeus Systems nc | |
6 | * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
7 | * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> | |
0b23fb36 IY |
8 | */ |
9 | ||
d678a59d | 10 | #include <common.h> |
1eb69ae4 | 11 | #include <cpu_func.h> |
60752ca8 | 12 | #include <dm.h> |
9fb625ce | 13 | #include <env.h> |
f7ae49fc | 14 | #include <log.h> |
0b23fb36 | 15 | #include <malloc.h> |
cf92e05c | 16 | #include <memalign.h> |
567173a6 | 17 | #include <miiphy.h> |
0b23fb36 | 18 | #include <net.h> |
84f64c8b | 19 | #include <netdev.h> |
90526e9f | 20 | #include <asm/cache.h> |
401d1c4f | 21 | #include <asm/global_data.h> |
c05ed00a | 22 | #include <linux/delay.h> |
ad8c43cb | 23 | #include <power/regulator.h> |
0b23fb36 | 24 | |
0b23fb36 | 25 | #include <asm/io.h> |
1221ce45 | 26 | #include <linux/errno.h> |
e2a66e60 | 27 | #include <linux/compiler.h> |
0b23fb36 | 28 | |
567173a6 JT |
29 | #include <asm/arch/clock.h> |
30 | #include <asm/arch/imx-regs.h> | |
552a848e | 31 | #include <asm/mach-imx/sys_proto.h> |
efd0b791 | 32 | #include <asm-generic/gpio.h> |
3b8f99a3 TH |
33 | #include <dm/device_compat.h> |
34 | #include <dm/lists.h> | |
efd0b791 MT |
35 | |
36 | #include "fec_mxc.h" | |
6a895d03 | 37 | #include <eth_phy.h> |
567173a6 | 38 | |
0b23fb36 IY |
39 | DECLARE_GLOBAL_DATA_PTR; |
40 | ||
bc1ce150 MV |
41 | /* |
42 | * Timeout the transfer after 5 mS. This is usually a bit more, since | |
43 | * the code in the tightloops this timeout is used in adds some overhead. | |
44 | */ | |
45 | #define FEC_XFER_TIMEOUT 5000 | |
46 | ||
db5b7f56 FE |
47 | /* |
48 | * The standard 32-byte DMA alignment does not work on mx6solox, which requires | |
49 | * 64-byte alignment in the DMA RX FEC buffer. | |
50 | * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also | |
51 | * satisfies the alignment on other SoCs (32-bytes) | |
52 | */ | |
53 | #define FEC_DMA_RX_MINALIGN 64 | |
54 | ||
0b23fb36 IY |
55 | #ifndef CONFIG_MII |
56 | #error "CONFIG_MII has to be defined!" | |
57 | #endif | |
58 | ||
be7e87e2 MV |
59 | /* |
60 | * The i.MX28 operates with packets in big endian. We need to swap them before | |
61 | * sending and after receiving. | |
62 | */ | |
5c1ad3e6 | 63 | #ifdef CONFIG_MX28 |
6e7df1d1 | 64 | #define CFG_FEC_MXC_SWAP_PACKET |
5c1ad3e6 EN |
65 | #endif |
66 | ||
67 | #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) | |
68 | ||
69 | /* Check various alignment issues at compile time */ | |
70 | #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) | |
71 | #error "ARCH_DMA_MINALIGN must be multiple of 16!" | |
72 | #endif | |
73 | ||
74 | #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ | |
75 | (PKTALIGN % ARCH_DMA_MINALIGN != 0)) | |
76 | #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" | |
be7e87e2 MV |
77 | #endif |
78 | ||
0b23fb36 IY |
79 | #undef DEBUG |
80 | ||
6e7df1d1 | 81 | #ifdef CFG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
82 | static void swap_packet(uint32_t *packet, int length) |
83 | { | |
84 | int i; | |
85 | ||
86 | for (i = 0; i < DIV_ROUND_UP(length, 4); i++) | |
87 | packet[i] = __swab32(packet[i]); | |
88 | } | |
89 | #endif | |
90 | ||
567173a6 JT |
91 | /* MII-interface related functions */ |
92 | static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr, | |
93 | uint8_t regaddr) | |
0b23fb36 | 94 | { |
0b23fb36 IY |
95 | uint32_t reg; /* convenient holder for the PHY register */ |
96 | uint32_t phy; /* convenient holder for the PHY */ | |
97 | uint32_t start; | |
13947f43 | 98 | int val; |
0b23fb36 IY |
99 | |
100 | /* | |
101 | * reading from any PHY's register is done by properly | |
102 | * programming the FEC's MII data register. | |
103 | */ | |
d133b881 | 104 | writel(FEC_IEVENT_MII, ð->ievent); |
567173a6 JT |
105 | reg = regaddr << FEC_MII_DATA_RA_SHIFT; |
106 | phy = phyaddr << FEC_MII_DATA_PA_SHIFT; | |
0b23fb36 IY |
107 | |
108 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | | |
d133b881 | 109 | phy | reg, ð->mii_data); |
0b23fb36 | 110 | |
567173a6 | 111 | /* wait for the related interrupt */ |
a60d1e5b | 112 | start = get_timer(0); |
d133b881 | 113 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
114 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
115 | printf("Read MDIO failed...\n"); | |
116 | return -1; | |
117 | } | |
118 | } | |
119 | ||
567173a6 | 120 | /* clear mii interrupt bit */ |
d133b881 | 121 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 | 122 | |
567173a6 | 123 | /* it's now safe to read the PHY's register */ |
13947f43 | 124 | val = (unsigned short)readl(ð->mii_data); |
567173a6 JT |
125 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, |
126 | regaddr, val); | |
13947f43 | 127 | return val; |
0b23fb36 IY |
128 | } |
129 | ||
673f6597 PF |
130 | #ifndef imx_get_fecclk |
131 | u32 __weak imx_get_fecclk(void) | |
132 | { | |
133 | return 0; | |
134 | } | |
135 | #endif | |
136 | ||
58ec4d33 AG |
137 | static int fec_get_clk_rate(void *udev, int idx) |
138 | { | |
58ec4d33 AG |
139 | struct fec_priv *fec; |
140 | struct udevice *dev; | |
141 | int ret; | |
142 | ||
673f6597 PF |
143 | if (IS_ENABLED(CONFIG_IMX8) || |
144 | CONFIG_IS_ENABLED(CLK_CCF)) { | |
145 | dev = udev; | |
146 | if (!dev) { | |
b247fa7b | 147 | ret = uclass_get_device_by_seq(UCLASS_ETH, idx, &dev); |
673f6597 PF |
148 | if (ret < 0) { |
149 | debug("Can't get FEC udev: %d\n", ret); | |
150 | return ret; | |
151 | } | |
58ec4d33 | 152 | } |
58ec4d33 | 153 | |
673f6597 PF |
154 | fec = dev_get_priv(dev); |
155 | if (fec) | |
156 | return fec->clk_rate; | |
58ec4d33 | 157 | |
673f6597 PF |
158 | return -EINVAL; |
159 | } else { | |
160 | return imx_get_fecclk(); | |
161 | } | |
58ec4d33 AG |
162 | } |
163 | ||
575c5cc0 | 164 | static void fec_mii_setspeed(struct ethernet_regs *eth) |
4294b248 SB |
165 | { |
166 | /* | |
167 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock | |
168 | * and do not drop the Preamble. | |
843a3e58 MR |
169 | * |
170 | * The i.MX28 and i.MX6 types have another field in the MSCR (aka | |
171 | * MII_SPEED) register that defines the MDIO output hold time. Earlier | |
172 | * versions are RAZ there, so just ignore the difference and write the | |
173 | * register always. | |
174 | * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. | |
175 | * HOLDTIME + 1 is the number of clk cycles the fec is holding the | |
176 | * output. | |
177 | * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). | |
178 | * Given that ceil(clkrate / 5000000) <= 64, the calculation for | |
179 | * holdtime cannot result in a value greater than 3. | |
4294b248 | 180 | */ |
58ec4d33 AG |
181 | u32 pclk; |
182 | u32 speed; | |
183 | u32 hold; | |
184 | int ret; | |
185 | ||
186 | ret = fec_get_clk_rate(NULL, 0); | |
187 | if (ret < 0) { | |
188 | printf("Can't find FEC0 clk rate: %d\n", ret); | |
189 | return; | |
190 | } | |
191 | pclk = ret; | |
192 | speed = DIV_ROUND_UP(pclk, 5000000); | |
193 | hold = DIV_ROUND_UP(pclk, 100000000) - 1; | |
194 | ||
6ba45cc0 MN |
195 | #ifdef FEC_QUIRK_ENET_MAC |
196 | speed--; | |
197 | #endif | |
843a3e58 | 198 | writel(speed << 1 | hold << 8, ð->mii_speed); |
575c5cc0 | 199 | debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); |
4294b248 | 200 | } |
0b23fb36 | 201 | |
567173a6 JT |
202 | static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr, |
203 | uint8_t regaddr, uint16_t data) | |
13947f43 | 204 | { |
0b23fb36 IY |
205 | uint32_t reg; /* convenient holder for the PHY register */ |
206 | uint32_t phy; /* convenient holder for the PHY */ | |
207 | uint32_t start; | |
208 | ||
567173a6 JT |
209 | reg = regaddr << FEC_MII_DATA_RA_SHIFT; |
210 | phy = phyaddr << FEC_MII_DATA_PA_SHIFT; | |
0b23fb36 IY |
211 | |
212 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | | |
d133b881 | 213 | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); |
0b23fb36 | 214 | |
567173a6 | 215 | /* wait for the MII interrupt */ |
a60d1e5b | 216 | start = get_timer(0); |
d133b881 | 217 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
218 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
219 | printf("Write MDIO failed...\n"); | |
220 | return -1; | |
221 | } | |
222 | } | |
223 | ||
567173a6 | 224 | /* clear MII interrupt bit */ |
d133b881 | 225 | writel(FEC_IEVENT_MII, ð->ievent); |
567173a6 JT |
226 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, |
227 | regaddr, data); | |
0b23fb36 IY |
228 | |
229 | return 0; | |
230 | } | |
231 | ||
567173a6 JT |
232 | static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr, |
233 | int regaddr) | |
13947f43 | 234 | { |
567173a6 | 235 | return fec_mdio_read(bus->priv, phyaddr, regaddr); |
13947f43 TK |
236 | } |
237 | ||
567173a6 JT |
238 | static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr, |
239 | int regaddr, u16 data) | |
13947f43 | 240 | { |
567173a6 | 241 | return fec_mdio_write(bus->priv, phyaddr, regaddr, data); |
13947f43 TK |
242 | } |
243 | ||
244 | #ifndef CONFIG_PHYLIB | |
0b23fb36 IY |
245 | static int miiphy_restart_aneg(struct eth_device *dev) |
246 | { | |
b774fe9d SB |
247 | int ret = 0; |
248 | #if !defined(CONFIG_FEC_MXC_NO_ANEG) | |
9e27e9dc | 249 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 250 | struct ethernet_regs *eth = fec->bus->priv; |
9e27e9dc | 251 | |
0b23fb36 IY |
252 | /* |
253 | * Wake up from sleep if necessary | |
254 | * Reset PHY, then delay 300ns | |
255 | */ | |
13947f43 | 256 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); |
0b23fb36 IY |
257 | udelay(1000); |
258 | ||
567173a6 | 259 | /* Set the auto-negotiation advertisement register bits */ |
13947f43 | 260 | fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, |
567173a6 JT |
261 | LPA_100FULL | LPA_100HALF | LPA_10FULL | |
262 | LPA_10HALF | PHY_ANLPAR_PSB_802_3); | |
13947f43 | 263 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, |
567173a6 | 264 | BMCR_ANENABLE | BMCR_ANRESTART); |
2e5f4421 MV |
265 | |
266 | if (fec->mii_postcall) | |
267 | ret = fec->mii_postcall(fec->phy_id); | |
268 | ||
b774fe9d | 269 | #endif |
2e5f4421 | 270 | return ret; |
0b23fb36 IY |
271 | } |
272 | ||
273 | static int miiphy_wait_aneg(struct eth_device *dev) | |
274 | { | |
275 | uint32_t start; | |
13947f43 | 276 | int status; |
9e27e9dc | 277 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 278 | struct ethernet_regs *eth = fec->bus->priv; |
0b23fb36 | 279 | |
567173a6 | 280 | /* Wait for AN completion */ |
a60d1e5b | 281 | start = get_timer(0); |
0b23fb36 IY |
282 | do { |
283 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
284 | printf("%s: Autonegotiation timeout\n", dev->name); | |
285 | return -1; | |
286 | } | |
287 | ||
13947f43 TK |
288 | status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); |
289 | if (status < 0) { | |
290 | printf("%s: Autonegotiation failed. status: %d\n", | |
567173a6 | 291 | dev->name, status); |
0b23fb36 IY |
292 | return -1; |
293 | } | |
8ef583a0 | 294 | } while (!(status & BMSR_LSTATUS)); |
0b23fb36 IY |
295 | |
296 | return 0; | |
297 | } | |
13947f43 TK |
298 | #endif |
299 | ||
0b23fb36 IY |
300 | static int fec_rx_task_enable(struct fec_priv *fec) |
301 | { | |
c0b5a3bb | 302 | writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active); |
0b23fb36 IY |
303 | return 0; |
304 | } | |
305 | ||
306 | static int fec_rx_task_disable(struct fec_priv *fec) | |
307 | { | |
308 | return 0; | |
309 | } | |
310 | ||
311 | static int fec_tx_task_enable(struct fec_priv *fec) | |
312 | { | |
c0b5a3bb | 313 | writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active); |
0b23fb36 IY |
314 | return 0; |
315 | } | |
316 | ||
317 | static int fec_tx_task_disable(struct fec_priv *fec) | |
318 | { | |
319 | return 0; | |
320 | } | |
321 | ||
322 | /** | |
323 | * Initialize receive task's buffer descriptors | |
324 | * @param[in] fec all we know about the device yet | |
325 | * @param[in] count receive buffer count to be allocated | |
5c1ad3e6 | 326 | * @param[in] dsize desired size of each receive buffer |
185f812c | 327 | * Return: 0 on success |
0b23fb36 | 328 | * |
79e5f27b | 329 | * Init all RX descriptors to default values. |
0b23fb36 | 330 | */ |
79e5f27b | 331 | static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) |
0b23fb36 | 332 | { |
5c1ad3e6 | 333 | uint32_t size; |
f24e482a | 334 | ulong data; |
5c1ad3e6 EN |
335 | int i; |
336 | ||
0b23fb36 | 337 | /* |
79e5f27b MV |
338 | * Reload the RX descriptors with default values and wipe |
339 | * the RX buffers. | |
0b23fb36 | 340 | */ |
5c1ad3e6 EN |
341 | size = roundup(dsize, ARCH_DMA_MINALIGN); |
342 | for (i = 0; i < count; i++) { | |
f24e482a YL |
343 | data = fec->rbd_base[i].data_pointer; |
344 | memset((void *)data, 0, dsize); | |
345 | flush_dcache_range(data, data + size); | |
79e5f27b MV |
346 | |
347 | fec->rbd_base[i].status = FEC_RBD_EMPTY; | |
348 | fec->rbd_base[i].data_length = 0; | |
5c1ad3e6 EN |
349 | } |
350 | ||
351 | /* Mark the last RBD to close the ring. */ | |
79e5f27b | 352 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; |
0b23fb36 IY |
353 | fec->rbd_index = 0; |
354 | ||
f24e482a YL |
355 | flush_dcache_range((ulong)fec->rbd_base, |
356 | (ulong)fec->rbd_base + size); | |
0b23fb36 IY |
357 | } |
358 | ||
359 | /** | |
360 | * Initialize transmit task's buffer descriptors | |
361 | * @param[in] fec all we know about the device yet | |
362 | * | |
363 | * Transmit buffers are created externally. We only have to init the BDs here.\n | |
364 | * Note: There is a race condition in the hardware. When only one BD is in | |
365 | * use it must be marked with the WRAP bit to use it for every transmitt. | |
366 | * This bit in combination with the READY bit results into double transmit | |
367 | * of each data buffer. It seems the state machine checks READY earlier then | |
368 | * resetting it after the first transfer. | |
369 | * Using two BDs solves this issue. | |
370 | */ | |
371 | static void fec_tbd_init(struct fec_priv *fec) | |
372 | { | |
f24e482a | 373 | ulong addr = (ulong)fec->tbd_base; |
5c1ad3e6 EN |
374 | unsigned size = roundup(2 * sizeof(struct fec_bd), |
375 | ARCH_DMA_MINALIGN); | |
79e5f27b MV |
376 | |
377 | memset(fec->tbd_base, 0, size); | |
378 | fec->tbd_base[0].status = 0; | |
379 | fec->tbd_base[1].status = FEC_TBD_WRAP; | |
0b23fb36 | 380 | fec->tbd_index = 0; |
79e5f27b | 381 | flush_dcache_range(addr, addr + size); |
0b23fb36 IY |
382 | } |
383 | ||
384 | /** | |
385 | * Mark the given read buffer descriptor as free | |
386 | * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 | |
567173a6 | 387 | * @param[in] prbd buffer descriptor to mark free again |
0b23fb36 | 388 | */ |
567173a6 | 389 | static void fec_rbd_clean(int last, struct fec_bd *prbd) |
0b23fb36 | 390 | { |
5c1ad3e6 | 391 | unsigned short flags = FEC_RBD_EMPTY; |
0b23fb36 | 392 | if (last) |
5c1ad3e6 | 393 | flags |= FEC_RBD_WRAP; |
567173a6 JT |
394 | writew(flags, &prbd->status); |
395 | writew(0, &prbd->data_length); | |
0b23fb36 IY |
396 | } |
397 | ||
f54183e6 | 398 | static int fec_get_hwaddr(int dev_id, unsigned char *mac) |
0b23fb36 | 399 | { |
be252b65 | 400 | imx_get_mac_from_fuse(dev_id, mac); |
0adb5b76 | 401 | return !is_valid_ethaddr(mac); |
0b23fb36 IY |
402 | } |
403 | ||
60752ca8 | 404 | static int fecmxc_set_hwaddr(struct udevice *dev) |
0b23fb36 | 405 | { |
60752ca8 | 406 | struct fec_priv *fec = dev_get_priv(dev); |
c69cda25 | 407 | struct eth_pdata *pdata = dev_get_plat(dev); |
60752ca8 | 408 | uchar *mac = pdata->enetaddr; |
0b23fb36 IY |
409 | |
410 | writel(0, &fec->eth->iaddr1); | |
411 | writel(0, &fec->eth->iaddr2); | |
412 | writel(0, &fec->eth->gaddr1); | |
413 | writel(0, &fec->eth->gaddr2); | |
414 | ||
567173a6 | 415 | /* Set physical address */ |
0b23fb36 | 416 | writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], |
567173a6 | 417 | &fec->eth->paddr1); |
0b23fb36 IY |
418 | writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); |
419 | ||
420 | return 0; | |
421 | } | |
422 | ||
567173a6 | 423 | /* Do initial configuration of the FEC registers */ |
a5990b26 MV |
424 | static void fec_reg_setup(struct fec_priv *fec) |
425 | { | |
426 | uint32_t rcntrl; | |
427 | ||
567173a6 | 428 | /* Set interrupt mask register */ |
a5990b26 MV |
429 | writel(0x00000000, &fec->eth->imask); |
430 | ||
567173a6 | 431 | /* Clear FEC-Lite interrupt event register(IEVENT) */ |
a5990b26 MV |
432 | writel(0xffffffff, &fec->eth->ievent); |
433 | ||
567173a6 | 434 | /* Set FEC-Lite receive control register(R_CNTRL): */ |
a5990b26 MV |
435 | |
436 | /* Start with frame length = 1518, common for all modes. */ | |
437 | rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; | |
9d2d924a | 438 | if (fec->xcv_type != SEVENWIRE) /* xMII modes */ |
439 | rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; | |
440 | if (fec->xcv_type == RGMII) | |
a5990b26 MV |
441 | rcntrl |= FEC_RCNTRL_RGMII; |
442 | else if (fec->xcv_type == RMII) | |
443 | rcntrl |= FEC_RCNTRL_RMII; | |
a5990b26 | 444 | |
87550a81 TH |
445 | if (fec->promisc) |
446 | rcntrl |= 0x8; | |
447 | ||
a5990b26 MV |
448 | writel(rcntrl, &fec->eth->r_cntrl); |
449 | } | |
450 | ||
0b23fb36 IY |
451 | /** |
452 | * Start the FEC engine | |
453 | * @param[in] dev Our device to handle | |
454 | */ | |
60752ca8 | 455 | static int fec_open(struct udevice *dev) |
0b23fb36 | 456 | { |
60752ca8 | 457 | struct fec_priv *fec = dev_get_priv(dev); |
28774cba | 458 | int speed; |
f24e482a | 459 | ulong addr, size; |
5c1ad3e6 | 460 | int i; |
0b23fb36 IY |
461 | |
462 | debug("fec_open: fec_open(dev)\n"); | |
463 | /* full-duplex, heartbeat disabled */ | |
464 | writel(1 << 2, &fec->eth->x_cntrl); | |
465 | fec->rbd_index = 0; | |
466 | ||
5c1ad3e6 EN |
467 | /* Invalidate all descriptors */ |
468 | for (i = 0; i < FEC_RBD_NUM - 1; i++) | |
469 | fec_rbd_clean(0, &fec->rbd_base[i]); | |
470 | fec_rbd_clean(1, &fec->rbd_base[i]); | |
471 | ||
472 | /* Flush the descriptors into RAM */ | |
473 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
474 | ARCH_DMA_MINALIGN); | |
f24e482a | 475 | addr = (ulong)fec->rbd_base; |
5c1ad3e6 EN |
476 | flush_dcache_range(addr, addr + size); |
477 | ||
28774cba | 478 | #ifdef FEC_QUIRK_ENET_MAC |
2ef2b950 JL |
479 | /* Enable ENET HW endian SWAP */ |
480 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, | |
567173a6 | 481 | &fec->eth->ecntrl); |
2ef2b950 JL |
482 | /* Enable ENET store and forward mode */ |
483 | writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, | |
567173a6 | 484 | &fec->eth->x_wmrk); |
2ef2b950 | 485 | #endif |
567173a6 | 486 | /* Enable FEC-Lite controller */ |
cb17b92d | 487 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, |
567173a6 JT |
488 | &fec->eth->ecntrl); |
489 | ||
a1a34fae PS |
490 | #ifdef FEC_ENET_ENABLE_TXC_DELAY |
491 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_TXC_DLY, | |
492 | &fec->eth->ecntrl); | |
493 | #endif | |
494 | ||
495 | #ifdef FEC_ENET_ENABLE_RXC_DELAY | |
496 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RXC_DLY, | |
497 | &fec->eth->ecntrl); | |
498 | #endif | |
499 | ||
8ba59608 | 500 | #if defined(CONFIG_MX53) || defined(CONFIG_MX6SL) |
740d6ae5 | 501 | udelay(100); |
740d6ae5 | 502 | |
567173a6 | 503 | /* setup the MII gasket for RMII mode */ |
740d6ae5 JR |
504 | /* disable the gasket */ |
505 | writew(0, &fec->eth->miigsk_enr); | |
506 | ||
507 | /* wait for the gasket to be disabled */ | |
508 | while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) | |
509 | udelay(2); | |
510 | ||
511 | /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ | |
512 | writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); | |
513 | ||
514 | /* re-enable the gasket */ | |
515 | writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); | |
516 | ||
517 | /* wait until MII gasket is ready */ | |
518 | int max_loops = 10; | |
519 | while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { | |
520 | if (--max_loops <= 0) { | |
521 | printf("WAIT for MII Gasket ready timed out\n"); | |
522 | break; | |
523 | } | |
524 | } | |
525 | #endif | |
0b23fb36 | 526 | |
13947f43 | 527 | #ifdef CONFIG_PHYLIB |
4dc27eed | 528 | { |
13947f43 | 529 | /* Start up the PHY */ |
11af8d65 TT |
530 | int ret = phy_startup(fec->phydev); |
531 | ||
532 | if (ret) { | |
533 | printf("Could not initialize PHY %s\n", | |
534 | fec->phydev->dev->name); | |
535 | return ret; | |
536 | } | |
13947f43 | 537 | speed = fec->phydev->speed; |
13947f43 TK |
538 | } |
539 | #else | |
0b23fb36 | 540 | miiphy_wait_aneg(edev); |
28774cba | 541 | speed = miiphy_speed(edev->name, fec->phy_id); |
9e27e9dc | 542 | miiphy_duplex(edev->name, fec->phy_id); |
13947f43 | 543 | #endif |
0b23fb36 | 544 | |
28774cba TK |
545 | #ifdef FEC_QUIRK_ENET_MAC |
546 | { | |
547 | u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; | |
bcb6e902 | 548 | u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; |
28774cba TK |
549 | if (speed == _1000BASET) |
550 | ecr |= FEC_ECNTRL_SPEED; | |
551 | else if (speed != _100BASET) | |
552 | rcr |= FEC_RCNTRL_RMII_10T; | |
553 | writel(ecr, &fec->eth->ecntrl); | |
554 | writel(rcr, &fec->eth->r_cntrl); | |
555 | } | |
556 | #endif | |
557 | debug("%s:Speed=%i\n", __func__, speed); | |
558 | ||
567173a6 | 559 | /* Enable SmartDMA receive task */ |
0b23fb36 IY |
560 | fec_rx_task_enable(fec); |
561 | ||
562 | udelay(100000); | |
563 | return 0; | |
564 | } | |
565 | ||
60752ca8 | 566 | static int fecmxc_init(struct udevice *dev) |
0b23fb36 | 567 | { |
60752ca8 | 568 | struct fec_priv *fec = dev_get_priv(dev); |
f24e482a YL |
569 | u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop; |
570 | u8 *i; | |
571 | ulong addr; | |
0b23fb36 | 572 | |
e9319f11 | 573 | /* Initialize MAC address */ |
60752ca8 | 574 | fecmxc_set_hwaddr(dev); |
e9319f11 | 575 | |
567173a6 | 576 | /* Setup transmit descriptors, there are two in total. */ |
79e5f27b | 577 | fec_tbd_init(fec); |
0b23fb36 | 578 | |
79e5f27b MV |
579 | /* Setup receive descriptors. */ |
580 | fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); | |
0b23fb36 | 581 | |
a5990b26 | 582 | fec_reg_setup(fec); |
9eb3770b | 583 | |
f41471e6 | 584 | if (fec->xcv_type != SEVENWIRE) |
575c5cc0 | 585 | fec_mii_setspeed(fec->bus->priv); |
9eb3770b | 586 | |
567173a6 | 587 | /* Set Opcode/Pause Duration Register */ |
0b23fb36 IY |
588 | writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ |
589 | writel(0x2, &fec->eth->x_wmrk); | |
567173a6 JT |
590 | |
591 | /* Set multicast address filter */ | |
0b23fb36 IY |
592 | writel(0x00000000, &fec->eth->gaddr1); |
593 | writel(0x00000000, &fec->eth->gaddr2); | |
594 | ||
238a53c7 | 595 | /* Do not access reserved register */ |
09de565f PF |
596 | if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp() && |
597 | !is_imx93()) { | |
fbecbaa1 PF |
598 | /* clear MIB RAM */ |
599 | for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) | |
600 | writel(0, i); | |
0b23fb36 | 601 | |
fbecbaa1 PF |
602 | /* FIFO receive start register */ |
603 | writel(0x520, &fec->eth->r_fstart); | |
604 | } | |
0b23fb36 IY |
605 | |
606 | /* size and address of each buffer */ | |
607 | writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); | |
f24e482a YL |
608 | |
609 | addr = (ulong)fec->tbd_base; | |
610 | writel((uint32_t)addr, &fec->eth->etdsr); | |
611 | ||
612 | addr = (ulong)fec->rbd_base; | |
613 | writel((uint32_t)addr, &fec->eth->erdsr); | |
0b23fb36 | 614 | |
13947f43 | 615 | #ifndef CONFIG_PHYLIB |
0b23fb36 IY |
616 | if (fec->xcv_type != SEVENWIRE) |
617 | miiphy_restart_aneg(dev); | |
13947f43 | 618 | #endif |
0b23fb36 IY |
619 | fec_open(dev); |
620 | return 0; | |
621 | } | |
622 | ||
623 | /** | |
624 | * Halt the FEC engine | |
625 | * @param[in] dev Our device to handle | |
626 | */ | |
60752ca8 | 627 | static void fecmxc_halt(struct udevice *dev) |
0b23fb36 | 628 | { |
60752ca8 | 629 | struct fec_priv *fec = dev_get_priv(dev); |
0b23fb36 IY |
630 | int counter = 0xffff; |
631 | ||
567173a6 | 632 | /* issue graceful stop command to the FEC transmitter if necessary */ |
cb17b92d | 633 | writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), |
567173a6 | 634 | &fec->eth->x_cntrl); |
0b23fb36 IY |
635 | |
636 | debug("eth_halt: wait for stop regs\n"); | |
567173a6 | 637 | /* wait for graceful stop to register */ |
0b23fb36 | 638 | while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) |
cb17b92d | 639 | udelay(1); |
0b23fb36 | 640 | |
567173a6 | 641 | /* Disable SmartDMA tasks */ |
0b23fb36 IY |
642 | fec_tx_task_disable(fec); |
643 | fec_rx_task_disable(fec); | |
644 | ||
645 | /* | |
646 | * Disable the Ethernet Controller | |
647 | * Note: this will also reset the BD index counter! | |
648 | */ | |
740d6ae5 | 649 | writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, |
567173a6 | 650 | &fec->eth->ecntrl); |
0b23fb36 IY |
651 | fec->rbd_index = 0; |
652 | fec->tbd_index = 0; | |
0b23fb36 IY |
653 | debug("eth_halt: done\n"); |
654 | } | |
655 | ||
656 | /** | |
657 | * Transmit one frame | |
658 | * @param[in] dev Our ethernet device to handle | |
659 | * @param[in] packet Pointer to the data to be transmitted | |
660 | * @param[in] length Data count in bytes | |
185f812c | 661 | * Return: 0 on success |
0b23fb36 | 662 | */ |
60752ca8 | 663 | static int fecmxc_send(struct udevice *dev, void *packet, int length) |
0b23fb36 IY |
664 | { |
665 | unsigned int status; | |
f24e482a YL |
666 | u32 size; |
667 | ulong addr, end; | |
bc1ce150 MV |
668 | int timeout = FEC_XFER_TIMEOUT; |
669 | int ret = 0; | |
0b23fb36 IY |
670 | |
671 | /* | |
672 | * This routine transmits one frame. This routine only accepts | |
673 | * 6-byte Ethernet addresses. | |
674 | */ | |
60752ca8 | 675 | struct fec_priv *fec = dev_get_priv(dev); |
0b23fb36 IY |
676 | |
677 | /* | |
678 | * Check for valid length of data. | |
679 | */ | |
680 | if ((length > 1500) || (length <= 0)) { | |
4294b248 | 681 | printf("Payload (%d) too large\n", length); |
0b23fb36 IY |
682 | return -1; |
683 | } | |
684 | ||
685 | /* | |
5c1ad3e6 EN |
686 | * Setup the transmit buffer. We are always using the first buffer for |
687 | * transmission, the second will be empty and only used to stop the DMA | |
688 | * engine. We also flush the packet to RAM here to avoid cache trouble. | |
0b23fb36 | 689 | */ |
6e7df1d1 | 690 | #ifdef CFG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
691 | swap_packet((uint32_t *)packet, length); |
692 | #endif | |
5c1ad3e6 | 693 | |
f24e482a | 694 | addr = (ulong)packet; |
efe24d2e MV |
695 | end = roundup(addr + length, ARCH_DMA_MINALIGN); |
696 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
697 | flush_dcache_range(addr, end); | |
5c1ad3e6 | 698 | |
0b23fb36 | 699 | writew(length, &fec->tbd_base[fec->tbd_index].data_length); |
f24e482a | 700 | writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer); |
5c1ad3e6 | 701 | |
0b23fb36 IY |
702 | /* |
703 | * update BD's status now | |
704 | * This block: | |
705 | * - is always the last in a chain (means no chain) | |
706 | * - should transmitt the CRC | |
707 | * - might be the last BD in the list, so the address counter should | |
708 | * wrap (-> keep the WRAP flag) | |
709 | */ | |
710 | status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; | |
711 | status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; | |
712 | writew(status, &fec->tbd_base[fec->tbd_index].status); | |
713 | ||
5c1ad3e6 EN |
714 | /* |
715 | * Flush data cache. This code flushes both TX descriptors to RAM. | |
716 | * After this code, the descriptors will be safely in RAM and we | |
717 | * can start DMA. | |
718 | */ | |
719 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
f24e482a | 720 | addr = (ulong)fec->tbd_base; |
5c1ad3e6 EN |
721 | flush_dcache_range(addr, addr + size); |
722 | ||
ab94cd49 MV |
723 | /* |
724 | * Below we read the DMA descriptor's last four bytes back from the | |
725 | * DRAM. This is important in order to make sure that all WRITE | |
726 | * operations on the bus that were triggered by previous cache FLUSH | |
727 | * have completed. | |
728 | * | |
729 | * Otherwise, on MX28, it is possible to observe a corruption of the | |
730 | * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM | |
731 | * for the bus structure of MX28. The scenario is as follows: | |
732 | * | |
733 | * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going | |
734 | * to DRAM due to flush_dcache_range() | |
735 | * 2) ARM core writes the FEC registers via AHB_ARB2 | |
736 | * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3 | |
737 | * | |
738 | * Note that 2) does sometimes finish before 1) due to reordering of | |
739 | * WRITE accesses on the AHB bus, therefore triggering 3) before the | |
740 | * DMA descriptor is fully written into DRAM. This results in occasional | |
741 | * corruption of the DMA descriptor. | |
742 | */ | |
743 | readl(addr + size - 4); | |
744 | ||
567173a6 | 745 | /* Enable SmartDMA transmit task */ |
0b23fb36 IY |
746 | fec_tx_task_enable(fec); |
747 | ||
748 | /* | |
5c1ad3e6 EN |
749 | * Wait until frame is sent. On each turn of the wait cycle, we must |
750 | * invalidate data cache to see what's really in RAM. Also, we need | |
751 | * barrier here. | |
0b23fb36 | 752 | */ |
67449098 | 753 | while (--timeout) { |
c0b5a3bb | 754 | if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR)) |
bc1ce150 | 755 | break; |
0b23fb36 | 756 | } |
5c1ad3e6 | 757 | |
f599288d | 758 | if (!timeout) { |
67449098 | 759 | ret = -EINVAL; |
f599288d FE |
760 | goto out; |
761 | } | |
762 | ||
763 | /* | |
764 | * The TDAR bit is cleared when the descriptors are all out from TX | |
765 | * but on mx6solox we noticed that the READY bit is still not cleared | |
766 | * right after TDAR. | |
767 | * These are two distinct signals, and in IC simulation, we found that | |
768 | * TDAR always gets cleared prior than the READY bit of last BD becomes | |
769 | * cleared. | |
770 | * In mx6solox, we use a later version of FEC IP. It looks like that | |
771 | * this intrinsic behaviour of TDAR bit has changed in this newer FEC | |
772 | * version. | |
773 | * | |
774 | * Fix this by polling the READY bit of BD after the TDAR polling, | |
775 | * which covers the mx6solox case and does not harm the other SoCs. | |
776 | */ | |
777 | timeout = FEC_XFER_TIMEOUT; | |
778 | while (--timeout) { | |
779 | invalidate_dcache_range(addr, addr + size); | |
780 | if (!(readw(&fec->tbd_base[fec->tbd_index].status) & | |
781 | FEC_TBD_READY)) | |
782 | break; | |
783 | } | |
67449098 | 784 | |
f599288d | 785 | if (!timeout) |
67449098 MV |
786 | ret = -EINVAL; |
787 | ||
f599288d | 788 | out: |
67449098 | 789 | debug("fec_send: status 0x%x index %d ret %i\n", |
567173a6 JT |
790 | readw(&fec->tbd_base[fec->tbd_index].status), |
791 | fec->tbd_index, ret); | |
0b23fb36 IY |
792 | /* for next transmission use the other buffer */ |
793 | if (fec->tbd_index) | |
794 | fec->tbd_index = 0; | |
795 | else | |
796 | fec->tbd_index = 1; | |
797 | ||
bc1ce150 | 798 | return ret; |
0b23fb36 IY |
799 | } |
800 | ||
801 | /** | |
802 | * Pull one frame from the card | |
803 | * @param[in] dev Our ethernet device to handle | |
185f812c | 804 | * Return: Length of packet read |
0b23fb36 | 805 | */ |
60752ca8 | 806 | static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp) |
0b23fb36 | 807 | { |
60752ca8 | 808 | struct fec_priv *fec = dev_get_priv(dev); |
0b23fb36 IY |
809 | struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; |
810 | unsigned long ievent; | |
811 | int frame_length, len = 0; | |
0b23fb36 | 812 | uint16_t bd_status; |
f24e482a | 813 | ulong addr, size, end; |
5c1ad3e6 | 814 | int i; |
07763ac9 | 815 | |
07763ac9 YL |
816 | *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE); |
817 | if (*packetp == 0) { | |
818 | printf("%s: error allocating packetp\n", __func__); | |
819 | return -ENOMEM; | |
820 | } | |
0b23fb36 | 821 | |
567173a6 | 822 | /* Check if any critical events have happened */ |
0b23fb36 IY |
823 | ievent = readl(&fec->eth->ievent); |
824 | writel(ievent, &fec->eth->ievent); | |
eda959f3 | 825 | debug("fec_recv: ievent 0x%lx\n", ievent); |
0b23fb36 | 826 | if (ievent & FEC_IEVENT_BABR) { |
60752ca8 JT |
827 | fecmxc_halt(dev); |
828 | fecmxc_init(dev); | |
0b23fb36 IY |
829 | printf("some error: 0x%08lx\n", ievent); |
830 | return 0; | |
831 | } | |
832 | if (ievent & FEC_IEVENT_HBERR) { | |
833 | /* Heartbeat error */ | |
834 | writel(0x00000001 | readl(&fec->eth->x_cntrl), | |
567173a6 | 835 | &fec->eth->x_cntrl); |
0b23fb36 IY |
836 | } |
837 | if (ievent & FEC_IEVENT_GRA) { | |
838 | /* Graceful stop complete */ | |
839 | if (readl(&fec->eth->x_cntrl) & 0x00000001) { | |
60752ca8 | 840 | fecmxc_halt(dev); |
0b23fb36 | 841 | writel(~0x00000001 & readl(&fec->eth->x_cntrl), |
567173a6 | 842 | &fec->eth->x_cntrl); |
60752ca8 | 843 | fecmxc_init(dev); |
0b23fb36 IY |
844 | } |
845 | } | |
846 | ||
847 | /* | |
5c1ad3e6 EN |
848 | * Read the buffer status. Before the status can be read, the data cache |
849 | * must be invalidated, because the data in RAM might have been changed | |
850 | * by DMA. The descriptors are properly aligned to cachelines so there's | |
851 | * no need to worry they'd overlap. | |
852 | * | |
853 | * WARNING: By invalidating the descriptor here, we also invalidate | |
854 | * the descriptors surrounding this one. Therefore we can NOT change the | |
855 | * contents of this descriptor nor the surrounding ones. The problem is | |
856 | * that in order to mark the descriptor as processed, we need to change | |
857 | * the descriptor. The solution is to mark the whole cache line when all | |
858 | * descriptors in the cache line are processed. | |
0b23fb36 | 859 | */ |
f24e482a | 860 | addr = (ulong)rbd; |
5c1ad3e6 EN |
861 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
862 | size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
863 | invalidate_dcache_range(addr, addr + size); | |
864 | ||
0b23fb36 IY |
865 | bd_status = readw(&rbd->status); |
866 | debug("fec_recv: status 0x%x\n", bd_status); | |
867 | ||
868 | if (!(bd_status & FEC_RBD_EMPTY)) { | |
869 | if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && | |
567173a6 JT |
870 | ((readw(&rbd->data_length) - 4) > 14)) { |
871 | /* Get buffer address and size */ | |
b189584b | 872 | addr = readl(&rbd->data_pointer); |
0b23fb36 | 873 | frame_length = readw(&rbd->data_length) - 4; |
567173a6 | 874 | /* Invalidate data cache over the buffer */ |
efe24d2e MV |
875 | end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); |
876 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
877 | invalidate_dcache_range(addr, end); | |
5c1ad3e6 | 878 | |
567173a6 | 879 | /* Fill the buffer and pass it to upper layers */ |
6e7df1d1 | 880 | #ifdef CFG_FEC_MXC_SWAP_PACKET |
b189584b | 881 | swap_packet((uint32_t *)addr, frame_length); |
be7e87e2 | 882 | #endif |
07763ac9 | 883 | |
07763ac9 | 884 | memcpy(*packetp, (char *)addr, frame_length); |
0b23fb36 IY |
885 | len = frame_length; |
886 | } else { | |
887 | if (bd_status & FEC_RBD_ERR) | |
f24e482a YL |
888 | debug("error frame: 0x%08lx 0x%08x\n", |
889 | addr, bd_status); | |
0b23fb36 | 890 | } |
5c1ad3e6 | 891 | |
0b23fb36 | 892 | /* |
5c1ad3e6 EN |
893 | * Free the current buffer, restart the engine and move forward |
894 | * to the next buffer. Here we check if the whole cacheline of | |
895 | * descriptors was already processed and if so, we mark it free | |
896 | * as whole. | |
0b23fb36 | 897 | */ |
5c1ad3e6 EN |
898 | size = RXDESC_PER_CACHELINE - 1; |
899 | if ((fec->rbd_index & size) == size) { | |
900 | i = fec->rbd_index - size; | |
f24e482a | 901 | addr = (ulong)&fec->rbd_base[i]; |
5c1ad3e6 EN |
902 | for (; i <= fec->rbd_index ; i++) { |
903 | fec_rbd_clean(i == (FEC_RBD_NUM - 1), | |
904 | &fec->rbd_base[i]); | |
905 | } | |
906 | flush_dcache_range(addr, | |
567173a6 | 907 | addr + ARCH_DMA_MINALIGN); |
5c1ad3e6 EN |
908 | } |
909 | ||
0b23fb36 IY |
910 | fec_rx_task_enable(fec); |
911 | fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; | |
912 | } | |
913 | debug("fec_recv: stop\n"); | |
914 | ||
915 | return len; | |
916 | } | |
917 | ||
ef8e3a3b TK |
918 | static void fec_set_dev_name(char *dest, int dev_id) |
919 | { | |
920 | sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); | |
921 | } | |
922 | ||
79e5f27b MV |
923 | static int fec_alloc_descs(struct fec_priv *fec) |
924 | { | |
925 | unsigned int size; | |
926 | int i; | |
927 | uint8_t *data; | |
f24e482a | 928 | ulong addr; |
79e5f27b MV |
929 | |
930 | /* Allocate TX descriptors. */ | |
931 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
932 | fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
933 | if (!fec->tbd_base) | |
934 | goto err_tx; | |
935 | ||
936 | /* Allocate RX descriptors. */ | |
937 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
938 | fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
939 | if (!fec->rbd_base) | |
940 | goto err_rx; | |
941 | ||
942 | memset(fec->rbd_base, 0, size); | |
943 | ||
944 | /* Allocate RX buffers. */ | |
945 | ||
946 | /* Maximum RX buffer size. */ | |
db5b7f56 | 947 | size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); |
79e5f27b | 948 | for (i = 0; i < FEC_RBD_NUM; i++) { |
db5b7f56 | 949 | data = memalign(FEC_DMA_RX_MINALIGN, size); |
79e5f27b MV |
950 | if (!data) { |
951 | printf("%s: error allocating rxbuf %d\n", __func__, i); | |
952 | goto err_ring; | |
953 | } | |
954 | ||
955 | memset(data, 0, size); | |
956 | ||
f24e482a YL |
957 | addr = (ulong)data; |
958 | fec->rbd_base[i].data_pointer = (uint32_t)addr; | |
79e5f27b MV |
959 | fec->rbd_base[i].status = FEC_RBD_EMPTY; |
960 | fec->rbd_base[i].data_length = 0; | |
961 | /* Flush the buffer to memory. */ | |
f24e482a | 962 | flush_dcache_range(addr, addr + size); |
79e5f27b MV |
963 | } |
964 | ||
965 | /* Mark the last RBD to close the ring. */ | |
966 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; | |
967 | ||
968 | fec->rbd_index = 0; | |
969 | fec->tbd_index = 0; | |
970 | ||
971 | return 0; | |
972 | ||
973 | err_ring: | |
f24e482a YL |
974 | for (; i >= 0; i--) { |
975 | addr = fec->rbd_base[i].data_pointer; | |
976 | free((void *)addr); | |
977 | } | |
79e5f27b MV |
978 | free(fec->rbd_base); |
979 | err_rx: | |
980 | free(fec->tbd_base); | |
981 | err_tx: | |
982 | return -ENOMEM; | |
983 | } | |
984 | ||
985 | static void fec_free_descs(struct fec_priv *fec) | |
986 | { | |
987 | int i; | |
f24e482a | 988 | ulong addr; |
79e5f27b | 989 | |
f24e482a YL |
990 | for (i = 0; i < FEC_RBD_NUM; i++) { |
991 | addr = fec->rbd_base[i].data_pointer; | |
992 | free((void *)addr); | |
993 | } | |
79e5f27b MV |
994 | free(fec->rbd_base); |
995 | free(fec->tbd_base); | |
996 | } | |
997 | ||
1bcabd79 | 998 | struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) |
60752ca8 | 999 | { |
1bcabd79 | 1000 | struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; |
60752ca8 JT |
1001 | struct mii_dev *bus; |
1002 | int ret; | |
1003 | ||
1004 | bus = mdio_alloc(); | |
1005 | if (!bus) { | |
1006 | printf("mdio_alloc failed\n"); | |
1007 | return NULL; | |
1008 | } | |
1009 | bus->read = fec_phy_read; | |
1010 | bus->write = fec_phy_write; | |
1011 | bus->priv = eth; | |
1012 | fec_set_dev_name(bus->name, dev_id); | |
1013 | ||
1014 | ret = mdio_register(bus); | |
1015 | if (ret) { | |
1016 | printf("mdio_register failed\n"); | |
1017 | free(bus); | |
1018 | return NULL; | |
1019 | } | |
1020 | fec_mii_setspeed(eth); | |
1021 | return bus; | |
1022 | } | |
1023 | ||
3b8f99a3 TH |
1024 | #ifdef CONFIG_DM_MDIO |
1025 | struct dm_fec_mdio_priv { | |
1026 | struct ethernet_regs *regs; | |
1027 | }; | |
1028 | ||
1029 | static int dm_fec_mdio_read(struct udevice *dev, int addr, int devad, int reg) | |
1030 | { | |
1031 | struct dm_fec_mdio_priv *priv = dev_get_priv(dev); | |
1032 | ||
1033 | return fec_mdio_read(priv->regs, addr, reg); | |
1034 | } | |
1035 | ||
1036 | static int dm_fec_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 data) | |
1037 | { | |
1038 | struct dm_fec_mdio_priv *priv = dev_get_priv(dev); | |
1039 | ||
1040 | return fec_mdio_write(priv->regs, addr, reg, data); | |
1041 | } | |
1042 | ||
1043 | static const struct mdio_ops dm_fec_mdio_ops = { | |
1044 | .read = dm_fec_mdio_read, | |
1045 | .write = dm_fec_mdio_write, | |
1046 | }; | |
1047 | ||
1048 | static int dm_fec_mdio_probe(struct udevice *dev) | |
1049 | { | |
1050 | struct dm_fec_mdio_priv *priv = dev_get_priv(dev); | |
1051 | ||
1052 | priv->regs = (struct ethernet_regs *)ofnode_get_addr(dev_ofnode(dev->parent)); | |
1053 | ||
1054 | return 0; | |
1055 | } | |
1056 | ||
1057 | U_BOOT_DRIVER(fec_mdio) = { | |
1058 | .name = "fec_mdio", | |
1059 | .id = UCLASS_MDIO, | |
1060 | .probe = dm_fec_mdio_probe, | |
1061 | .ops = &dm_fec_mdio_ops, | |
1062 | .priv_auto = sizeof(struct dm_fec_mdio_priv), | |
1063 | }; | |
1064 | ||
1065 | static int dm_fec_bind_mdio(struct udevice *dev) | |
1066 | { | |
1067 | struct udevice *mdiodev; | |
1068 | const char *name; | |
1069 | ofnode mdio; | |
1070 | int ret = -ENODEV; | |
1071 | ||
1072 | /* for a UCLASS_MDIO driver we need to bind and probe manually | |
1073 | * for an internal MDIO bus that has no dt compatible of its own | |
1074 | */ | |
1075 | ofnode_for_each_subnode(mdio, dev_ofnode(dev)) { | |
1076 | name = ofnode_get_name(mdio); | |
1077 | ||
1078 | if (strcmp(name, "mdio")) | |
1079 | continue; | |
1080 | ||
1081 | ret = device_bind_driver_to_node(dev, "fec_mdio", | |
1082 | name, mdio, &mdiodev); | |
1083 | if (ret) { | |
1084 | printf("%s bind %s failed: %d\n", __func__, name, ret); | |
1085 | break; | |
1086 | } | |
1087 | ||
1088 | /* need to probe it as there is no compatible to do so */ | |
1089 | ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdiodev); | |
1090 | if (!ret) | |
1091 | return 0; | |
1092 | printf("%s probe %s failed: %d\n", __func__, name, ret); | |
1093 | } | |
1094 | ||
1095 | return ret; | |
1096 | } | |
1097 | #endif | |
1098 | ||
1ed2570f JT |
1099 | static int fecmxc_read_rom_hwaddr(struct udevice *dev) |
1100 | { | |
1101 | struct fec_priv *priv = dev_get_priv(dev); | |
c69cda25 | 1102 | struct eth_pdata *pdata = dev_get_plat(dev); |
1ed2570f JT |
1103 | |
1104 | return fec_get_hwaddr(priv->dev_id, pdata->enetaddr); | |
1105 | } | |
1106 | ||
87550a81 TH |
1107 | static int fecmxc_set_promisc(struct udevice *dev, bool enable) |
1108 | { | |
1109 | struct fec_priv *priv = dev_get_priv(dev); | |
1110 | ||
1111 | priv->promisc = enable; | |
1112 | ||
1113 | return 0; | |
1114 | } | |
1115 | ||
07763ac9 YL |
1116 | static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length) |
1117 | { | |
1118 | if (packet) | |
1119 | free(packet); | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
60752ca8 JT |
1124 | static const struct eth_ops fecmxc_ops = { |
1125 | .start = fecmxc_init, | |
1126 | .send = fecmxc_send, | |
1127 | .recv = fecmxc_recv, | |
07763ac9 | 1128 | .free_pkt = fecmxc_free_pkt, |
60752ca8 JT |
1129 | .stop = fecmxc_halt, |
1130 | .write_hwaddr = fecmxc_set_hwaddr, | |
1ed2570f | 1131 | .read_rom_hwaddr = fecmxc_read_rom_hwaddr, |
87550a81 | 1132 | .set_promisc = fecmxc_set_promisc, |
60752ca8 JT |
1133 | }; |
1134 | ||
89b5bd54 | 1135 | static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev) |
774ec60b MW |
1136 | { |
1137 | struct ofnode_phandle_args phandle_args; | |
eccd1329 | 1138 | int reg, ret; |
774ec60b | 1139 | |
eccd1329 SA |
1140 | ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, |
1141 | &phandle_args); | |
1142 | if (ret) { | |
69c81d65 TH |
1143 | priv->phy_of_node = ofnode_find_subnode(dev_ofnode(dev), |
1144 | "fixed-link"); | |
1145 | if (ofnode_valid(priv->phy_of_node)) | |
1146 | return 0; | |
1147 | debug("Failed to find phy-handle (err = %d)\n", ret); | |
eccd1329 | 1148 | return ret; |
774ec60b MW |
1149 | } |
1150 | ||
89090661 | 1151 | if (!ofnode_is_enabled(phandle_args.node)) |
eccd1329 | 1152 | return -ENOENT; |
89b5bd54 | 1153 | |
eccd1329 | 1154 | priv->phy_of_node = phandle_args.node; |
774ec60b MW |
1155 | reg = ofnode_read_u32_default(phandle_args.node, "reg", 0); |
1156 | ||
1157 | return reg; | |
1158 | } | |
1159 | ||
60752ca8 JT |
1160 | static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) |
1161 | { | |
3b8f99a3 | 1162 | struct phy_device *phydev = NULL; |
774ec60b | 1163 | int addr; |
60752ca8 | 1164 | |
89b5bd54 | 1165 | addr = device_get_phy_addr(priv, dev); |
fa760c32 TR |
1166 | #ifdef CFG_FEC_MXC_PHYADDR |
1167 | addr = CFG_FEC_MXC_PHYADDR; | |
60752ca8 JT |
1168 | #endif |
1169 | ||
3b8f99a3 TH |
1170 | if (IS_ENABLED(CONFIG_DM_MDIO)) |
1171 | phydev = dm_eth_phy_connect(dev); | |
1172 | if (!phydev) | |
1173 | phydev = phy_connect(priv->bus, addr, dev, priv->interface); | |
60752ca8 JT |
1174 | if (!phydev) |
1175 | return -ENODEV; | |
1176 | ||
60752ca8 | 1177 | priv->phydev = phydev; |
89b5bd54 | 1178 | priv->phydev->node = priv->phy_of_node; |
60752ca8 JT |
1179 | phy_config(phydev); |
1180 | ||
1181 | return 0; | |
1182 | } | |
1183 | ||
bcee8d67 | 1184 | #if CONFIG_IS_ENABLED(DM_GPIO) |
efd0b791 MT |
1185 | /* FEC GPIO reset */ |
1186 | static void fec_gpio_reset(struct fec_priv *priv) | |
1187 | { | |
1188 | debug("fec_gpio_reset: fec_gpio_reset(dev)\n"); | |
1189 | if (dm_gpio_is_valid(&priv->phy_reset_gpio)) { | |
1190 | dm_gpio_set_value(&priv->phy_reset_gpio, 1); | |
9b8b9188 | 1191 | mdelay(priv->reset_delay); |
efd0b791 | 1192 | dm_gpio_set_value(&priv->phy_reset_gpio, 0); |
31d4045d AC |
1193 | if (priv->reset_post_delay) |
1194 | mdelay(priv->reset_post_delay); | |
efd0b791 MT |
1195 | } |
1196 | } | |
1197 | #endif | |
1198 | ||
80a34e40 MV |
1199 | static int fecmxc_set_ref_clk(struct clk *clk_ref, phy_interface_t interface) |
1200 | { | |
1201 | unsigned int freq; | |
1202 | int ret; | |
1203 | ||
1204 | if (!CONFIG_IS_ENABLED(CLK_CCF)) | |
1205 | return 0; | |
1206 | ||
1207 | if (interface == PHY_INTERFACE_MODE_MII) | |
1208 | freq = 25000000; | |
1209 | else if (interface == PHY_INTERFACE_MODE_RMII) | |
1210 | freq = 50000000; | |
1211 | else if (interface == PHY_INTERFACE_MODE_RGMII || | |
1212 | interface == PHY_INTERFACE_MODE_RGMII_ID || | |
1213 | interface == PHY_INTERFACE_MODE_RGMII_RXID || | |
1214 | interface == PHY_INTERFACE_MODE_RGMII_TXID) | |
1215 | freq = 125000000; | |
1216 | else | |
1217 | return -EINVAL; | |
1218 | ||
1219 | ret = clk_set_rate(clk_ref, freq); | |
1220 | if (ret < 0) | |
1221 | return ret; | |
1222 | ||
1223 | return 0; | |
1224 | } | |
1225 | ||
60752ca8 JT |
1226 | static int fecmxc_probe(struct udevice *dev) |
1227 | { | |
cd435919 | 1228 | bool dm_mii_bus = true; |
c69cda25 | 1229 | struct eth_pdata *pdata = dev_get_plat(dev); |
60752ca8 JT |
1230 | struct fec_priv *priv = dev_get_priv(dev); |
1231 | struct mii_dev *bus = NULL; | |
60752ca8 JT |
1232 | uint32_t start; |
1233 | int ret; | |
1234 | ||
4bdc3524 MV |
1235 | ret = board_interface_eth_init(dev, pdata->phy_interface); |
1236 | if (ret) | |
1237 | return ret; | |
1238 | ||
24f95e14 | 1239 | if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) { |
3b26d527 PF |
1240 | if (enet_fused((ulong)priv->eth)) { |
1241 | printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth); | |
1242 | return -ENODEV; | |
1243 | } | |
1244 | } | |
1245 | ||
58ec4d33 AG |
1246 | if (IS_ENABLED(CONFIG_IMX8)) { |
1247 | ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); | |
1248 | if (ret < 0) { | |
1249 | debug("Can't get FEC ipg clk: %d\n", ret); | |
1250 | return ret; | |
1251 | } | |
1252 | ret = clk_enable(&priv->ipg_clk); | |
1253 | if (ret < 0) { | |
1254 | debug("Can't enable FEC ipg clk: %d\n", ret); | |
1255 | return ret; | |
1256 | } | |
1257 | ||
673f6597 PF |
1258 | priv->clk_rate = clk_get_rate(&priv->ipg_clk); |
1259 | } else if (CONFIG_IS_ENABLED(CLK_CCF)) { | |
1260 | ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); | |
1261 | if (ret < 0) { | |
1262 | debug("Can't get FEC ipg clk: %d\n", ret); | |
1263 | return ret; | |
1264 | } | |
1265 | ret = clk_enable(&priv->ipg_clk); | |
1266 | if(ret) | |
1267 | return ret; | |
1268 | ||
1269 | ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk); | |
1270 | if (ret < 0) { | |
1271 | debug("Can't get FEC ahb clk: %d\n", ret); | |
1272 | return ret; | |
1273 | } | |
1274 | ret = clk_enable(&priv->ahb_clk); | |
1275 | if (ret) | |
1276 | return ret; | |
1277 | ||
1278 | ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out); | |
1279 | if (!ret) { | |
1280 | ret = clk_enable(&priv->clk_enet_out); | |
1281 | if (ret) | |
1282 | return ret; | |
1283 | } | |
1284 | ||
1285 | ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref); | |
1286 | if (!ret) { | |
80a34e40 MV |
1287 | ret = fecmxc_set_ref_clk(&priv->clk_ref, |
1288 | pdata->phy_interface); | |
1289 | if (ret) | |
1290 | return ret; | |
1291 | ||
673f6597 PF |
1292 | ret = clk_enable(&priv->clk_ref); |
1293 | if (ret) | |
1294 | return ret; | |
1295 | } | |
1296 | ||
1297 | ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp); | |
1298 | if (!ret) { | |
1299 | ret = clk_enable(&priv->clk_ptp); | |
1300 | if (ret) | |
1301 | return ret; | |
1302 | } | |
1303 | ||
58ec4d33 AG |
1304 | priv->clk_rate = clk_get_rate(&priv->ipg_clk); |
1305 | } | |
1306 | ||
60752ca8 JT |
1307 | ret = fec_alloc_descs(priv); |
1308 | if (ret) | |
1309 | return ret; | |
1310 | ||
ad8c43cb MF |
1311 | #ifdef CONFIG_DM_REGULATOR |
1312 | if (priv->phy_supply) { | |
9dc7d527 | 1313 | ret = regulator_set_enable_if_allowed(priv->phy_supply, true); |
ad8c43cb MF |
1314 | if (ret) { |
1315 | printf("%s: Error enabling phy supply\n", dev->name); | |
1316 | return ret; | |
1317 | } | |
1318 | } | |
1319 | #endif | |
1320 | ||
bcee8d67 | 1321 | #if CONFIG_IS_ENABLED(DM_GPIO) |
efd0b791 MT |
1322 | fec_gpio_reset(priv); |
1323 | #endif | |
60752ca8 | 1324 | /* Reset chip. */ |
567173a6 JT |
1325 | writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, |
1326 | &priv->eth->ecntrl); | |
60752ca8 JT |
1327 | start = get_timer(0); |
1328 | while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
1329 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
f697addf | 1330 | printf("FEC MXC: Timeout resetting chip\n"); |
60752ca8 JT |
1331 | goto err_timeout; |
1332 | } | |
1333 | udelay(10); | |
1334 | } | |
1335 | ||
1336 | fec_reg_setup(priv); | |
60752ca8 | 1337 | |
8b85dfc6 | 1338 | priv->dev_id = dev_seq(dev); |
6a895d03 | 1339 | |
3b8f99a3 TH |
1340 | #ifdef CONFIG_DM_MDIO |
1341 | ret = dm_fec_bind_mdio(dev); | |
1342 | if (ret && ret != -ENODEV) | |
1343 | return ret; | |
1344 | #endif | |
1345 | ||
6a895d03 YL |
1346 | #ifdef CONFIG_DM_ETH_PHY |
1347 | bus = eth_phy_get_mdio_bus(dev); | |
1348 | #endif | |
1349 | ||
1350 | if (!bus) { | |
cd435919 | 1351 | dm_mii_bus = false; |
fbada485 | 1352 | #ifdef CONFIG_FEC_MXC_MDIO_BASE |
8b85dfc6 SG |
1353 | bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, |
1354 | dev_seq(dev)); | |
fbada485 | 1355 | #else |
8b85dfc6 | 1356 | bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev)); |
fbada485 | 1357 | #endif |
6a895d03 | 1358 | } |
306dd7da LW |
1359 | if (!bus) { |
1360 | ret = -ENOMEM; | |
1361 | goto err_mii; | |
1362 | } | |
1363 | ||
6a895d03 YL |
1364 | #ifdef CONFIG_DM_ETH_PHY |
1365 | eth_phy_set_mdio_bus(dev, bus); | |
1366 | #endif | |
1367 | ||
306dd7da | 1368 | priv->bus = bus; |
306dd7da | 1369 | priv->interface = pdata->phy_interface; |
0126c641 MF |
1370 | switch (priv->interface) { |
1371 | case PHY_INTERFACE_MODE_MII: | |
1372 | priv->xcv_type = MII100; | |
1373 | break; | |
1374 | case PHY_INTERFACE_MODE_RMII: | |
1375 | priv->xcv_type = RMII; | |
1376 | break; | |
1377 | case PHY_INTERFACE_MODE_RGMII: | |
1378 | case PHY_INTERFACE_MODE_RGMII_ID: | |
1379 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
1380 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
1381 | priv->xcv_type = RGMII; | |
1382 | break; | |
1383 | default: | |
08f1d58a TR |
1384 | priv->xcv_type = MII100; |
1385 | printf("Unsupported interface type %d defaulting to MII100\n", | |
1386 | priv->interface); | |
0126c641 MF |
1387 | break; |
1388 | } | |
1389 | ||
306dd7da LW |
1390 | ret = fec_phy_init(priv, dev); |
1391 | if (ret) | |
1392 | goto err_phy; | |
1393 | ||
60752ca8 JT |
1394 | return 0; |
1395 | ||
60752ca8 | 1396 | err_phy: |
cd435919 SA |
1397 | if (!dm_mii_bus) { |
1398 | mdio_unregister(bus); | |
1399 | free(bus); | |
1400 | } | |
60752ca8 | 1401 | err_mii: |
2087eac2 | 1402 | err_timeout: |
60752ca8 JT |
1403 | fec_free_descs(priv); |
1404 | return ret; | |
1405 | } | |
1406 | ||
1407 | static int fecmxc_remove(struct udevice *dev) | |
1408 | { | |
1409 | struct fec_priv *priv = dev_get_priv(dev); | |
1410 | ||
1411 | free(priv->phydev); | |
1412 | fec_free_descs(priv); | |
1413 | mdio_unregister(priv->bus); | |
1414 | mdio_free(priv->bus); | |
1415 | ||
ad8c43cb MF |
1416 | #ifdef CONFIG_DM_REGULATOR |
1417 | if (priv->phy_supply) | |
1418 | regulator_set_enable(priv->phy_supply, false); | |
1419 | #endif | |
1420 | ||
60752ca8 JT |
1421 | return 0; |
1422 | } | |
1423 | ||
d1998a9f | 1424 | static int fecmxc_of_to_plat(struct udevice *dev) |
60752ca8 | 1425 | { |
efd0b791 | 1426 | int ret = 0; |
c69cda25 | 1427 | struct eth_pdata *pdata = dev_get_plat(dev); |
60752ca8 | 1428 | struct fec_priv *priv = dev_get_priv(dev); |
60752ca8 | 1429 | |
2548493a | 1430 | pdata->iobase = dev_read_addr(dev); |
60752ca8 JT |
1431 | priv->eth = (struct ethernet_regs *)pdata->iobase; |
1432 | ||
123ca114 | 1433 | pdata->phy_interface = dev_read_phy_mode(dev); |
ffb0f6f4 | 1434 | if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) |
60752ca8 | 1435 | return -EINVAL; |
60752ca8 | 1436 | |
ad8c43cb MF |
1437 | #ifdef CONFIG_DM_REGULATOR |
1438 | device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply); | |
1439 | #endif | |
1440 | ||
bcee8d67 | 1441 | #if CONFIG_IS_ENABLED(DM_GPIO) |
efd0b791 | 1442 | ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, |
4223fb0e | 1443 | &priv->phy_reset_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); |
331fcabe MF |
1444 | if (ret < 0) |
1445 | return 0; /* property is optional, don't return error! */ | |
60752ca8 | 1446 | |
331fcabe | 1447 | priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1); |
efd0b791 | 1448 | if (priv->reset_delay > 1000) { |
331fcabe MF |
1449 | printf("FEC MXC: phy reset duration should be <= 1000ms\n"); |
1450 | /* property value wrong, use default value */ | |
1451 | priv->reset_delay = 1; | |
efd0b791 | 1452 | } |
31d4045d AC |
1453 | |
1454 | priv->reset_post_delay = dev_read_u32_default(dev, | |
1455 | "phy-reset-post-delay", | |
1456 | 0); | |
1457 | if (priv->reset_post_delay > 1000) { | |
1458 | printf("FEC MXC: phy reset post delay should be <= 1000ms\n"); | |
1459 | /* property value wrong, use default value */ | |
1460 | priv->reset_post_delay = 0; | |
1461 | } | |
efd0b791 MT |
1462 | #endif |
1463 | ||
331fcabe | 1464 | return 0; |
60752ca8 JT |
1465 | } |
1466 | ||
1467 | static const struct udevice_id fecmxc_ids[] = { | |
7782f4e4 | 1468 | { .compatible = "fsl,imx28-fec" }, |
60752ca8 | 1469 | { .compatible = "fsl,imx6q-fec" }, |
979e0fc8 PF |
1470 | { .compatible = "fsl,imx6sl-fec" }, |
1471 | { .compatible = "fsl,imx6sx-fec" }, | |
1472 | { .compatible = "fsl,imx6ul-fec" }, | |
948239ea | 1473 | { .compatible = "fsl,imx53-fec" }, |
58ec4d33 | 1474 | { .compatible = "fsl,imx7d-fec" }, |
27589e7d | 1475 | { .compatible = "fsl,mvf600-fec" }, |
09de565f | 1476 | { .compatible = "fsl,imx93-fec" }, |
60752ca8 JT |
1477 | { } |
1478 | }; | |
1479 | ||
1480 | U_BOOT_DRIVER(fecmxc_gem) = { | |
1481 | .name = "fecmxc", | |
1482 | .id = UCLASS_ETH, | |
1483 | .of_match = fecmxc_ids, | |
d1998a9f | 1484 | .of_to_plat = fecmxc_of_to_plat, |
60752ca8 JT |
1485 | .probe = fecmxc_probe, |
1486 | .remove = fecmxc_remove, | |
1487 | .ops = &fecmxc_ops, | |
41575d8e | 1488 | .priv_auto = sizeof(struct fec_priv), |
caa4daa2 | 1489 | .plat_auto = sizeof(struct eth_pdata), |
60752ca8 | 1490 | }; |