]>
Commit | Line | Data |
---|---|---|
120b5ef2 AM |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * ENETC ethernet controller driver | |
cd8817ac | 4 | * Copyright 2017-2021 NXP |
120b5ef2 AM |
5 | */ |
6 | ||
d678a59d | 7 | #include <common.h> |
120b5ef2 AM |
8 | #include <dm.h> |
9 | #include <errno.h> | |
4d72caa5 | 10 | #include <fdt_support.h> |
336d4615 | 11 | #include <malloc.h> |
120b5ef2 | 12 | #include <memalign.h> |
90526e9f SG |
13 | #include <net.h> |
14 | #include <asm/cache.h> | |
120b5ef2 AM |
15 | #include <asm/io.h> |
16 | #include <pci.h> | |
1d99534b | 17 | #include <miiphy.h> |
eb41d8a1 | 18 | #include <linux/bug.h> |
c05ed00a | 19 | #include <linux/delay.h> |
120b5ef2 AM |
20 | |
21 | #include "fsl_enetc.h" | |
22 | ||
9c2aee1b AM |
23 | #define ENETC_DRIVER_NAME "enetc_eth" |
24 | ||
5025224f SY |
25 | static int enetc_remove(struct udevice *dev); |
26 | ||
9c2aee1b AM |
27 | /* |
28 | * sets the MAC address in IERB registers, this setting is persistent and | |
29 | * carried over to Linux. | |
30 | */ | |
31 | static void enetc_set_ierb_primary_mac(struct udevice *dev, int devfn, | |
32 | const u8 *enetaddr) | |
33 | { | |
34 | #ifdef CONFIG_ARCH_LS1028A | |
35 | /* | |
36 | * LS1028A is the only part with IERB at this time and there are plans to change | |
37 | * its structure, keep this LS1028A specific for now | |
38 | */ | |
39 | #define IERB_BASE 0x1f0800000ULL | |
40 | #define IERB_PFMAC(pf, vf, n) (IERB_BASE + 0x8000 + (pf) * 0x100 + (vf) * 8 \ | |
41 | + (n) * 4) | |
42 | ||
43 | static int ierb_fn_to_pf[] = {0, 1, 2, -1, -1, -1, 3}; | |
44 | ||
45 | u16 lower = *(const u16 *)(enetaddr + 4); | |
46 | u32 upper = *(const u32 *)enetaddr; | |
47 | ||
48 | if (ierb_fn_to_pf[devfn] < 0) | |
49 | return; | |
50 | ||
51 | out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 0), upper); | |
52 | out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 1), (u32)lower); | |
53 | #endif | |
54 | } | |
55 | ||
56 | /* sets up primary MAC addresses in DT/IERB */ | |
57 | void fdt_fixup_enetc_mac(void *blob) | |
58 | { | |
8a8d24bd | 59 | struct pci_child_plat *ppdata; |
9c2aee1b AM |
60 | struct eth_pdata *pdata; |
61 | struct udevice *dev; | |
62 | struct uclass *uc; | |
63 | char path[256]; | |
64 | int offset; | |
65 | int devfn; | |
66 | ||
67 | uclass_get(UCLASS_ETH, &uc); | |
68 | uclass_foreach_dev(dev, uc) { | |
69 | if (!dev->driver || !dev->driver->name || | |
70 | strcmp(dev->driver->name, ENETC_DRIVER_NAME)) | |
71 | continue; | |
72 | ||
c69cda25 | 73 | pdata = dev_get_plat(dev); |
caa4daa2 | 74 | ppdata = dev_get_parent_plat(dev); |
9c2aee1b AM |
75 | devfn = PCI_FUNC(ppdata->devfn); |
76 | ||
77 | enetc_set_ierb_primary_mac(dev, devfn, pdata->enetaddr); | |
78 | ||
79 | snprintf(path, 256, "/soc/pcie@1f0000000/ethernet@%x,%x", | |
80 | PCI_DEV(ppdata->devfn), PCI_FUNC(ppdata->devfn)); | |
81 | offset = fdt_path_offset(blob, path); | |
82 | if (offset < 0) | |
83 | continue; | |
84 | fdt_setprop(blob, offset, "mac-address", pdata->enetaddr, 6); | |
85 | } | |
86 | } | |
87 | ||
120b5ef2 AM |
88 | /* |
89 | * Bind the device: | |
90 | * - set a more explicit name on the interface | |
91 | */ | |
92 | static int enetc_bind(struct udevice *dev) | |
93 | { | |
94 | char name[16]; | |
95 | static int eth_num_devices; | |
96 | ||
97 | /* | |
98 | * prefer using PCI function numbers to number interfaces, but these | |
99 | * are only available if dts nodes are present. For PCI they are | |
100 | * optional, handle that case too. Just in case some nodes are present | |
101 | * and some are not, use different naming scheme - enetc-N based on | |
102 | * PCI function # and enetc#N based on interface count | |
103 | */ | |
f10643cf | 104 | if (ofnode_valid(dev_ofnode(dev))) |
120b5ef2 AM |
105 | sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev))); |
106 | else | |
107 | sprintf(name, "enetc#%u", eth_num_devices++); | |
108 | device_set_name(dev, name); | |
109 | ||
110 | return 0; | |
111 | } | |
112 | ||
e4aafd5c AM |
113 | /* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */ |
114 | static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) | |
115 | { | |
116 | struct enetc_mdio_priv priv; | |
117 | ||
118 | priv.regs_base = bus->priv; | |
119 | return enetc_mdio_read_priv(&priv, addr, devad, reg); | |
120 | } | |
121 | ||
122 | static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, | |
123 | u16 val) | |
124 | { | |
125 | struct enetc_mdio_priv priv; | |
126 | ||
127 | priv.regs_base = bus->priv; | |
128 | return enetc_mdio_write_priv(&priv, addr, devad, reg, val); | |
129 | } | |
130 | ||
131 | /* only interfaces that can pin out through serdes have internal MDIO */ | |
132 | static bool enetc_has_imdio(struct udevice *dev) | |
133 | { | |
134 | struct enetc_priv *priv = dev_get_priv(dev); | |
135 | ||
136 | return !!(priv->imdio.priv); | |
137 | } | |
138 | ||
139 | /* set up serdes for SGMII */ | |
140 | static int enetc_init_sgmii(struct udevice *dev) | |
141 | { | |
142 | struct enetc_priv *priv = dev_get_priv(dev); | |
9bc07e81 AM |
143 | bool is2500 = false; |
144 | u16 reg; | |
e4aafd5c AM |
145 | |
146 | if (!enetc_has_imdio(dev)) | |
147 | return 0; | |
148 | ||
8149b150 | 149 | if (priv->uclass_id == PHY_INTERFACE_MODE_2500BASEX) |
9bc07e81 AM |
150 | is2500 = true; |
151 | ||
152 | /* | |
153 | * Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed. | |
154 | * Although fixed speed is 1Gbps, we could be running at 2.5Gbps based | |
155 | * on PLL configuration. Setting 1G for 2.5G here is counter intuitive | |
156 | * but intentional. | |
157 | */ | |
158 | reg = ENETC_PCS_IF_MODE_SGMII; | |
159 | reg |= is2500 ? ENETC_PCS_IF_MODE_SPEED_1G : ENETC_PCS_IF_MODE_SGMII_AN; | |
e4aafd5c | 160 | enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE, |
9bc07e81 | 161 | ENETC_PCS_IF_MODE, reg); |
e4aafd5c AM |
162 | |
163 | /* Dev ability - SGMII */ | |
164 | enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE, | |
165 | ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII); | |
166 | ||
167 | /* Adjust link timer for SGMII */ | |
168 | enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE, | |
169 | ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL); | |
170 | enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE, | |
171 | ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL); | |
172 | ||
9bc07e81 AM |
173 | reg = ENETC_PCS_CR_DEF_VAL; |
174 | reg |= is2500 ? ENETC_PCS_CR_RST : ENETC_PCS_CR_RESET_AN; | |
e4aafd5c AM |
175 | /* restart PCS AN */ |
176 | enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE, | |
9bc07e81 | 177 | ENETC_PCS_CR, reg); |
e4aafd5c AM |
178 | |
179 | return 0; | |
180 | } | |
181 | ||
182 | /* set up MAC for RGMII */ | |
71346a84 | 183 | static void enetc_init_rgmii(struct udevice *dev, struct phy_device *phydev) |
e4aafd5c AM |
184 | { |
185 | struct enetc_priv *priv = dev_get_priv(dev); | |
71346a84 | 186 | u32 old_val, val; |
e4aafd5c | 187 | |
71346a84 | 188 | old_val = val = enetc_read_port(priv, ENETC_PM_IF_MODE); |
e4aafd5c | 189 | |
71346a84 VO |
190 | /* disable unreliable RGMII in-band signaling and force the MAC into |
191 | * the speed negotiated by the PHY. | |
192 | */ | |
193 | val &= ~ENETC_PM_IF_MODE_AN_ENA; | |
194 | ||
195 | if (phydev->speed == SPEED_1000) { | |
196 | val &= ~ENETC_PM_IFM_SSP_MASK; | |
197 | val |= ENETC_PM_IFM_SSP_1000; | |
198 | } else if (phydev->speed == SPEED_100) { | |
199 | val &= ~ENETC_PM_IFM_SSP_MASK; | |
200 | val |= ENETC_PM_IFM_SSP_100; | |
201 | } else if (phydev->speed == SPEED_10) { | |
202 | val &= ~ENETC_PM_IFM_SSP_MASK; | |
203 | val |= ENETC_PM_IFM_SSP_10; | |
204 | } | |
205 | ||
206 | if (phydev->duplex == DUPLEX_FULL) | |
207 | val |= ENETC_PM_IFM_FULL_DPX; | |
208 | else | |
209 | val &= ~ENETC_PM_IFM_FULL_DPX; | |
210 | ||
211 | if (val == old_val) | |
212 | return; | |
213 | ||
214 | enetc_write_port(priv, ENETC_PM_IF_MODE, val); | |
e4aafd5c AM |
215 | } |
216 | ||
b8e4eec7 | 217 | /* set up MAC configuration for the given interface type */ |
71346a84 VO |
218 | static void enetc_setup_mac_iface(struct udevice *dev, |
219 | struct phy_device *phydev) | |
e4aafd5c AM |
220 | { |
221 | struct enetc_priv *priv = dev_get_priv(dev); | |
222 | u32 if_mode; | |
223 | ||
8149b150 | 224 | switch (priv->uclass_id) { |
b8e4eec7 AM |
225 | case PHY_INTERFACE_MODE_RGMII: |
226 | case PHY_INTERFACE_MODE_RGMII_ID: | |
227 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
228 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
71346a84 | 229 | enetc_init_rgmii(dev, phydev); |
b8e4eec7 | 230 | break; |
b8e4eec7 | 231 | case PHY_INTERFACE_MODE_USXGMII: |
77b11f76 | 232 | case PHY_INTERFACE_MODE_10GBASER: |
b8e4eec7 AM |
233 | /* set ifmode to (US)XGMII */ |
234 | if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE); | |
235 | if_mode &= ~ENETC_PM_IF_IFMODE_MASK; | |
236 | enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode); | |
237 | break; | |
238 | }; | |
239 | } | |
240 | ||
241 | /* set up serdes for SXGMII */ | |
242 | static int enetc_init_sxgmii(struct udevice *dev) | |
243 | { | |
244 | struct enetc_priv *priv = dev_get_priv(dev); | |
e4aafd5c AM |
245 | |
246 | if (!enetc_has_imdio(dev)) | |
247 | return 0; | |
248 | ||
249 | /* Dev ability - SXGMII */ | |
250 | enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL, | |
251 | ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII); | |
252 | ||
253 | /* Restart PCS AN */ | |
254 | enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL, | |
255 | ENETC_PCS_CR, | |
9bc07e81 | 256 | ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN); |
e4aafd5c AM |
257 | |
258 | return 0; | |
259 | } | |
260 | ||
261 | /* Apply protocol specific configuration to MAC, serdes as needed */ | |
262 | static void enetc_start_pcs(struct udevice *dev) | |
263 | { | |
264 | struct enetc_priv *priv = dev_get_priv(dev); | |
e4aafd5c | 265 | |
1e354cb3 | 266 | /* register internal MDIO for debug purposes */ |
e4aafd5c | 267 | if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) { |
e4aafd5c AM |
268 | priv->imdio.read = enetc_mdio_read; |
269 | priv->imdio.write = enetc_mdio_write; | |
270 | priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE; | |
f848b480 | 271 | strlcpy(priv->imdio.name, dev->name, MDIO_NAME_LEN); |
1e354cb3 AM |
272 | if (!miiphy_get_dev_by_name(priv->imdio.name)) |
273 | mdio_register(&priv->imdio); | |
e4aafd5c AM |
274 | } |
275 | ||
f10643cf | 276 | if (!ofnode_valid(dev_ofnode(dev))) { |
e4aafd5c AM |
277 | enetc_dbg(dev, "no enetc ofnode found, skipping PCS set-up\n"); |
278 | return; | |
279 | } | |
280 | ||
8149b150 SG |
281 | priv->uclass_id = dev_read_phy_mode(dev); |
282 | if (priv->uclass_id == PHY_INTERFACE_MODE_NA) { | |
e4aafd5c AM |
283 | enetc_dbg(dev, |
284 | "phy-mode property not found, defaulting to SGMII\n"); | |
8149b150 | 285 | priv->uclass_id = PHY_INTERFACE_MODE_SGMII; |
123ca114 | 286 | } |
e4aafd5c | 287 | |
8149b150 | 288 | switch (priv->uclass_id) { |
e4aafd5c | 289 | case PHY_INTERFACE_MODE_SGMII: |
7c2d5d16 | 290 | case PHY_INTERFACE_MODE_2500BASEX: |
e4aafd5c AM |
291 | enetc_init_sgmii(dev); |
292 | break; | |
e22e3aff | 293 | case PHY_INTERFACE_MODE_USXGMII: |
77b11f76 | 294 | case PHY_INTERFACE_MODE_10GBASER: |
e4aafd5c AM |
295 | enetc_init_sxgmii(dev); |
296 | break; | |
297 | }; | |
298 | } | |
299 | ||
1d99534b | 300 | /* Configure the actual/external ethernet PHY, if one is found */ |
cd8817ac | 301 | static int enetc_config_phy(struct udevice *dev) |
1d99534b AM |
302 | { |
303 | struct enetc_priv *priv = dev_get_priv(dev); | |
1d99534b AM |
304 | int supported; |
305 | ||
17bd7eae | 306 | priv->phy = dm_eth_phy_connect(dev); |
17bd7eae | 307 | if (!priv->phy) |
cd8817ac | 308 | return -ENODEV; |
1d99534b | 309 | |
307f8a6d AM |
310 | supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full; |
311 | priv->phy->supported &= supported; | |
312 | priv->phy->advertising &= supported; | |
17bd7eae | 313 | |
cd8817ac | 314 | return phy_config(priv->phy); |
1d99534b AM |
315 | } |
316 | ||
120b5ef2 AM |
317 | /* |
318 | * Probe ENETC driver: | |
319 | * - initialize port and station interface BARs | |
320 | */ | |
321 | static int enetc_probe(struct udevice *dev) | |
322 | { | |
323 | struct enetc_priv *priv = dev_get_priv(dev); | |
5025224f | 324 | int res; |
120b5ef2 | 325 | |
89090661 | 326 | if (ofnode_valid(dev_ofnode(dev)) && !ofnode_is_enabled(dev_ofnode(dev))) { |
120b5ef2 AM |
327 | enetc_dbg(dev, "interface disabled\n"); |
328 | return -ENODEV; | |
329 | } | |
330 | ||
331 | priv->enetc_txbd = memalign(ENETC_BD_ALIGN, | |
332 | sizeof(struct enetc_tx_bd) * ENETC_BD_CNT); | |
333 | priv->enetc_rxbd = memalign(ENETC_BD_ALIGN, | |
334 | sizeof(union enetc_rx_bd) * ENETC_BD_CNT); | |
335 | ||
336 | if (!priv->enetc_txbd || !priv->enetc_rxbd) { | |
337 | /* free should be able to handle NULL, just free all pointers */ | |
338 | free(priv->enetc_txbd); | |
339 | free(priv->enetc_rxbd); | |
340 | ||
341 | return -ENOMEM; | |
342 | } | |
343 | ||
344 | /* initialize register */ | |
2635e3b5 | 345 | priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, 0); |
120b5ef2 AM |
346 | if (!priv->regs_base) { |
347 | enetc_dbg(dev, "failed to map BAR0\n"); | |
348 | return -EINVAL; | |
349 | } | |
350 | priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF; | |
351 | ||
352 | dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY); | |
353 | ||
a931f783 | 354 | enetc_start_pcs(dev); |
a931f783 | 355 | |
5025224f SY |
356 | res = enetc_config_phy(dev); |
357 | if(res) | |
358 | enetc_remove(dev); | |
359 | return res; | |
120b5ef2 AM |
360 | } |
361 | ||
362 | /* | |
363 | * Remove the driver from an interface: | |
364 | * - free up allocated memory | |
365 | */ | |
366 | static int enetc_remove(struct udevice *dev) | |
367 | { | |
368 | struct enetc_priv *priv = dev_get_priv(dev); | |
369 | ||
7704b7fd MW |
370 | if (miiphy_get_dev_by_name(priv->imdio.name)) |
371 | mdio_unregister(&priv->imdio); | |
372 | ||
120b5ef2 AM |
373 | free(priv->enetc_txbd); |
374 | free(priv->enetc_rxbd); | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
42c66f05 MW |
379 | /* |
380 | * LS1028A is the only part with IERB at this time and there are plans to | |
381 | * change its structure, keep this LS1028A specific for now. | |
382 | */ | |
383 | #define LS1028A_IERB_BASE 0x1f0800000ULL | |
384 | #define LS1028A_IERB_PSIPMAR0(pf, vf) (LS1028A_IERB_BASE + 0x8000 \ | |
385 | + (pf) * 0x100 + (vf) * 8) | |
386 | #define LS1028A_IERB_PSIPMAR1(pf, vf) (LS1028A_IERB_PSIPMAR0(pf, vf) + 4) | |
387 | ||
388 | static int enetc_ls1028a_write_hwaddr(struct udevice *dev) | |
389 | { | |
8a8d24bd | 390 | struct pci_child_plat *ppdata = dev_get_parent_plat(dev); |
42c66f05 | 391 | const int devfn_to_pf[] = {0, 1, 2, -1, -1, -1, 3}; |
c69cda25 | 392 | struct eth_pdata *plat = dev_get_plat(dev); |
42c66f05 MW |
393 | int devfn = PCI_FUNC(ppdata->devfn); |
394 | u8 *addr = plat->enetaddr; | |
395 | u32 lower, upper; | |
396 | int pf; | |
397 | ||
398 | if (devfn >= ARRAY_SIZE(devfn_to_pf)) | |
399 | return 0; | |
400 | ||
401 | pf = devfn_to_pf[devfn]; | |
402 | if (pf < 0) | |
403 | return 0; | |
404 | ||
405 | lower = *(const u16 *)(addr + 4); | |
406 | upper = *(const u32 *)addr; | |
407 | ||
408 | out_le32(LS1028A_IERB_PSIPMAR0(pf, 0), upper); | |
409 | out_le32(LS1028A_IERB_PSIPMAR1(pf, 0), lower); | |
410 | ||
411 | return 0; | |
412 | } | |
413 | ||
ee5c70b8 | 414 | static int enetc_write_hwaddr(struct udevice *dev) |
120b5ef2 | 415 | { |
c69cda25 | 416 | struct eth_pdata *plat = dev_get_plat(dev); |
ee5c70b8 MW |
417 | struct enetc_priv *priv = dev_get_priv(dev); |
418 | u8 *addr = plat->enetaddr; | |
419 | ||
42c66f05 MW |
420 | if (IS_ENABLED(CONFIG_ARCH_LS1028A)) |
421 | return enetc_ls1028a_write_hwaddr(dev); | |
422 | ||
120b5ef2 AM |
423 | u16 lower = *(const u16 *)(addr + 4); |
424 | u32 upper = *(const u32 *)addr; | |
425 | ||
426 | enetc_write_port(priv, ENETC_PSIPMAR0, upper); | |
427 | enetc_write_port(priv, ENETC_PSIPMAR1, lower); | |
ee5c70b8 MW |
428 | |
429 | return 0; | |
120b5ef2 AM |
430 | } |
431 | ||
432 | /* Configure port parameters (# of rings, frame size, enable port) */ | |
433 | static void enetc_enable_si_port(struct enetc_priv *priv) | |
434 | { | |
435 | u32 val; | |
436 | ||
437 | /* set Rx/Tx BDR count */ | |
438 | val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT); | |
439 | val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT); | |
440 | enetc_write_port(priv, ENETC_PSICFGR(0), val); | |
441 | /* set Rx max frame size */ | |
442 | enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE); | |
443 | /* enable MAC port */ | |
444 | enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN); | |
445 | /* enable port */ | |
446 | enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN); | |
447 | /* set SI cache policy */ | |
448 | enetc_write(priv, ENETC_SICAR0, | |
449 | ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG); | |
450 | /* enable SI */ | |
451 | enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN); | |
452 | } | |
453 | ||
454 | /* returns DMA address for a given buffer index */ | |
455 | static inline u64 enetc_rxb_address(struct udevice *dev, int i) | |
456 | { | |
457 | return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i])); | |
458 | } | |
459 | ||
460 | /* | |
461 | * Setup a single Tx BD Ring (ID = 0): | |
462 | * - set Tx buffer descriptor address | |
463 | * - set the BD count | |
464 | * - initialize the producer and consumer index | |
465 | */ | |
466 | static void enetc_setup_tx_bdr(struct udevice *dev) | |
467 | { | |
468 | struct enetc_priv *priv = dev_get_priv(dev); | |
469 | struct bd_ring *tx_bdr = &priv->tx_bdr; | |
470 | u64 tx_bd_add = (u64)priv->enetc_txbd; | |
471 | ||
472 | /* used later to advance to the next Tx BD */ | |
473 | tx_bdr->bd_count = ENETC_BD_CNT; | |
474 | tx_bdr->next_prod_idx = 0; | |
475 | tx_bdr->next_cons_idx = 0; | |
476 | tx_bdr->cons_idx = priv->regs_base + | |
477 | ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR); | |
478 | tx_bdr->prod_idx = priv->regs_base + | |
479 | ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR); | |
480 | ||
481 | /* set Tx BD address */ | |
482 | enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0, | |
483 | lower_32_bits(tx_bd_add)); | |
484 | enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1, | |
485 | upper_32_bits(tx_bd_add)); | |
486 | /* set Tx 8 BD count */ | |
487 | enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR, | |
488 | tx_bdr->bd_count); | |
489 | ||
490 | /* reset both producer/consumer indexes */ | |
491 | enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx); | |
492 | enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx); | |
493 | ||
494 | /* enable TX ring */ | |
495 | enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN); | |
496 | } | |
497 | ||
498 | /* | |
499 | * Setup a single Rx BD Ring (ID = 0): | |
500 | * - set Rx buffer descriptors address (one descriptor per buffer) | |
501 | * - set buffer size as max frame size | |
502 | * - enable Rx ring | |
503 | * - reset consumer and producer indexes | |
504 | * - set buffer for each descriptor | |
505 | */ | |
506 | static void enetc_setup_rx_bdr(struct udevice *dev) | |
507 | { | |
508 | struct enetc_priv *priv = dev_get_priv(dev); | |
509 | struct bd_ring *rx_bdr = &priv->rx_bdr; | |
510 | u64 rx_bd_add = (u64)priv->enetc_rxbd; | |
511 | int i; | |
512 | ||
513 | /* used later to advance to the next BD produced by ENETC HW */ | |
514 | rx_bdr->bd_count = ENETC_BD_CNT; | |
515 | rx_bdr->next_prod_idx = 0; | |
516 | rx_bdr->next_cons_idx = 0; | |
517 | rx_bdr->cons_idx = priv->regs_base + | |
518 | ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR); | |
519 | rx_bdr->prod_idx = priv->regs_base + | |
520 | ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR); | |
521 | ||
522 | /* set Rx BD address */ | |
523 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0, | |
524 | lower_32_bits(rx_bd_add)); | |
525 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1, | |
526 | upper_32_bits(rx_bd_add)); | |
527 | /* set Rx BD count (multiple of 8) */ | |
528 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR, | |
529 | rx_bdr->bd_count); | |
530 | /* set Rx buffer size */ | |
531 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN); | |
532 | ||
533 | /* fill Rx BD */ | |
534 | memset(priv->enetc_rxbd, 0, | |
535 | rx_bdr->bd_count * sizeof(union enetc_rx_bd)); | |
536 | for (i = 0; i < rx_bdr->bd_count; i++) { | |
537 | priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i); | |
538 | /* each RX buffer must be aligned to 64B */ | |
539 | WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1)); | |
540 | } | |
541 | ||
542 | /* reset producer (ENETC owned) and consumer (SW owned) index */ | |
543 | enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx); | |
544 | enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx); | |
545 | ||
546 | /* enable Rx ring */ | |
547 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN); | |
548 | } | |
549 | ||
550 | /* | |
551 | * Start ENETC interface: | |
552 | * - perform FLR | |
553 | * - enable access to port and SI registers | |
554 | * - set mac address | |
555 | * - setup TX/RX buffer descriptors | |
556 | * - enable Tx/Rx rings | |
557 | */ | |
558 | static int enetc_start(struct udevice *dev) | |
559 | { | |
120b5ef2 AM |
560 | struct enetc_priv *priv = dev_get_priv(dev); |
561 | ||
562 | /* reset and enable the PCI device */ | |
563 | dm_pci_flr(dev); | |
564 | dm_pci_clrset_config16(dev, PCI_COMMAND, 0, | |
565 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
566 | ||
120b5ef2 AM |
567 | enetc_enable_si_port(priv); |
568 | ||
569 | /* setup Tx/Rx buffer descriptors */ | |
570 | enetc_setup_tx_bdr(dev); | |
571 | enetc_setup_rx_bdr(dev); | |
572 | ||
71346a84 VO |
573 | enetc_setup_mac_iface(dev, priv->phy); |
574 | ||
c4428507 | 575 | return phy_startup(priv->phy); |
120b5ef2 AM |
576 | } |
577 | ||
578 | /* | |
579 | * Stop the network interface: | |
580 | * - just quiesce it, we can wipe all configuration as _start starts from | |
581 | * scratch each time | |
582 | */ | |
583 | static void enetc_stop(struct udevice *dev) | |
584 | { | |
585 | /* FLR is sufficient to quiesce the device */ | |
586 | dm_pci_flr(dev); | |
1e354cb3 AM |
587 | /* leave the BARs accessible after we stop, this is needed to use |
588 | * internal MDIO in command line. | |
589 | */ | |
590 | dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY); | |
120b5ef2 AM |
591 | } |
592 | ||
593 | /* | |
594 | * ENETC transmit packet: | |
595 | * - check if Tx BD ring is full | |
596 | * - set buffer/packet address (dma address) | |
597 | * - set final fragment flag | |
598 | * - try while producer index equals consumer index or timeout | |
599 | */ | |
600 | static int enetc_send(struct udevice *dev, void *packet, int length) | |
601 | { | |
602 | struct enetc_priv *priv = dev_get_priv(dev); | |
603 | struct bd_ring *txr = &priv->tx_bdr; | |
604 | void *nv_packet = (void *)packet; | |
605 | int tries = ENETC_POLL_TRIES; | |
606 | u32 pi, ci; | |
607 | ||
608 | pi = txr->next_prod_idx; | |
609 | ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK; | |
610 | /* Tx ring is full when */ | |
611 | if (((pi + 1) % txr->bd_count) == ci) { | |
612 | enetc_dbg(dev, "Tx BDR full\n"); | |
613 | return -ETIMEDOUT; | |
614 | } | |
615 | enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length, | |
616 | upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet)); | |
617 | ||
618 | /* prepare Tx BD */ | |
619 | memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd)); | |
620 | priv->enetc_txbd[pi].addr = | |
621 | cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet)); | |
622 | priv->enetc_txbd[pi].buf_len = cpu_to_le16(length); | |
623 | priv->enetc_txbd[pi].frm_len = cpu_to_le16(length); | |
624 | priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F); | |
625 | dmb(); | |
626 | /* send frame: increment producer index */ | |
627 | pi = (pi + 1) % txr->bd_count; | |
628 | txr->next_prod_idx = pi; | |
629 | enetc_write_reg(txr->prod_idx, pi); | |
630 | while ((--tries >= 0) && | |
631 | (pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK))) | |
632 | udelay(10); | |
633 | ||
634 | return tries > 0 ? 0 : -ETIMEDOUT; | |
635 | } | |
636 | ||
637 | /* | |
638 | * Receive frame: | |
639 | * - wait for the next BD to get ready bit set | |
640 | * - clean up the descriptor | |
641 | * - move on and indicate to HW that the cleaned BD is available for Rx | |
642 | */ | |
643 | static int enetc_recv(struct udevice *dev, int flags, uchar **packetp) | |
644 | { | |
645 | struct enetc_priv *priv = dev_get_priv(dev); | |
646 | struct bd_ring *rxr = &priv->rx_bdr; | |
647 | int tries = ENETC_POLL_TRIES; | |
648 | int pi = rxr->next_prod_idx; | |
649 | int ci = rxr->next_cons_idx; | |
650 | u32 status; | |
651 | int len; | |
652 | u8 rdy; | |
653 | ||
654 | do { | |
655 | dmb(); | |
656 | status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus); | |
657 | /* check if current BD is ready to be consumed */ | |
658 | rdy = ENETC_RXBD_STATUS_R(status); | |
659 | } while (--tries >= 0 && !rdy); | |
660 | ||
661 | if (!rdy) | |
662 | return -EAGAIN; | |
663 | ||
664 | dmb(); | |
665 | len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len); | |
666 | *packetp = (uchar *)enetc_rxb_address(dev, pi); | |
667 | enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len, | |
668 | ENETC_RXBD_STATUS_ERRORS(status), | |
669 | upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp)); | |
670 | ||
671 | /* BD clean up and advance to next in ring */ | |
672 | memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd)); | |
673 | priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi); | |
674 | rxr->next_prod_idx = (pi + 1) % rxr->bd_count; | |
675 | ci = (ci + 1) % rxr->bd_count; | |
676 | rxr->next_cons_idx = ci; | |
677 | dmb(); | |
678 | /* free up the slot in the ring for HW */ | |
679 | enetc_write_reg(rxr->cons_idx, ci); | |
680 | ||
681 | return len; | |
682 | } | |
683 | ||
684 | static const struct eth_ops enetc_ops = { | |
685 | .start = enetc_start, | |
686 | .send = enetc_send, | |
687 | .recv = enetc_recv, | |
688 | .stop = enetc_stop, | |
ee5c70b8 | 689 | .write_hwaddr = enetc_write_hwaddr, |
120b5ef2 AM |
690 | }; |
691 | ||
692 | U_BOOT_DRIVER(eth_enetc) = { | |
9c2aee1b | 693 | .name = ENETC_DRIVER_NAME, |
120b5ef2 AM |
694 | .id = UCLASS_ETH, |
695 | .bind = enetc_bind, | |
696 | .probe = enetc_probe, | |
697 | .remove = enetc_remove, | |
698 | .ops = &enetc_ops, | |
41575d8e | 699 | .priv_auto = sizeof(struct enetc_priv), |
caa4daa2 | 700 | .plat_auto = sizeof(struct eth_pdata), |
120b5ef2 AM |
701 | }; |
702 | ||
703 | static struct pci_device_id enetc_ids[] = { | |
704 | { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) }, | |
705 | {} | |
706 | }; | |
707 | ||
708 | U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids); |