[people/ms/u-boot.git] / drivers / net / fsl_mcdmafec.c

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <malloc.h>
#include <command.h>
#include <config.h>
#include <net.h>
#include <miiphy.h>

#undef	ET_DEBUG
#undef	MII_DEBUG

/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH		1520
#define PKT_MAXBUF_SIZE		1518
#define PKT_MINBUF_SIZE		64
#define PKT_MAXBLR_SIZE		1536
#define LAST_PKTBUFSRX		PKTBUFSRX - 1
#define BD_ENET_RX_W_E		(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
#define BD_ENET_TX_RDY_LST	(BD_ENET_TX_READY | BD_ENET_TX_LAST)
#define FIFO_ERRSTAT		(FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)

/* RxBD bits definitions */
#define BD_ENET_RX_ERR	(BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
			 BD_ENET_RX_OV | BD_ENET_RX_TR)

#include <asm/immap.h>
#include <asm/fsl_mcdmafec.h>

#include "MCD_dma.h"

DECLARE_GLOBAL_DATA_PTR;

struct fec_info_dma fec_info[] = {
#ifdef CONFIG_SYS_FEC0_IOBASE
	{
	 0,			/* index */
	 CONFIG_SYS_FEC0_IOBASE,	/* io base */
	 CONFIG_SYS_FEC0_PINMUX,	/* gpio pin muxing */
	 CONFIG_SYS_FEC0_MIIBASE,	/* mii base */
	 -1,			/* phy_addr */
	 0,			/* duplex and speed */
	 0,			/* phy name */
	 0,			/* phyname init */
	 0,			/* RX BD */
	 0,			/* TX BD */
	 0,			/* rx Index */
	 0,			/* tx Index */
	 0,			/* tx buffer */
	 0,			/* initialized flag */
	 (struct fec_info_dma *)-1,	/* next */
	 FEC0_RX_TASK,		/* rxTask */
	 FEC0_TX_TASK,		/* txTask */
	 FEC0_RX_PRIORITY,	/* rxPri */
	 FEC0_TX_PRIORITY,	/* txPri */
	 FEC0_RX_INIT,		/* rxInit */
	 FEC0_TX_INIT,		/* txInit */
	 0,			/* usedTbdIndex */
	 0,			/* cleanTbdNum */
	 },
#endif
#ifdef CONFIG_SYS_FEC1_IOBASE
	{
	 1,			/* index */
	 CONFIG_SYS_FEC1_IOBASE,	/* io base */
	 CONFIG_SYS_FEC1_PINMUX,	/* gpio pin muxing */
	 CONFIG_SYS_FEC1_MIIBASE,	/* mii base */
	 -1,			/* phy_addr */
	 0,			/* duplex and speed */
	 0,			/* phy name */
	 0,			/* phy name init */
#ifdef CONFIG_SYS_DMA_USE_INTSRAM
	 (cbd_t *)DBUF_LENGTH,	/* RX BD */
#else
	 0,			/* RX BD */
#endif
	 0,			/* TX BD */
	 0,			/* rx Index */
	 0,			/* tx Index */
	 0,			/* tx buffer */
	 0,			/* initialized flag */
	 (struct fec_info_dma *)-1,	/* next */
	 FEC1_RX_TASK,		/* rxTask */
	 FEC1_TX_TASK,		/* txTask */
	 FEC1_RX_PRIORITY,	/* rxPri */
	 FEC1_TX_PRIORITY,	/* txPri */
	 FEC1_RX_INIT,		/* rxInit */
	 FEC1_TX_INIT,		/* txInit */
	 0,			/* usedTbdIndex */
	 0,			/* cleanTbdNum */
	 }
#endif
};

static int fec_send(struct eth_device *dev, volatile void *packet, int length);
static int fec_recv(struct eth_device *dev);
static int fec_init(struct eth_device *dev, bd_t * bd);
static void fec_halt(struct eth_device *dev);

#ifdef ET_DEBUG
static void dbg_fec_regs(struct eth_device *dev)
{
	struct fec_info_dma *info = dev->priv;
	volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);

	printf("=====\n");
	printf("ievent       %x - %x\n", (int)&fecp->eir, fecp->eir);
	printf("imask        %x - %x\n", (int)&fecp->eimr, fecp->eimr);
	printf("ecntrl       %x - %x\n", (int)&fecp->ecr, fecp->ecr);
	printf("mii_mframe   %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
	printf("mii_speed    %x - %x\n", (int)&fecp->mscr, fecp->mscr);
	printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
	printf("r_cntrl      %x - %x\n", (int)&fecp->rcr, fecp->rcr);
	printf("r hash       %x - %x\n", (int)&fecp->rhr, fecp->rhr);
	printf("x_cntrl      %x - %x\n", (int)&fecp->tcr, fecp->tcr);
	printf("padr_l       %x - %x\n", (int)&fecp->palr, fecp->palr);
	printf("padr_u       %x - %x\n", (int)&fecp->paur, fecp->paur);
	printf("op_pause     %x - %x\n", (int)&fecp->opd, fecp->opd);
	printf("iadr_u       %x - %x\n", (int)&fecp->iaur, fecp->iaur);
	printf("iadr_l       %x - %x\n", (int)&fecp->ialr, fecp->ialr);
	printf("gadr_u       %x - %x\n", (int)&fecp->gaur, fecp->gaur);
	printf("gadr_l       %x - %x\n", (int)&fecp->galr, fecp->galr);
	printf("x_wmrk       %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
	printf("r_fdata      %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
	printf("r_fstat      %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
	printf("r_fctrl      %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
	printf("r_flrfp      %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
	printf("r_flwfp      %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
	printf("r_frfar      %x - %x\n", (int)&fecp->rfar, fecp->rfar);
	printf("r_frfrp      %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
	printf("r_frfwp      %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
	printf("t_fdata      %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
	printf("t_fstat      %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
	printf("t_fctrl      %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
	printf("t_flrfp      %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
	printf("t_flwfp      %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
	printf("t_ftfar      %x - %x\n", (int)&fecp->tfar, fecp->tfar);
	printf("t_ftfrp      %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
	printf("t_ftfwp      %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
	printf("frst         %x - %x\n", (int)&fecp->frst, fecp->frst);
	printf("ctcwr        %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
}
#endif

static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
				 int dup_spd)
{
	if ((dup_spd >> 16) == FULL) {
		/* Set maximum frame length */
		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
		    FEC_RCR_PROM | 0x100;
		fecp->tcr = FEC_TCR_FDEN;
	} else {
		/* Half duplex mode */
		fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
		    FEC_RCR_MII_MODE | FEC_RCR_DRT;
		fecp->tcr &= ~FEC_TCR_FDEN;
	}

	if ((dup_spd & 0xFFFF) == _100BASET) {
#ifdef MII_DEBUG
		printf("100Mbps\n");
#endif
		bd->bi_ethspeed = 100;
	} else {
#ifdef MII_DEBUG
		printf("10Mbps\n");
#endif
		bd->bi_ethspeed = 10;
	}
}

static int fec_send(struct eth_device *dev, volatile void *packet, int length)
{
	struct fec_info_dma *info = dev->priv;
	cbd_t *pTbd, *pUsedTbd;
	u16 phyStatus;

	miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);

	/* process all the consumed TBDs */
	while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
		pUsedTbd = &info->txbd[info->usedTbdIdx];
		if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
#ifdef ET_DEBUG
			printf("Cannot clean TBD %d, in use\n",
			       info->cleanTbdNum);
#endif
			return 0;
		}

		/* clean this buffer descriptor */
		if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
			pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
		else
			pUsedTbd->cbd_sc = 0;

		/* update some indeces for a correct handling of the TBD ring */
		info->cleanTbdNum++;
		info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
	}

	/* Check for valid length of data. */
	if ((length > 1500) || (length <= 0)) {
		return -1;
	}

	/* Check the number of vacant TxBDs. */
	if (info->cleanTbdNum < 1) {
		printf("No available TxBDs ...\n");
		return -1;
	}

	/* Get the first TxBD to send the mac header */
	pTbd = &info->txbd[info->txIdx];
	pTbd->cbd_datlen = length;
	pTbd->cbd_bufaddr = (u32) packet;
	pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
	info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;

	/* Enable DMA transmit task */
	MCD_continDma(info->txTask);

	info->cleanTbdNum -= 1;

	/* wait until frame is sent . */
	while (pTbd->cbd_sc & BD_ENET_TX_READY) {
		udelay(10);
	}

	return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
}

static int fec_recv(struct eth_device *dev)
{
	struct fec_info_dma *info = dev->priv;
	volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);

	cbd_t *pRbd = &info->rxbd[info->rxIdx];
	u32 ievent;
	int frame_length, len = 0;

	/* Check if any critical events have happened */
	ievent = fecp->eir;
	if (ievent != 0) {
		fecp->eir = ievent;

		if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
			printf("fec_recv: error\n");
			fec_halt(dev);
			fec_init(dev, NULL);
			return 0;
		}

		if (ievent & FEC_EIR_HBERR) {
			/* Heartbeat error */
			fecp->tcr |= FEC_TCR_GTS;
		}

		if (ievent & FEC_EIR_GRA) {
			/* Graceful stop complete */
			if (fecp->tcr & FEC_TCR_GTS) {
				printf("fec_recv: tcr_gts\n");
				fec_halt(dev);
				fecp->tcr &= ~FEC_TCR_GTS;
				fec_init(dev, NULL);
			}
		}
	}

	if (!(pRbd->cbd_sc & BD_ENET_RX_EMPTY)) {
		if ((pRbd->cbd_sc & BD_ENET_RX_LAST)
		    && !(pRbd->cbd_sc & BD_ENET_RX_ERR)
		    && ((pRbd->cbd_datlen - 4) > 14)) {

			/* Get buffer address and size */
			frame_length = pRbd->cbd_datlen - 4;

			/* Fill the buffer and pass it to upper layers */
			NetReceive((volatile uchar *)pRbd->cbd_bufaddr,
				   frame_length);
			len = frame_length;
		}

		/* Reset buffer descriptor as empty */
		if ((info->rxIdx) == (PKTBUFSRX - 1))
			pRbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
		else
			pRbd->cbd_sc = BD_ENET_RX_EMPTY;

		pRbd->cbd_datlen = PKTSIZE_ALIGN;

		/* Now, we have an empty RxBD, restart the DMA receive task */
		MCD_continDma(info->rxTask);

		/* Increment BD count */
		info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX;
	}

	return len;
}

static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
{
	u8 currByte;		/* byte for which to compute the CRC */
	int byte;		/* loop - counter */
	int bit;		/* loop - counter */
	u32 crc = 0xffffffff;	/* initial value */

	for (byte = 0; byte < 6; byte++) {
		currByte = mac[byte];
		for (bit = 0; bit < 8; bit++) {
			if ((currByte & 0x01) ^ (crc & 0x01)) {
				crc >>= 1;
				crc = crc ^ 0xedb88320;
			} else {
				crc >>= 1;
			}
			currByte >>= 1;
		}
	}

	crc = crc >> 26;

	/* Set individual hash table register */
	if (crc >= 32) {
		fecp->ialr = (1 << (crc - 32));
		fecp->iaur = 0;
	} else {
		fecp->ialr = 0;
		fecp->iaur = (1 << crc);
	}

	/* Set physical address */
	fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
	fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;

	/* Clear multicast address hash table */
	fecp->gaur = 0;
	fecp->galr = 0;
}

static int fec_init(struct eth_device *dev, bd_t * bd)
{
	struct fec_info_dma *info = dev->priv;
	volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
	int i;

#ifdef ET_DEBUG
	printf("fec_init: iobase 0x%08x ...\n", info->iobase);
#endif

	fecpin_setclear(dev, 1);

	fec_halt(dev);

#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
	defined (CONFIG_SYS_DISCOVER_PHY)

	mii_init();

	set_fec_duplex_speed(fecp, bd, info->dup_spd);
#else
#ifndef CONFIG_SYS_DISCOVER_PHY
	set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
#endif				/* ifndef CONFIG_SYS_DISCOVER_PHY */
#endif				/* CONFIG_CMD_MII || CONFIG_MII */

	/* We use strictly polling mode only */
	fecp->eimr = 0;

	/* Clear any pending interrupt */
	fecp->eir = 0xffffffff;

	/* Set station address   */
	if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
		fec_set_hwaddr(fecp, bd->bi_enetaddr);
	} else {
		fec_set_hwaddr(fecp, bd->bi_enet1addr);
	}

	/* Set Opcode/Pause Duration Register */
	fecp->opd = 0x00010020;

	/* Setup Buffers and Buffer Desriptors */
	info->rxIdx = 0;
	info->txIdx = 0;

	/* Setup Receiver Buffer Descriptors (13.14.24.18)
	 * Settings:     Empty, Wrap */
	for (i = 0; i < PKTBUFSRX; i++) {
		info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
		info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
		info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
	}
	info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;

	/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
	 * Settings:    Last, Tx CRC */
	for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
		info->txbd[i].cbd_sc = 0;
		info->txbd[i].cbd_datlen = 0;
		info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
	}
	info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;

	info->usedTbdIdx = 0;
	info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER;

	/* Set Rx FIFO alarm and granularity value */
	fecp->rfcr = 0x0c000000;
	fecp->rfar = 0x0000030c;

	/* Set Tx FIFO granularity value */
	fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
	fecp->tfar = 0x00000080;

	fecp->tfwr = 0x2;
	fecp->ctcwr = 0x03000000;

	/* Enable DMA receive task */
	MCD_startDma(info->rxTask,	/* Dma channel */
		     (s8 *) info->rxbd,	/*Source Address */
		     0,		/* Source increment */
		     (s8 *) (&fecp->rfdr),	/* dest */
		     4,		/* dest increment */
		     0,		/* DMA size */
		     4,		/* xfer size */
		     info->rxInit,	/* initiator */
		     info->rxPri,	/* priority */
		     (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),	/* Flags */
		     (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)	/* Function description */
	    );

	/* Enable DMA tx task with no ready buffer descriptors */
	MCD_startDma(info->txTask,	/* Dma channel */
		     (s8 *) info->txbd,	/*Source Address */
		     0,		/* Source increment */
		     (s8 *) (&fecp->tfdr),	/* dest */
		     4,		/* dest incr */
		     0,		/* DMA size */
		     4,		/* xfer size */
		     info->txInit,	/* initiator */
		     info->txPri,	/* priority */
		     (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),	/* Flags */
		     (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)	/* Function description */
	    );

	/* Now enable the transmit and receive processing */
	fecp->ecr |= FEC_ECR_ETHER_EN;

	return 1;
}

static void fec_halt(struct eth_device *dev)
{
	struct fec_info_dma *info = dev->priv;
	volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
	int counter = 0xffff;

	/* issue graceful stop command to the FEC transmitter if necessary */
	fecp->tcr |= FEC_TCR_GTS;

	/* wait for graceful stop to register */
	while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ;

	/* Disable DMA tasks */
	MCD_killDma(info->txTask);
	MCD_killDma(info->rxTask);;

	/* Disable the Ethernet Controller */
	fecp->ecr &= ~FEC_ECR_ETHER_EN;

	/* Clear FIFO status registers */
	fecp->rfsr &= FIFO_ERRSTAT;
	fecp->tfsr &= FIFO_ERRSTAT;

	fecp->frst = 0x01000000;

	/* Issue a reset command to the FEC chip */
	fecp->ecr |= FEC_ECR_RESET;

	/* wait at least 20 clock cycles */
	udelay(10000);

#ifdef ET_DEBUG
	printf("Ethernet task stopped\n");
#endif
}

int mcdmafec_initialize(bd_t * bis)
{
	struct eth_device *dev;
	int i;
#ifdef CONFIG_SYS_DMA_USE_INTSRAM
	u32 tmp = CONFIG_SYS_INTSRAM + 0x2000;
#endif

	for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {

		dev =
		    (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
						  sizeof *dev);
		if (dev == NULL)
			hang();

		memset(dev, 0, sizeof(*dev));

		sprintf(dev->name, "FEC%d", fec_info[i].index);

		dev->priv = &fec_info[i];
		dev->init = fec_init;
		dev->halt = fec_halt;
		dev->send = fec_send;
		dev->recv = fec_recv;

		/* setup Receive and Transmit buffer descriptor */
#ifdef CONFIG_SYS_DMA_USE_INTSRAM
		fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
		tmp = (u32)fec_info[i].rxbd;
		fec_info[i].txbd =
		    (cbd_t *)((u32)fec_info[i].txbd + tmp +
		    (PKTBUFSRX * sizeof(cbd_t)));
		tmp = (u32)fec_info[i].txbd;
		fec_info[i].txbuf =
		    (char *)((u32)fec_info[i].txbuf + tmp +
		    (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
		tmp = (u32)fec_info[i].txbuf;
#else
		fec_info[i].rxbd =
		    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
				       (PKTBUFSRX * sizeof(cbd_t)));
		fec_info[i].txbd =
		    (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
				       (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
		fec_info[i].txbuf =
		    (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
#endif

#ifdef ET_DEBUG
		printf("rxbd %x txbd %x\n",
		       (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
#endif

		fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);

		eth_register(dev);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
		miiphy_register(dev->name,
				mcffec_miiphy_read, mcffec_miiphy_write);
#endif

		if (i > 0)
			fec_info[i - 1].next = &fec_info[i];
	}
	fec_info[i - 1].next = &fec_info[0];

	/* default speed */
	bis->bi_ethspeed = 10;

	return 0;
}
Commit	Line	Data
777d1abd TL	1	/*
	2	* (C) Copyright 2000-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2007 Freescale Semiconductor, Inc.
	6	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <malloc.h>
	29	#include <command.h>
	30	#include <config.h>
	31	#include <net.h>
	32	#include <miiphy.h>
	33
777d1abd TL	34	#undef ET_DEBUG
	35	#undef MII_DEBUG
	36
	37	/* Ethernet Transmit and Receive Buffers */
	38	#define DBUF_LENGTH 1520
	39	#define PKT_MAXBUF_SIZE 1518
	40	#define PKT_MINBUF_SIZE 64
	41	#define PKT_MAXBLR_SIZE 1536
	42	#define LAST_PKTBUFSRX PKTBUFSRX - 1
	43	#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP \| BD_ENET_RX_EMPTY)
	44	#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY \| BD_ENET_TX_LAST)
	45	#define FIFO_ERRSTAT (FIFO_STAT_RXW \| FIFO_STAT_UF \| FIFO_STAT_OF)
	46
	47	/* RxBD bits definitions */
	48	#define BD_ENET_RX_ERR (BD_ENET_RX_LG \| BD_ENET_RX_NO \| BD_ENET_RX_CR \| \
	49	BD_ENET_RX_OV \| BD_ENET_RX_TR)
	50
777d1abd TL	51	#include <asm/immap.h>
	52	#include <asm/fsl_mcdmafec.h>
	53
	54	#include "MCD_dma.h"
	55
	56	DECLARE_GLOBAL_DATA_PTR;
	57
	58	struct fec_info_dma fec_info[] = {
6d0f6bcf	59	#ifdef CONFIG_SYS_FEC0_IOBASE
777d1abd TL	60	{
777d1abd TL	61	0, /* index */
6d0f6bcf JCPV	62	CONFIG_SYS_FEC0_IOBASE, /* io base */
	63	CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
	64	CONFIG_SYS_FEC0_MIIBASE, /* mii base */
777d1abd TL	65	-1, /* phy_addr */
	66	0, /* duplex and speed */
	67	0, /* phy name */
	68	0, /* phyname init */
	69	0, /* RX BD */
	70	0, /* TX BD */
	71	0, /* rx Index */
	72	0, /* tx Index */
	73	0, /* tx buffer */
	74	0, /* initialized flag */
	75	(struct fec_info_dma )-1, / next */
	76	FEC0_RX_TASK, /* rxTask */
	77	FEC0_TX_TASK, /* txTask */
	78	FEC0_RX_PRIORITY, /* rxPri */
	79	FEC0_TX_PRIORITY, /* txPri */
	80	FEC0_RX_INIT, /* rxInit */
	81	FEC0_TX_INIT, /* txInit */
	82	0, /* usedTbdIndex */
	83	0, /* cleanTbdNum */
	84	},
	85	#endif
6d0f6bcf	86	#ifdef CONFIG_SYS_FEC1_IOBASE
777d1abd TL	87	{
777d1abd TL	88	1, /* index */
6d0f6bcf JCPV	89	CONFIG_SYS_FEC1_IOBASE, /* io base */
	90	CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
	91	CONFIG_SYS_FEC1_MIIBASE, /* mii base */
777d1abd TL	92	-1, /* phy_addr */
	93	0, /* duplex and speed */
	94	0, /* phy name */
	95	0, /* phy name init */
6d0f6bcf	96	#ifdef CONFIG_SYS_DMA_USE_INTSRAM
429be27c	97	(cbd_t )DBUF_LENGTH, / RX BD */
f32f7fe7	98	#else
777d1abd	99	0, /* RX BD */
f32f7fe7	100	#endif
777d1abd TL	101	0, /* TX BD */
	102	0, /* rx Index */
	103	0, /* tx Index */
	104	0, /* tx buffer */
	105	0, /* initialized flag */
	106	(struct fec_info_dma )-1, / next */
	107	FEC1_RX_TASK, /* rxTask */
	108	FEC1_TX_TASK, /* txTask */
	109	FEC1_RX_PRIORITY, /* rxPri */
	110	FEC1_TX_PRIORITY, /* txPri */
	111	FEC1_RX_INIT, /* rxInit */
	112	FEC1_TX_INIT, /* txInit */
	113	0, /* usedTbdIndex */
	114	0, /* cleanTbdNum */
	115	}
	116	#endif
	117	};
	118
	119	static int fec_send(struct eth_device dev, volatile void packet, int length);
	120	static int fec_recv(struct eth_device *dev);
	121	static int fec_init(struct eth_device dev, bd_t bd);
	122	static void fec_halt(struct eth_device *dev);
	123
	124	#ifdef ET_DEBUG
	125	static void dbg_fec_regs(struct eth_device *dev)
	126	{
	127	struct fec_info_dma *info = dev->priv;
	128	volatile fecdma_t fecp = (fecdma_t ) (info->iobase);
	129
	130	printf("=====\n");
	131	printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
	132	printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
	133	printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
	134	printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
	135	printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
	136	printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
	137	printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
	138	printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
	139	printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
	140	printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
	141	printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
	142	printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
	143	printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
	144	printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
	145	printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
	146	printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
	147	printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
	148	printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
	149	printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
	150	printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
	151	printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
	152	printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
	153	printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
	154	printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
	155	printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
	156	printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
	157	printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
	158	printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
	159	printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
	160	printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
	161	printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
	162	printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
	163	printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
	164	printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
165	printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
166	}
167	#endif
168
f32f7fe7 TL	169	static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
f32f7fe7 TL	170	int dup_spd)
777d1abd TL	171	{
	172	if ((dup_spd >> 16) == FULL) {
	173	/* Set maximum frame length */
	174	fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) \| FEC_RCR_MII_MODE \|
	175	FEC_RCR_PROM \| 0x100;
	176	fecp->tcr = FEC_TCR_FDEN;
	177	} else {
	178	/* Half duplex mode */
	179	fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) \|
	180	FEC_RCR_MII_MODE \| FEC_RCR_DRT;
	181	fecp->tcr &= ~FEC_TCR_FDEN;
	182	}
	183
	184	if ((dup_spd & 0xFFFF) == _100BASET) {
	185	#ifdef MII_DEBUG
	186	printf("100Mbps\n");
	187	#endif
	188	bd->bi_ethspeed = 100;
	189	} else {
	190	#ifdef MII_DEBUG
	191	printf("10Mbps\n");
	192	#endif
	193	bd->bi_ethspeed = 10;
	194	}
	195	}
	196
	197	static int fec_send(struct eth_device dev, volatile void packet, int length)
	198	{
	199	struct fec_info_dma *info = dev->priv;
	200	cbd_t pTbd, pUsedTbd;
	201	u16 phyStatus;
	202
	203	miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);
	204
	205	/* process all the consumed TBDs */
6d0f6bcf	206	while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
777d1abd TL	207	pUsedTbd = &info->txbd[info->usedTbdIdx];
	208	if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
	209	#ifdef ET_DEBUG
	210	printf("Cannot clean TBD %d, in use\n",
	211	info->cleanTbdNum);
	212	#endif
	213	return 0;
	214	}
	215
	216	/* clean this buffer descriptor */
6d0f6bcf	217	if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
777d1abd TL	218	pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
	219	else
	220	pUsedTbd->cbd_sc = 0;
	221
	222	/* update some indeces for a correct handling of the TBD ring */
	223	info->cleanTbdNum++;
6d0f6bcf	224	info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
777d1abd TL	225	}
	226
	227	/* Check for valid length of data. */
	228	if ((length > 1500) \|\| (length <= 0)) {
	229	return -1;
	230	}
	231
	232	/* Check the number of vacant TxBDs. */
	233	if (info->cleanTbdNum < 1) {
	234	printf("No available TxBDs ...\n");
	235	return -1;
	236	}
	237
	238	/* Get the first TxBD to send the mac header */
	239	pTbd = &info->txbd[info->txIdx];
	240	pTbd->cbd_datlen = length;
	241	pTbd->cbd_bufaddr = (u32) packet;
	242	pTbd->cbd_sc \|= BD_ENET_TX_LAST \| BD_ENET_TX_TC \| BD_ENET_TX_READY;
6d0f6bcf	243	info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
777d1abd TL	244
	245	/* Enable DMA transmit task */
	246	MCD_continDma(info->txTask);
	247
	248	info->cleanTbdNum -= 1;
	249
	250	/* wait until frame is sent . */
	251	while (pTbd->cbd_sc & BD_ENET_TX_READY) {
	252	udelay(10);
	253	}
	254
	255	return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
	256	}
	257
	258	static int fec_recv(struct eth_device *dev)
	259	{
	260	struct fec_info_dma *info = dev->priv;
	261	volatile fecdma_t fecp = (fecdma_t ) (info->iobase);
	262
	263	cbd_t *pRbd = &info->rxbd[info->rxIdx];
	264	u32 ievent;
	265	int frame_length, len = 0;
	266
	267	/* Check if any critical events have happened */
	268	ievent = fecp->eir;
	269	if (ievent != 0) {
	270	fecp->eir = ievent;
	271
	272	if (ievent & (FEC_EIR_BABT \| FEC_EIR_TXERR \| FEC_EIR_RXERR)) {
	273	printf("fec_recv: error\n");
	274	fec_halt(dev);
	275	fec_init(dev, NULL);
	276	return 0;
	277	}
	278
	279	if (ievent & FEC_EIR_HBERR) {
	280	/* Heartbeat error */
	281	fecp->tcr \|= FEC_TCR_GTS;
	282	}
	283
	284	if (ievent & FEC_EIR_GRA) {
	285	/* Graceful stop complete */
	286	if (fecp->tcr & FEC_TCR_GTS) {
	287	printf("fec_recv: tcr_gts\n");
	288	fec_halt(dev);
	289	fecp->tcr &= ~FEC_TCR_GTS;
	290	fec_init(dev, NULL);
	291	}
	292	}
	293	}
	294
	295	if (!(pRbd->cbd_sc & BD_ENET_RX_EMPTY)) {
	296	if ((pRbd->cbd_sc & BD_ENET_RX_LAST)
	297	&& !(pRbd->cbd_sc & BD_ENET_RX_ERR)
	298	&& ((pRbd->cbd_datlen - 4) > 14)) {
	299
	300	/* Get buffer address and size */
	301	frame_length = pRbd->cbd_datlen - 4;
	302
	303	/* Fill the buffer and pass it to upper layers */
	304	NetReceive((volatile uchar *)pRbd->cbd_bufaddr,
	305	frame_length);
	306	len = frame_length;
	307	}
308
309	/* Reset buffer descriptor as empty */
310	if ((info->rxIdx) == (PKTBUFSRX - 1))
311	pRbd->cbd_sc = (BD_ENET_RX_WRAP \| BD_ENET_RX_EMPTY);
312	else
313	pRbd->cbd_sc = BD_ENET_RX_EMPTY;
314
315	pRbd->cbd_datlen = PKTSIZE_ALIGN;
316
317	/* Now, we have an empty RxBD, restart the DMA receive task */
318	MCD_continDma(info->rxTask);
319
320	/* Increment BD count */
321	info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX;
322	}
323
324	return len;
325	}
326
327	static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
328	{
329	u8 currByte; /* byte for which to compute the CRC */
330	int byte; /* loop - counter */
331	int bit; /* loop - counter */
332	u32 crc = 0xffffffff; /* initial value */
333
334	for (byte = 0; byte < 6; byte++) {
335	currByte = mac[byte];
336	for (bit = 0; bit < 8; bit++) {
337	if ((currByte & 0x01) ^ (crc & 0x01)) {
338	crc >>= 1;
339	crc = crc ^ 0xedb88320;
340	} else {
341	crc >>= 1;
342	}
343	currByte >>= 1;
344	}
345	}
346
347	crc = crc >> 26;
348
349	/* Set individual hash table register */
350	if (crc >= 32) {
351	fecp->ialr = (1 << (crc - 32));
352	fecp->iaur = 0;
353	} else {
354	fecp->ialr = 0;
355	fecp->iaur = (1 << crc);
356	}
357
358	/* Set physical address */
359	fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
360	fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
361
362	/* Clear multicast address hash table */
363	fecp->gaur = 0;
364	fecp->galr = 0;
365	}
366
367	static int fec_init(struct eth_device dev, bd_t bd)
368	{
369	struct fec_info_dma *info = dev->priv;
370	volatile fecdma_t fecp = (fecdma_t ) (info->iobase);
371	int i;
372
373	#ifdef ET_DEBUG
374	printf("fec_init: iobase 0x%08x ...\n", info->iobase);
375	#endif
376
377	fecpin_setclear(dev, 1);
378
379	fec_halt(dev);
380
381	#if defined(CONFIG_CMD_MII) \|\| defined (CONFIG_MII) \|\| \
6d0f6bcf	382	defined (CONFIG_SYS_DISCOVER_PHY)
777d1abd TL	383
	384	mii_init();
	385
	386	set_fec_duplex_speed(fecp, bd, info->dup_spd);
	387	#else
6d0f6bcf	388	#ifndef CONFIG_SYS_DISCOVER_PHY
777d1abd	389	set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) \| FECSPEED);
6d0f6bcf	390	#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
777d1abd TL	391	#endif /* CONFIG_CMD_MII \|\| CONFIG_MII */
	392
	393	/* We use strictly polling mode only */
	394	fecp->eimr = 0;
	395
	396	/* Clear any pending interrupt */
	397	fecp->eir = 0xffffffff;
	398
	399	/* Set station address */
6d0f6bcf	400	if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
777d1abd TL	401	fec_set_hwaddr(fecp, bd->bi_enetaddr);
	402	} else {
	403	fec_set_hwaddr(fecp, bd->bi_enet1addr);
	404	}
	405
	406	/* Set Opcode/Pause Duration Register */
	407	fecp->opd = 0x00010020;
	408
	409	/* Setup Buffers and Buffer Desriptors */
	410	info->rxIdx = 0;
	411	info->txIdx = 0;
	412
	413	/* Setup Receiver Buffer Descriptors (13.14.24.18)
	414	* Settings: Empty, Wrap */
	415	for (i = 0; i < PKTBUFSRX; i++) {
	416	info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
	417	info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
	418	info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
	419	}
	420	info->rxbd[PKTBUFSRX - 1].cbd_sc \|= BD_ENET_RX_WRAP;
	421
	422	/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
	423	* Settings: Last, Tx CRC */
6d0f6bcf	424	for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
777d1abd TL	425	info->txbd[i].cbd_sc = 0;
	426	info->txbd[i].cbd_datlen = 0;
	427	info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
	428	}
6d0f6bcf	429	info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc \|= BD_ENET_TX_WRAP;
777d1abd TL	430
777d1abd TL	431	info->usedTbdIdx = 0;
6d0f6bcf	432	info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER;
777d1abd TL	433
	434	/* Set Rx FIFO alarm and granularity value */
	435	fecp->rfcr = 0x0c000000;
	436	fecp->rfar = 0x0000030c;
	437
	438	/* Set Tx FIFO granularity value */
	439	fecp->tfcr = FIFO_CTRL_FRAME \| FIFO_CTRL_GR(6) \| 0x00040000;
	440	fecp->tfar = 0x00000080;
	441
	442	fecp->tfwr = 0x2;
	443	fecp->ctcwr = 0x03000000;
	444
	445	/* Enable DMA receive task */
	446	MCD_startDma(info->rxTask, /* Dma channel */
	447	(s8 ) info->rxbd, /Source Address */
	448	0, /* Source increment */
	449	(s8 ) (&fecp->rfdr), / dest */
	450	4, /* dest increment */
	451	0, /* DMA size */
	452	4, /* xfer size */
	453	info->rxInit, /* initiator */
	454	info->rxPri, /* priority */
	455	(MCD_FECRX_DMA \| MCD_TT_FLAGS_DEF), /* Flags */
	456	(MCD_NO_CSUM \| MCD_NO_BYTE_SWAP) /* Function description */
	457	);
	458
	459	/* Enable DMA tx task with no ready buffer descriptors */
	460	MCD_startDma(info->txTask, /* Dma channel */
	461	(s8 ) info->txbd, /Source Address */
	462	0, /* Source increment */
	463	(s8 ) (&fecp->tfdr), / dest */
	464	4, /* dest incr */
	465	0, /* DMA size */
	466	4, /* xfer size */
	467	info->txInit, /* initiator */
	468	info->txPri, /* priority */
	469	(MCD_FECTX_DMA \| MCD_TT_FLAGS_DEF), /* Flags */
	470	(MCD_NO_CSUM \| MCD_NO_BYTE_SWAP) /* Function description */
	471	);
	472
	473	/* Now enable the transmit and receive processing */
	474	fecp->ecr \|= FEC_ECR_ETHER_EN;
	475
	476	return 1;
	477	}
	478
	479	static void fec_halt(struct eth_device *dev)
	480	{
	481	struct fec_info_dma *info = dev->priv;
	482	volatile fecdma_t fecp = (fecdma_t ) (info->iobase);
	483	int counter = 0xffff;
	484
	485	/* issue graceful stop command to the FEC transmitter if necessary */
	486	fecp->tcr \|= FEC_TCR_GTS;
	487
	488	/* wait for graceful stop to register */
	489	while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ;
	490
	491	/* Disable DMA tasks */
	492	MCD_killDma(info->txTask);
	493	MCD_killDma(info->rxTask);;
	494
	495	/* Disable the Ethernet Controller */
	496	fecp->ecr &= ~FEC_ECR_ETHER_EN;
497
498	/* Clear FIFO status registers */
499	fecp->rfsr &= FIFO_ERRSTAT;
500	fecp->tfsr &= FIFO_ERRSTAT;
501
502	fecp->frst = 0x01000000;
503
504	/* Issue a reset command to the FEC chip */
505	fecp->ecr \|= FEC_ECR_RESET;
506
507	/* wait at least 20 clock cycles */
508	udelay(10000);
509
510	#ifdef ET_DEBUG
511	printf("Ethernet task stopped\n");
512	#endif
513	}
514
515	int mcdmafec_initialize(bd_t * bis)
516	{
517	struct eth_device *dev;
518	int i;
6d0f6bcf JCPV	519	#ifdef CONFIG_SYS_DMA_USE_INTSRAM
6d0f6bcf JCPV	520	u32 tmp = CONFIG_SYS_INTSRAM + 0x2000;
f32f7fe7	521	#endif
777d1abd TL	522
	523	for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
	524
	525	dev =
6d0f6bcf	526	(struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
777d1abd TL	527	sizeof *dev);
	528	if (dev == NULL)
	529	hang();
	530
	531	memset(dev, 0, sizeof(*dev));
	532
	533	sprintf(dev->name, "FEC%d", fec_info[i].index);
	534
	535	dev->priv = &fec_info[i];
	536	dev->init = fec_init;
	537	dev->halt = fec_halt;
	538	dev->send = fec_send;
	539	dev->recv = fec_recv;
	540
	541	/* setup Receive and Transmit buffer descriptor */
6d0f6bcf	542	#ifdef CONFIG_SYS_DMA_USE_INTSRAM
429be27c TL	543	fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
429be27c TL	544	tmp = (u32)fec_info[i].rxbd;
f32f7fe7	545	fec_info[i].txbd =
429be27c TL	546	(cbd_t *)((u32)fec_info[i].txbd + tmp +
	547	(PKTBUFSRX * sizeof(cbd_t)));
	548	tmp = (u32)fec_info[i].txbd;
f32f7fe7	549	fec_info[i].txbuf =
429be27c	550	(char *)((u32)fec_info[i].txbuf + tmp +
6d0f6bcf	551	(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
429be27c	552	tmp = (u32)fec_info[i].txbuf;
f32f7fe7	553	#else
777d1abd	554	fec_info[i].rxbd =
6d0f6bcf	555	(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
777d1abd TL	556	(PKTBUFSRX * sizeof(cbd_t)));
777d1abd TL	557	fec_info[i].txbd =
6d0f6bcf JCPV	558	(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
6d0f6bcf JCPV	559	(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
777d1abd	560	fec_info[i].txbuf =
6d0f6bcf	561	(char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
f32f7fe7	562	#endif
777d1abd TL	563
	564	#ifdef ET_DEBUG
	565	printf("rxbd %x txbd %x\n",
	566	(int)fec_info[i].rxbd, (int)fec_info[i].txbd);
	567	#endif
	568
6d0f6bcf	569	fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
777d1abd TL	570
	571	eth_register(dev);
	572
	573	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
	574	miiphy_register(dev->name,
	575	mcffec_miiphy_read, mcffec_miiphy_write);
	576	#endif
	577
	578	if (i > 0)
	579	fec_info[i - 1].next = &fec_info[i];
	580	}
	581	fec_info[i - 1].next = &fec_info[0];
	582
	583	/* default speed */
	584	bis->bi_ethspeed = 10;
	585
b31da88b	586	return 0;
777d1abd	587	}