[people/ms/u-boot.git] / drivers / net / keystone_net.c

/*
 * Ethernet driver for TI K2HK EVM.
 *
 * (C) Copyright 2012-2014
 *     Texas Instruments Incorporated, <www.ti.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */
#include <common.h>
#include <command.h>

#include <net.h>
#include <phy.h>
#include <errno.h>
#include <miiphy.h>
#include <malloc.h>
#include <asm/ti-common/keystone_nav.h>
#include <asm/ti-common/keystone_net.h>
#include <asm/ti-common/keystone_serdes.h>

unsigned int emac_open;
static struct mii_dev *mdio_bus;
static unsigned int sys_has_mdio = 1;

#ifdef KEYSTONE2_EMAC_GIG_ENABLE
#define emac_gigabit_enable(x)	keystone2_eth_gigabit_enable(x)
#else
#define emac_gigabit_enable(x)	/* no gigabit to enable */
#endif

#define RX_BUFF_NUMS	24
#define RX_BUFF_LEN	1520
#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
#define SGMII_ANEG_TIMEOUT		4000

static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);

struct rx_buff_desc net_rx_buffs = {
	.buff_ptr	= rx_buffs,
	.num_buffs	= RX_BUFF_NUMS,
	.buff_len	= RX_BUFF_LEN,
	.rx_flow	= 22,
};

static void keystone2_net_serdes_setup(void);

int keystone2_eth_read_mac_addr(struct eth_device *dev)
{
	struct eth_priv_t *eth_priv;
	u32 maca = 0;
	u32 macb = 0;

	eth_priv = (struct eth_priv_t *)dev->priv;

	/* Read the e-fuse mac address */
	if (eth_priv->slave_port == 1) {
		maca = __raw_readl(MAC_ID_BASE_ADDR);
		macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
	}

	dev->enetaddr[0] = (macb >>  8) & 0xff;
	dev->enetaddr[1] = (macb >>  0) & 0xff;
	dev->enetaddr[2] = (maca >> 24) & 0xff;
	dev->enetaddr[3] = (maca >> 16) & 0xff;
	dev->enetaddr[4] = (maca >>  8) & 0xff;
	dev->enetaddr[5] = (maca >>  0) & 0xff;

	return 0;
}

/* MDIO */

static int keystone2_mdio_reset(struct mii_dev *bus)
{
	u_int32_t clkdiv;
	struct mdio_regs *adap_mdio = bus->priv;

	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;

	writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
	       MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
	       &adap_mdio->control);

	while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
		;

	return 0;
}

/**
 * keystone2_mdio_read - read a PHY register via MDIO interface.
 * Blocks until operation is complete.
 */
static int keystone2_mdio_read(struct mii_dev *bus,
			       int addr, int devad, int reg)
{
	int tmp;
	struct mdio_regs *adap_mdio = bus->priv;

	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
		;

	writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
	       ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
	       &adap_mdio->useraccess0);

	/* Wait for command to complete */
	while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
		;

	if (tmp & MDIO_USERACCESS0_ACK)
		return tmp & 0xffff;

	return -1;
}

/**
 * keystone2_mdio_write - write to a PHY register via MDIO interface.
 * Blocks until operation is complete.
 */
static int keystone2_mdio_write(struct mii_dev *bus,
				int addr, int devad, int reg, u16 val)
{
	struct mdio_regs *adap_mdio = bus->priv;

	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
		;

	writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
	       ((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
	       (val & 0xffff), &adap_mdio->useraccess0);

	/* Wait for command to complete */
	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
		;

	return 0;
}

static void  __attribute__((unused))
	keystone2_eth_gigabit_enable(struct eth_device *dev)
{
	u_int16_t data;
	struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;

	if (sys_has_mdio) {
		data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
					   MDIO_DEVAD_NONE, 0);
		/* speed selection MSB */
		if (!(data & (1 << 6)))
			return;
	}

	/*
	 * Check if link detected is giga-bit
	 * If Gigabit mode detected, enable gigbit in MAC
	 */
	writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
		     CPGMACSL_REG_CTL) |
	       EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
	       DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
}

int keystone_sgmii_link_status(int port)
{
	u32 status = 0;

	status = __raw_readl(SGMII_STATUS_REG(port));

	return (status & SGMII_REG_STATUS_LOCK) &&
	       (status & SGMII_REG_STATUS_LINK);
}

int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
{
	unsigned int i, status, mask;
	unsigned int mr_adv_ability, control;

	switch (interface) {
	case SGMII_LINK_MAC_MAC_AUTONEG:
		mr_adv_ability	= (SGMII_REG_MR_ADV_ENABLE |
				   SGMII_REG_MR_ADV_LINK |
				   SGMII_REG_MR_ADV_FULL_DUPLEX |
				   SGMII_REG_MR_ADV_GIG_MODE);
		control		= (SGMII_REG_CONTROL_MASTER |
				   SGMII_REG_CONTROL_AUTONEG);

		break;
	case SGMII_LINK_MAC_PHY:
	case SGMII_LINK_MAC_PHY_FORCED:
		mr_adv_ability	= SGMII_REG_MR_ADV_ENABLE;
		control		= SGMII_REG_CONTROL_AUTONEG;

		break;
	case SGMII_LINK_MAC_MAC_FORCED:
		mr_adv_ability	= (SGMII_REG_MR_ADV_ENABLE |
				   SGMII_REG_MR_ADV_LINK |
				   SGMII_REG_MR_ADV_FULL_DUPLEX |
				   SGMII_REG_MR_ADV_GIG_MODE);
		control		= SGMII_REG_CONTROL_MASTER;

		break;
	case SGMII_LINK_MAC_FIBER:
		mr_adv_ability	= 0x20;
		control		= SGMII_REG_CONTROL_AUTONEG;

		break;
	default:
		mr_adv_ability	= SGMII_REG_MR_ADV_ENABLE;
		control		= SGMII_REG_CONTROL_AUTONEG;
	}

	__raw_writel(0, SGMII_CTL_REG(port));

	/*
	 * Wait for the SerDes pll to lock,
	 * but don't trap if lock is never read
	 */
	for (i = 0; i < 1000; i++)  {
		udelay(2000);
		status = __raw_readl(SGMII_STATUS_REG(port));
		if ((status & SGMII_REG_STATUS_LOCK) != 0)
			break;
	}

	__raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
	__raw_writel(control, SGMII_CTL_REG(port));


	mask = SGMII_REG_STATUS_LINK;

	if (control & SGMII_REG_CONTROL_AUTONEG)
		mask |= SGMII_REG_STATUS_AUTONEG;

	status = __raw_readl(SGMII_STATUS_REG(port));
	if ((status & mask) == mask)
		return 0;

	printf("\n%s Waiting for SGMII auto negotiation to complete",
	       phy_dev->dev->name);
	while ((status & mask) != mask) {
		/*
		 * Timeout reached ?
		 */
		if (i > SGMII_ANEG_TIMEOUT) {
			puts(" TIMEOUT !\n");
			phy_dev->link = 0;
			return 0;
		}

		if (ctrlc()) {
			puts("user interrupt!\n");
			phy_dev->link = 0;
			return -EINTR;
		}

		if ((i++ % 500) == 0)
			printf(".");

		udelay(1000);   /* 1 ms */
		status = __raw_readl(SGMII_STATUS_REG(port));
	}
	puts(" done\n");

	return 0;
}

int mac_sl_reset(u32 port)
{
	u32 i, v;

	if (port >= DEVICE_N_GMACSL_PORTS)
		return GMACSL_RET_INVALID_PORT;

	/* Set the soft reset bit */
	writel(CPGMAC_REG_RESET_VAL_RESET,
	       DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);

	/* Wait for the bit to clear */
	for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
		v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
		if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
		    CPGMAC_REG_RESET_VAL_RESET)
			return GMACSL_RET_OK;
	}

	/* Timeout on the reset */
	return GMACSL_RET_WARN_RESET_INCOMPLETE;
}

int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
{
	u32 v, i;
	int ret = GMACSL_RET_OK;

	if (port >= DEVICE_N_GMACSL_PORTS)
		return GMACSL_RET_INVALID_PORT;

	if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
		cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
		ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
	}

	/* Must wait if the device is undergoing reset */
	for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
		v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
		if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
		    CPGMAC_REG_RESET_VAL_RESET)
			break;
	}

	if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
		return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;

	writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
	writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);

#ifdef CONFIG_K2E_EVM
	/* Map RX packet flow priority to 0 */
	writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
#endif

	return ret;
}

int ethss_config(u32 ctl, u32 max_pkt_size)
{
	u32 i;

	/* Max length register */
	writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);

	/* Control register */
	writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);

	/* All statistics enabled by default */
	writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
	       DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);

	/* Reset and enable the ALE */
	writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
	       CPSW_REG_VAL_ALE_CTL_BYPASS,
	       DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);

	/* All ports put into forward mode */
	for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
		writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
		       DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));

	return 0;
}

int ethss_start(void)
{
	int i;
	struct mac_sl_cfg cfg;

	cfg.max_rx_len	= MAX_SIZE_STREAM_BUFFER;
	cfg.ctl		= GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;

	for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
		mac_sl_reset(i);
		mac_sl_config(i, &cfg);
	}

	return 0;
}

int ethss_stop(void)
{
	int i;

	for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
		mac_sl_reset(i);

	return 0;
}

int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
{
	if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
		num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;

	return ksnav_send(&netcp_pktdma, buffer,
			  num_bytes, (slave_port_num) << 16);
}

/* Eth device open */
static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
{
	struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
	struct phy_device *phy_dev = eth_priv->phy_dev;

	debug("+ emac_open\n");

	net_rx_buffs.rx_flow	= eth_priv->rx_flow;

	sys_has_mdio =
		(eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;

	keystone2_net_serdes_setup();

	keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
			      eth_priv->sgmii_link_type);

	udelay(10000);

	/* On chip switch configuration */
	ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);

	/* TODO: add error handling code */
	if (qm_init()) {
		printf("ERROR: qm_init()\n");
		return -1;
	}
	if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
		qm_close();
		printf("ERROR: netcp_init()\n");
		return -1;
	}

	/*
	 * Streaming switch configuration. If not present this
	 * statement is defined to void in target.h.
	 * If present this is usually defined to a series of register writes
	 */
	hw_config_streaming_switch();

	if (sys_has_mdio) {
		keystone2_mdio_reset(mdio_bus);

		phy_startup(phy_dev);
		if (phy_dev->link == 0) {
			ksnav_close(&netcp_pktdma);
			qm_close();
			return -1;
		}
	}

	emac_gigabit_enable(dev);

	ethss_start();

	debug("- emac_open\n");

	emac_open = 1;

	return 0;
}

/* Eth device close */
void keystone2_eth_close(struct eth_device *dev)
{
	struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
	struct phy_device *phy_dev = eth_priv->phy_dev;

	debug("+ emac_close\n");

	if (!emac_open)
		return;

	ethss_stop();

	ksnav_close(&netcp_pktdma);
	qm_close();
	phy_shutdown(phy_dev);

	emac_open = 0;

	debug("- emac_close\n");
}

/*
 * This function sends a single packet on the network and returns
 * positive number (number of bytes transmitted) or negative for error
 */
static int keystone2_eth_send_packet(struct eth_device *dev,
					void *packet, int length)
{
	int ret_status = -1;
	struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
	struct phy_device *phy_dev = eth_priv->phy_dev;

	genphy_update_link(phy_dev);
	if (phy_dev->link == 0)
		return -1;

	if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
		return ret_status;

	return length;
}

/*
 * This function handles receipt of a packet from the network
 */
static int keystone2_eth_rcv_packet(struct eth_device *dev)
{
	void *hd;
	int  pkt_size;
	u32  *pkt;

	hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
	if (hd == NULL)
		return 0;

	NetReceive((uchar *)pkt, pkt_size);

	ksnav_release_rxhd(&netcp_pktdma, hd);

	return pkt_size;
}

/*
 * This function initializes the EMAC hardware.
 */
int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
{
	int res;
	struct eth_device *dev;
	struct phy_device *phy_dev;

	dev = malloc(sizeof(struct eth_device));
	if (dev == NULL)
		return -1;

	memset(dev, 0, sizeof(struct eth_device));

	strcpy(dev->name, eth_priv->int_name);
	dev->priv = eth_priv;

	keystone2_eth_read_mac_addr(dev);

	dev->iobase		= 0;
	dev->init		= keystone2_eth_open;
	dev->halt		= keystone2_eth_close;
	dev->send		= keystone2_eth_send_packet;
	dev->recv		= keystone2_eth_rcv_packet;

	eth_register(dev);

	/* Register MDIO bus if it's not registered yet */
	if (!mdio_bus) {
		mdio_bus	= mdio_alloc();
		mdio_bus->read	= keystone2_mdio_read;
		mdio_bus->write	= keystone2_mdio_write;
		mdio_bus->reset	= keystone2_mdio_reset;
		mdio_bus->priv	= (void *)EMAC_MDIO_BASE_ADDR;
		sprintf(mdio_bus->name, "ethernet-mdio");

		res = mdio_register(mdio_bus);
		if (res)
			return res;
	}

	/* Create phy device and bind it with driver */
#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
	phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
			      dev, PHY_INTERFACE_MODE_SGMII);
	phy_config(phy_dev);
#else
	phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
				   PHY_INTERFACE_MODE_SGMII);
	phy_dev->dev = dev;
#endif
	eth_priv->phy_dev = phy_dev;

	return 0;
}

struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
	.clk = SERDES_CLOCK_156P25M,
	.rate = SERDES_RATE_5G,
	.rate_mode = SERDES_QUARTER_RATE,
	.intf = SERDES_PHY_SGMII,
	.loopback = 0,
};

static void keystone2_net_serdes_setup(void)
{
	ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
			&ks2_serdes_sgmii_156p25mhz,
			CONFIG_KSNET_SERDES_LANES_PER_SGMII);

#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
	ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
			&ks2_serdes_sgmii_156p25mhz,
			CONFIG_KSNET_SERDES_LANES_PER_SGMII);
#endif

	/* wait till setup */
	udelay(5000);
}
Commit	Line	Data
fc9a8e8d KM	1	/*
	2	* Ethernet driver for TI K2HK EVM.
	3	*
	4	* (C) Copyright 2012-2014
	5	* Texas Instruments Incorporated, <www.ti.com>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9	#include <common.h>
	10	#include <command.h>
	11
	12	#include <net.h>
3fe93623	13	#include <phy.h>
c05d05e7	14	#include <errno.h>
fc9a8e8d KM	15	#include <miiphy.h>
fc9a8e8d KM	16	#include <malloc.h>
ef454717	17	#include <asm/ti-common/keystone_nav.h>
0935cac6	18	#include <asm/ti-common/keystone_net.h>
a43febde	19	#include <asm/ti-common/keystone_serdes.h>
fc9a8e8d	20
fc9a8e8d	21	unsigned int emac_open;
550c5ce6	22	static struct mii_dev *mdio_bus;
fc9a8e8d KM	23	static unsigned int sys_has_mdio = 1;
	24
	25	#ifdef KEYSTONE2_EMAC_GIG_ENABLE
	26	#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
	27	#else
	28	#define emac_gigabit_enable(x) /* no gigabit to enable */
	29	#endif
	30
	31	#define RX_BUFF_NUMS 24
	32	#define RX_BUFF_LEN 1520
	33	#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
c05d05e7	34	#define SGMII_ANEG_TIMEOUT 4000
fc9a8e8d KM	35
	36	static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
	37
	38	struct rx_buff_desc net_rx_buffs = {
	39	.buff_ptr = rx_buffs,
	40	.num_buffs = RX_BUFF_NUMS,
	41	.buff_len = RX_BUFF_LEN,
	42	.rx_flow = 22,
	43	};
	44
a43febde	45	static void keystone2_net_serdes_setup(void);
fc9a8e8d	46
fc9a8e8d KM	47	int keystone2_eth_read_mac_addr(struct eth_device *dev)
	48	{
	49	struct eth_priv_t *eth_priv;
	50	u32 maca = 0;
	51	u32 macb = 0;
	52
	53	eth_priv = (struct eth_priv_t *)dev->priv;
	54
	55	/* Read the e-fuse mac address */
	56	if (eth_priv->slave_port == 1) {
	57	maca = __raw_readl(MAC_ID_BASE_ADDR);
	58	macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
	59	}
	60
	61	dev->enetaddr[0] = (macb >> 8) & 0xff;
	62	dev->enetaddr[1] = (macb >> 0) & 0xff;
	63	dev->enetaddr[2] = (maca >> 24) & 0xff;
	64	dev->enetaddr[3] = (maca >> 16) & 0xff;
	65	dev->enetaddr[4] = (maca >> 8) & 0xff;
	66	dev->enetaddr[5] = (maca >> 0) & 0xff;
	67
	68	return 0;
	69	}
	70
550c5ce6 KI	71	/* MDIO */
	72
	73	static int keystone2_mdio_reset(struct mii_dev *bus)
fc9a8e8d	74	{
550c5ce6 KI	75	u_int32_t clkdiv;
550c5ce6 KI	76	struct mdio_regs *adap_mdio = bus->priv;
fc9a8e8d KM	77
	78	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
	79
550c5ce6 KI	80	writel((clkdiv & 0xffff) \| MDIO_CONTROL_ENABLE \|
550c5ce6 KI	81	MDIO_CONTROL_FAULT \| MDIO_CONTROL_FAULT_ENABLE,
fc9a8e8d KM	82	&adap_mdio->control);
	83
	84	while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
	85	;
550c5ce6 KI	86
550c5ce6 KI	87	return 0;
fc9a8e8d KM	88	}
fc9a8e8d KM	89
550c5ce6 KI	90	/**
	91	* keystone2_mdio_read - read a PHY register via MDIO interface.
	92	* Blocks until operation is complete.
	93	*/
	94	static int keystone2_mdio_read(struct mii_dev *bus,
	95	int addr, int devad, int reg)
fc9a8e8d	96	{
550c5ce6 KI	97	int tmp;
550c5ce6 KI	98	struct mdio_regs *adap_mdio = bus->priv;
fc9a8e8d KM	99
	100	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
	101	;
	102
550c5ce6 KI	103	writel(MDIO_USERACCESS0_GO \| MDIO_USERACCESS0_WRITE_READ \|
550c5ce6 KI	104	((reg & 0x1f) << 21) \| ((addr & 0x1f) << 16),
fc9a8e8d KM	105	&adap_mdio->useraccess0);
	106
	107	/* Wait for command to complete */
	108	while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
	109	;
	110
550c5ce6 KI	111	if (tmp & MDIO_USERACCESS0_ACK)
550c5ce6 KI	112	return tmp & 0xffff;
fc9a8e8d	113
fc9a8e8d KM	114	return -1;
	115	}
	116
550c5ce6 KI	117	/**
550c5ce6 KI	118	* keystone2_mdio_write - write to a PHY register via MDIO interface.
fc9a8e8d KM	119	* Blocks until operation is complete.
fc9a8e8d KM	120	*/
550c5ce6 KI	121	static int keystone2_mdio_write(struct mii_dev *bus,
550c5ce6 KI	122	int addr, int devad, int reg, u16 val)
fc9a8e8d	123	{
550c5ce6 KI	124	struct mdio_regs *adap_mdio = bus->priv;
550c5ce6 KI	125
fc9a8e8d KM	126	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
	127	;
	128
550c5ce6 KI	129	writel(MDIO_USERACCESS0_GO \| MDIO_USERACCESS0_WRITE_WRITE \|
	130	((reg & 0x1f) << 21) \| ((addr & 0x1f) << 16) \|
	131	(val & 0xffff), &adap_mdio->useraccess0);
fc9a8e8d KM	132
	133	/* Wait for command to complete */
	134	while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
	135	;
	136
	137	return 0;
	138	}
	139
fc9a8e8d KM	140	static void __attribute__((unused))
	141	keystone2_eth_gigabit_enable(struct eth_device *dev)
	142	{
	143	u_int16_t data;
	144	struct eth_priv_t eth_priv = (struct eth_priv_t )dev->priv;
	145
	146	if (sys_has_mdio) {
550c5ce6 KI	147	data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
	148	MDIO_DEVAD_NONE, 0);
	149	/* speed selection MSB */
	150	if (!(data & (1 << 6)))
fc9a8e8d KM	151	return;
	152	}
	153
	154	/*
	155	* Check if link detected is giga-bit
	156	* If Gigabit mode detected, enable gigbit in MAC
	157	*/
b2cfe322 HZ	158	writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
b2cfe322 HZ	159	CPGMACSL_REG_CTL) \|
fc9a8e8d	160	EMAC_MACCONTROL_GIGFORCE \| EMAC_MACCONTROL_GIGABIT_ENABLE,
b2cfe322	161	DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
fc9a8e8d KM	162	}
	163
	164	int keystone_sgmii_link_status(int port)
	165	{
	166	u32 status = 0;
	167
	168	status = __raw_readl(SGMII_STATUS_REG(port));
	169
a4d2adee KI	170	return (status & SGMII_REG_STATUS_LOCK) &&
a4d2adee KI	171	(status & SGMII_REG_STATUS_LINK);
fc9a8e8d KM	172	}
fc9a8e8d KM	173
c05d05e7	174	int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
fc9a8e8d KM	175	{
	176	unsigned int i, status, mask;
	177	unsigned int mr_adv_ability, control;
	178
	179	switch (interface) {
	180	case SGMII_LINK_MAC_MAC_AUTONEG:
	181	mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE \|
	182	SGMII_REG_MR_ADV_LINK \|
	183	SGMII_REG_MR_ADV_FULL_DUPLEX \|
	184	SGMII_REG_MR_ADV_GIG_MODE);
	185	control = (SGMII_REG_CONTROL_MASTER \|
	186	SGMII_REG_CONTROL_AUTONEG);
	187
	188	break;
	189	case SGMII_LINK_MAC_PHY:
	190	case SGMII_LINK_MAC_PHY_FORCED:
	191	mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
	192	control = SGMII_REG_CONTROL_AUTONEG;
	193
	194	break;
	195	case SGMII_LINK_MAC_MAC_FORCED:
	196	mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE \|
	197	SGMII_REG_MR_ADV_LINK \|
	198	SGMII_REG_MR_ADV_FULL_DUPLEX \|
	199	SGMII_REG_MR_ADV_GIG_MODE);
	200	control = SGMII_REG_CONTROL_MASTER;
	201
	202	break;
	203	case SGMII_LINK_MAC_FIBER:
	204	mr_adv_ability = 0x20;
	205	control = SGMII_REG_CONTROL_AUTONEG;
	206
	207	break;
	208	default:
	209	mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
	210	control = SGMII_REG_CONTROL_AUTONEG;
	211	}
	212
	213	__raw_writel(0, SGMII_CTL_REG(port));
	214
	215	/*
	216	* Wait for the SerDes pll to lock,
	217	* but don't trap if lock is never read
	218	*/
	219	for (i = 0; i < 1000; i++) {
	220	udelay(2000);
	221	status = __raw_readl(SGMII_STATUS_REG(port));
	222	if ((status & SGMII_REG_STATUS_LOCK) != 0)
	223	break;
	224	}
	225
	226	__raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
	227	__raw_writel(control, SGMII_CTL_REG(port));
	228
	229
	230	mask = SGMII_REG_STATUS_LINK;
	231
	232	if (control & SGMII_REG_CONTROL_AUTONEG)
	233	mask \|= SGMII_REG_STATUS_AUTONEG;
	234
c05d05e7 KI	235	status = __raw_readl(SGMII_STATUS_REG(port));
	236	if ((status & mask) == mask)
	237	return 0;
	238
	239	printf("\n%s Waiting for SGMII auto negotiation to complete",
	240	phy_dev->dev->name);
	241	while ((status & mask) != mask) {
	242	/*
	243	* Timeout reached ?
	244	*/
	245	if (i > SGMII_ANEG_TIMEOUT) {
	246	puts(" TIMEOUT !\n");
	247	phy_dev->link = 0;
	248	return 0;
	249	}
	250
	251	if (ctrlc()) {
	252	puts("user interrupt!\n");
	253	phy_dev->link = 0;
	254	return -EINTR;
	255	}
	256
	257	if ((i++ % 500) == 0)
	258	printf(".");
	259
	260	udelay(1000); /* 1 ms */
fc9a8e8d	261	status = __raw_readl(SGMII_STATUS_REG(port));
fc9a8e8d	262	}
c05d05e7	263	puts(" done\n");
fc9a8e8d KM	264
	265	return 0;
	266	}
	267
	268	int mac_sl_reset(u32 port)
	269	{
	270	u32 i, v;
	271
	272	if (port >= DEVICE_N_GMACSL_PORTS)
	273	return GMACSL_RET_INVALID_PORT;
	274
	275	/* Set the soft reset bit */
e6c9428a KI	276	writel(CPGMAC_REG_RESET_VAL_RESET,
e6c9428a KI	277	DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
fc9a8e8d KM	278
	279	/* Wait for the bit to clear */
	280	for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
e6c9428a	281	v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
fc9a8e8d KM	282	if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
	283	CPGMAC_REG_RESET_VAL_RESET)
	284	return GMACSL_RET_OK;
	285	}
	286
	287	/* Timeout on the reset */
	288	return GMACSL_RET_WARN_RESET_INCOMPLETE;
	289	}
	290
	291	int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
	292	{
	293	u32 v, i;
	294	int ret = GMACSL_RET_OK;
	295
	296	if (port >= DEVICE_N_GMACSL_PORTS)
	297	return GMACSL_RET_INVALID_PORT;
	298
	299	if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
	300	cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
	301	ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
	302	}
	303
	304	/* Must wait if the device is undergoing reset */
	305	for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
e6c9428a	306	v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
fc9a8e8d KM	307	if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
	308	CPGMAC_REG_RESET_VAL_RESET)
	309	break;
	310	}
	311
	312	if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
	313	return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
	314
e6c9428a KI	315	writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
e6c9428a KI	316	writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
fc9a8e8d	317
ff11c769 KI	318	#ifdef CONFIG_K2E_EVM
	319	/* Map RX packet flow priority to 0 */
	320	writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
	321	#endif
	322
fc9a8e8d KM	323	return ret;
	324	}
	325
	326	int ethss_config(u32 ctl, u32 max_pkt_size)
	327	{
	328	u32 i;
	329
	330	/* Max length register */
e6c9428a	331	writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
fc9a8e8d KM	332
fc9a8e8d KM	333	/* Control register */
e6c9428a	334	writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
fc9a8e8d KM	335
fc9a8e8d KM	336	/* All statistics enabled by default */
e6c9428a KI	337	writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
e6c9428a KI	338	DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
fc9a8e8d KM	339
fc9a8e8d KM	340	/* Reset and enable the ALE */
e6c9428a KI	341	writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE \|
	342	CPSW_REG_VAL_ALE_CTL_BYPASS,
	343	DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
fc9a8e8d KM	344
	345	/* All ports put into forward mode */
	346	for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
e6c9428a KI	347	writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
e6c9428a KI	348	DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
fc9a8e8d KM	349
	350	return 0;
	351	}
	352
	353	int ethss_start(void)
	354	{
	355	int i;
	356	struct mac_sl_cfg cfg;
	357
	358	cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
	359	cfg.ctl = GMACSL_ENABLE \| GMACSL_RX_ENABLE_EXT_CTL;
	360
	361	for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
	362	mac_sl_reset(i);
	363	mac_sl_config(i, &cfg);
	364	}
	365
	366	return 0;
	367	}
	368
	369	int ethss_stop(void)
	370	{
	371	int i;
	372
	373	for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
	374	mac_sl_reset(i);
	375
	376	return 0;
	377	}
	378
	379	int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
	380	{
	381	if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
	382	num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
	383
9ea9021a KI	384	return ksnav_send(&netcp_pktdma, buffer,
9ea9021a KI	385	num_bytes, (slave_port_num) << 16);
fc9a8e8d KM	386	}
	387
	388	/* Eth device open */
	389	static int keystone2_eth_open(struct eth_device dev, bd_t bis)
	390	{
fc9a8e8d	391	struct eth_priv_t eth_priv = (struct eth_priv_t )dev->priv;
3fe93623	392	struct phy_device *phy_dev = eth_priv->phy_dev;
fc9a8e8d KM	393
	394	debug("+ emac_open\n");
	395
	396	net_rx_buffs.rx_flow = eth_priv->rx_flow;
	397
	398	sys_has_mdio =
	399	(eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
	400
a43febde	401	keystone2_net_serdes_setup();
fc9a8e8d	402
c05d05e7	403	keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
fc9a8e8d KM	404	eth_priv->sgmii_link_type);
	405
	406	udelay(10000);
	407
	408	/* On chip switch configuration */
	409	ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
	410
	411	/* TODO: add error handling code */
	412	if (qm_init()) {
	413	printf("ERROR: qm_init()\n");
	414	return -1;
	415	}
9ea9021a	416	if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
fc9a8e8d KM	417	qm_close();
	418	printf("ERROR: netcp_init()\n");
	419	return -1;
	420	}
	421
	422	/*
	423	* Streaming switch configuration. If not present this
	424	* statement is defined to void in target.h.
	425	* If present this is usually defined to a series of register writes
	426	*/
	427	hw_config_streaming_switch();
	428
	429	if (sys_has_mdio) {
550c5ce6	430	keystone2_mdio_reset(mdio_bus);
fc9a8e8d	431
3fe93623 KI	432	phy_startup(phy_dev);
3fe93623 KI	433	if (phy_dev->link == 0) {
9ea9021a	434	ksnav_close(&netcp_pktdma);
fc9a8e8d KM	435	qm_close();
	436	return -1;
	437	}
	438	}
	439
	440	emac_gigabit_enable(dev);
	441
	442	ethss_start();
	443
	444	debug("- emac_open\n");
	445
	446	emac_open = 1;
	447
	448	return 0;
	449	}
	450
	451	/* Eth device close */
	452	void keystone2_eth_close(struct eth_device *dev)
	453	{
3fe93623 KI	454	struct eth_priv_t eth_priv = (struct eth_priv_t )dev->priv;
	455	struct phy_device *phy_dev = eth_priv->phy_dev;
	456
fc9a8e8d KM	457	debug("+ emac_close\n");
	458
	459	if (!emac_open)
	460	return;
	461
	462	ethss_stop();
	463
9ea9021a	464	ksnav_close(&netcp_pktdma);
fc9a8e8d	465	qm_close();
3fe93623	466	phy_shutdown(phy_dev);
fc9a8e8d KM	467
	468	emac_open = 0;
	469
	470	debug("- emac_close\n");
	471	}
	472
fc9a8e8d KM	473	/*
	474	* This function sends a single packet on the network and returns
	475	* positive number (number of bytes transmitted) or negative for error
	476	*/
	477	static int keystone2_eth_send_packet(struct eth_device *dev,
	478	void *packet, int length)
	479	{
	480	int ret_status = -1;
	481	struct eth_priv_t eth_priv = (struct eth_priv_t )dev->priv;
a4d2adee	482	struct phy_device *phy_dev = eth_priv->phy_dev;
fc9a8e8d	483
a4d2adee KI	484	genphy_update_link(phy_dev);
a4d2adee KI	485	if (phy_dev->link == 0)
fc9a8e8d KM	486	return -1;
fc9a8e8d KM	487
fc9a8e8d KM	488	if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
	489	return ret_status;
	490
fc9a8e8d KM	491	return length;
	492	}
	493
	494	/*
	495	* This function handles receipt of a packet from the network
	496	*/
	497	static int keystone2_eth_rcv_packet(struct eth_device *dev)
	498	{
	499	void *hd;
	500	int pkt_size;
	501	u32 *pkt;
	502
9ea9021a	503	hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
fc9a8e8d KM	504	if (hd == NULL)
	505	return 0;
	506
	507	NetReceive((uchar *)pkt, pkt_size);
	508
9ea9021a	509	ksnav_release_rxhd(&netcp_pktdma, hd);
fc9a8e8d KM	510
	511	return pkt_size;
	512	}
	513
	514	/*
	515	* This function initializes the EMAC hardware.
	516	*/
	517	int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
	518	{
550c5ce6	519	int res;
fc9a8e8d	520	struct eth_device *dev;
3fe93623	521	struct phy_device *phy_dev;
fc9a8e8d KM	522
	523	dev = malloc(sizeof(struct eth_device));
	524	if (dev == NULL)
	525	return -1;
	526
	527	memset(dev, 0, sizeof(struct eth_device));
	528
	529	strcpy(dev->name, eth_priv->int_name);
	530	dev->priv = eth_priv;
	531
	532	keystone2_eth_read_mac_addr(dev);
	533
	534	dev->iobase = 0;
	535	dev->init = keystone2_eth_open;
	536	dev->halt = keystone2_eth_close;
	537	dev->send = keystone2_eth_send_packet;
	538	dev->recv = keystone2_eth_rcv_packet;
	539
	540	eth_register(dev);
	541
550c5ce6 KI	542	/* Register MDIO bus if it's not registered yet */
	543	if (!mdio_bus) {
	544	mdio_bus = mdio_alloc();
	545	mdio_bus->read = keystone2_mdio_read;
	546	mdio_bus->write = keystone2_mdio_write;
	547	mdio_bus->reset = keystone2_mdio_reset;
	548	mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
	549	sprintf(mdio_bus->name, "ethernet-mdio");
	550
	551	res = mdio_register(mdio_bus);
	552	if (res)
	553	return res;
	554	}
	555
3fe93623 KI	556	/* Create phy device and bind it with driver */
	557	#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
	558	phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
	559	dev, PHY_INTERFACE_MODE_SGMII);
	560	phy_config(phy_dev);
	561	#else
	562	phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
	563	PHY_INTERFACE_MODE_SGMII);
	564	phy_dev->dev = dev;
	565	#endif
	566	eth_priv->phy_dev = phy_dev;
	567
fc9a8e8d KM	568	return 0;
	569	}
	570
92a16c81 HZ	571	struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
	572	.clk = SERDES_CLOCK_156P25M,
	573	.rate = SERDES_RATE_5G,
	574	.rate_mode = SERDES_QUARTER_RATE,
	575	.intf = SERDES_PHY_SGMII,
	576	.loopback = 0,
	577	};
	578
a43febde	579	static void keystone2_net_serdes_setup(void)
fc9a8e8d	580	{
92a16c81 HZ	581	ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
	582	&ks2_serdes_sgmii_156p25mhz,
	583	CONFIG_KSNET_SERDES_LANES_PER_SGMII);
	584
87ac27bd	585	#if defined(CONFIG_SOC_K2E) \|\| defined(CONFIG_SOC_K2L)
3c61502a KI	586	ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
	587	&ks2_serdes_sgmii_156p25mhz,
	588	CONFIG_KSNET_SERDES_LANES_PER_SGMII);
	589	#endif
	590
92a16c81 HZ	591	/* wait till setup */
92a16c81 HZ	592	udelay(5000);
fc9a8e8d	593	}