[thirdparty/u-boot.git] / drivers / net / ldpaa_eth / ldpaa_wriop.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015 Freescale Semiconductor
 */

#include <common.h>
#include <asm/io.h>
#include <asm/types.h>
#include <malloc.h>
#include <net.h>
#include <linux/compat.h>
#include <asm/arch/fsl_serdes.h>
#include <fsl-mc/ldpaa_wriop.h>

struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];

__weak phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtc)
{
	return PHY_INTERFACE_MODE_NA;
}

void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
{
	phy_interface_t enet_if;
	int phy_num;

	dpmac_info[dpmac_id].enabled = 0;
	dpmac_info[dpmac_id].id = 0;
	dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NA;

	enet_if = wriop_dpmac_enet_if(dpmac_id, lane_prtcl);
	if (enet_if != PHY_INTERFACE_MODE_NA) {
		dpmac_info[dpmac_id].enabled = 1;
		dpmac_info[dpmac_id].id = dpmac_id;
		dpmac_info[dpmac_id].enet_if = enet_if;
	}
	for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
		dpmac_info[dpmac_id].phydev[phy_num] = NULL;
		dpmac_info[dpmac_id].phy_addr[phy_num] = -1;
	}
}

void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if)
{
	int phy_num;

	dpmac_info[dpmac_id].enabled = 1;
	dpmac_info[dpmac_id].id = dpmac_id;
	dpmac_info[dpmac_id].enet_if = enet_if;
	for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
		dpmac_info[dpmac_id].phydev[phy_num] = NULL;
		dpmac_info[dpmac_id].phy_addr[phy_num] = -1;
	}
}


/*TODO what it do */
static int wriop_dpmac_to_index(int dpmac_id)
{
	int i;

	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
		if (dpmac_info[i].id == dpmac_id)
			return i;
	}

	return -1;
}

int wriop_disable_dpmac(int dpmac_id)
{
	int i = wriop_dpmac_to_index(dpmac_id);

	if (i == -1)
		return -ENODEV;

	dpmac_info[i].enabled = 0;
	wriop_dpmac_disable(dpmac_id);

	return 0;
}

int wriop_enable_dpmac(int dpmac_id)
{
	int i = wriop_dpmac_to_index(dpmac_id);

	if (i == -1)
		return -ENODEV;

	dpmac_info[i].enabled = 1;
	wriop_dpmac_enable(dpmac_id);

	return 0;
}

int wriop_is_enabled_dpmac(int dpmac_id)
{
	int i = wriop_dpmac_to_index(dpmac_id);

	if (i == -1)
		return -ENODEV;

	return dpmac_info[i].enabled;
}


int wriop_set_mdio(int dpmac_id, struct mii_dev *bus)
{
	int i = wriop_dpmac_to_index(dpmac_id);

	if (i == -1)
		return -ENODEV;

	dpmac_info[i].bus = bus;

	return 0;
}

struct mii_dev *wriop_get_mdio(int dpmac_id)
{
	int i = wriop_dpmac_to_index(dpmac_id);

	if (i == -1)
		return NULL;

	return dpmac_info[i].bus;
}

int wriop_set_phy_address(int dpmac_id, int phy_num, int address)
{
	int i = wriop_dpmac_to_index(dpmac_id);

	if (i == -1)
		return -ENODEV;
	if (phy_num < 0 || phy_num >= WRIOP_MAX_PHY_NUM)
		return -EINVAL;

	dpmac_info[i].phy_addr[phy_num] = address;

	return 0;
}

int wriop_get_phy_address(int dpmac_id, int phy_num)
{
	int i = wriop_dpmac_to_index(dpmac_id);

	if (i == -1)
		return -ENODEV;
	if (phy_num < 0 || phy_num >= WRIOP_MAX_PHY_NUM)
		return -EINVAL;

	return dpmac_info[i].phy_addr[phy_num];
}

int wriop_set_phy_dev(int dpmac_id, int phy_num, struct phy_device *phydev)
{
	int i = wriop_dpmac_to_index(dpmac_id);

	if (i == -1)
		return -ENODEV;
	if (phy_num < 0 || phy_num >= WRIOP_MAX_PHY_NUM)
		return -EINVAL;

	dpmac_info[i].phydev[phy_num] = phydev;

	return 0;
}

struct phy_device *wriop_get_phy_dev(int dpmac_id, int phy_num)
{
	int i = wriop_dpmac_to_index(dpmac_id);

	if (i == -1)
		return NULL;
	if (phy_num < 0 || phy_num >= WRIOP_MAX_PHY_NUM)
		return NULL;

	return dpmac_info[i].phydev[phy_num];
}

phy_interface_t wriop_get_enet_if(int dpmac_id)
{
	int i = wriop_dpmac_to_index(dpmac_id);

	if (i == -1)
		return PHY_INTERFACE_MODE_NA;

	if (dpmac_info[i].enabled)
		return dpmac_info[i].enet_if;

	return PHY_INTERFACE_MODE_NA;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
9cc2c471 PK	2	/*
9cc2c471 PK	3	* Copyright (C) 2015 Freescale Semiconductor
9cc2c471 PK	4	*/
9cc2c471 PK	5
d678a59d	6	#include <common.h>
9cc2c471 PK	7	#include <asm/io.h>
	8	#include <asm/types.h>
	9	#include <malloc.h>
	10	#include <net.h>
	11	#include <linux/compat.h>
	12	#include <asm/arch/fsl_serdes.h>
	13	#include <fsl-mc/ldpaa_wriop.h>
	14
	15	struct wriop_dpmac_info dpmac_info[NUM_WRIOP_PORTS];
	16
	17	__weak phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtc)
	18	{
ffb0f6f4	19	return PHY_INTERFACE_MODE_NA;
9cc2c471 PK	20	}
	21
	22	void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
	23	{
	24	phy_interface_t enet_if;
1a048cd6	25	int phy_num;
9cc2c471	26
99e904c1 PK	27	dpmac_info[dpmac_id].enabled = 0;
99e904c1 PK	28	dpmac_info[dpmac_id].id = 0;
ffb0f6f4	29	dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NA;
9cc2c471	30
99e904c1	31	enet_if = wriop_dpmac_enet_if(dpmac_id, lane_prtcl);
ffb0f6f4	32	if (enet_if != PHY_INTERFACE_MODE_NA) {
99e904c1 PK	33	dpmac_info[dpmac_id].enabled = 1;
	34	dpmac_info[dpmac_id].id = dpmac_id;
	35	dpmac_info[dpmac_id].enet_if = enet_if;
9cc2c471	36	}
1a048cd6 PB	37	for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
	38	dpmac_info[dpmac_id].phydev[phy_num] = NULL;
	39	dpmac_info[dpmac_id].phy_addr[phy_num] = -1;
	40	}
9cc2c471 PK	41	}
9cc2c471 PK	42
17d066fc AK	43	void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if)
17d066fc AK	44	{
1a048cd6 PB	45	int phy_num;
1a048cd6 PB	46
17d066fc AK	47	dpmac_info[dpmac_id].enabled = 1;
17d066fc AK	48	dpmac_info[dpmac_id].id = dpmac_id;
17d066fc	49	dpmac_info[dpmac_id].enet_if = enet_if;
1a048cd6 PB	50	for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
	51	dpmac_info[dpmac_id].phydev[phy_num] = NULL;
	52	dpmac_info[dpmac_id].phy_addr[phy_num] = -1;
	53	}
17d066fc AK	54	}
	55
	56
9cc2c471 PK	57	/TODO what it do /
	58	static int wriop_dpmac_to_index(int dpmac_id)
	59	{
	60	int i;
	61
	62	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
	63	if (dpmac_info[i].id == dpmac_id)
	64	return i;
	65	}
	66
	67	return -1;
	68	}
	69
1a048cd6	70	int wriop_disable_dpmac(int dpmac_id)
9cc2c471 PK	71	{
	72	int i = wriop_dpmac_to_index(dpmac_id);
	73
	74	if (i == -1)
1a048cd6	75	return -ENODEV;
9cc2c471 PK	76
	77	dpmac_info[i].enabled = 0;
	78	wriop_dpmac_disable(dpmac_id);
1a048cd6 PB	79
1a048cd6 PB	80	return 0;
9cc2c471 PK	81	}
9cc2c471 PK	82
1a048cd6	83	int wriop_enable_dpmac(int dpmac_id)
9cc2c471 PK	84	{
	85	int i = wriop_dpmac_to_index(dpmac_id);
	86
	87	if (i == -1)
1a048cd6	88	return -ENODEV;
9cc2c471 PK	89
	90	dpmac_info[i].enabled = 1;
	91	wriop_dpmac_enable(dpmac_id);
1a048cd6 PB	92
1a048cd6 PB	93	return 0;
9cc2c471 PK	94	}
9cc2c471 PK	95
1a048cd6	96	int wriop_is_enabled_dpmac(int dpmac_id)
f9127a04 PK	97	{
	98	int i = wriop_dpmac_to_index(dpmac_id);
	99
	100	if (i == -1)
1a048cd6	101	return -ENODEV;
f9127a04 PK	102
	103	return dpmac_info[i].enabled;
	104	}
	105
	106
1a048cd6	107	int wriop_set_mdio(int dpmac_id, struct mii_dev *bus)
9cc2c471 PK	108	{
	109	int i = wriop_dpmac_to_index(dpmac_id);
	110
	111	if (i == -1)
1a048cd6	112	return -ENODEV;
9cc2c471 PK	113
9cc2c471 PK	114	dpmac_info[i].bus = bus;
1a048cd6 PB	115
1a048cd6 PB	116	return 0;
9cc2c471 PK	117	}
	118
	119	struct mii_dev *wriop_get_mdio(int dpmac_id)
	120	{
	121	int i = wriop_dpmac_to_index(dpmac_id);
	122
	123	if (i == -1)
	124	return NULL;
	125
	126	return dpmac_info[i].bus;
	127	}
	128
1a048cd6	129	int wriop_set_phy_address(int dpmac_id, int phy_num, int address)
9cc2c471 PK	130	{
	131	int i = wriop_dpmac_to_index(dpmac_id);
	132
	133	if (i == -1)
1a048cd6 PB	134	return -ENODEV;
	135	if (phy_num < 0 \|\| phy_num >= WRIOP_MAX_PHY_NUM)
	136	return -EINVAL;
	137
	138	dpmac_info[i].phy_addr[phy_num] = address;
9cc2c471	139
1a048cd6	140	return 0;
9cc2c471 PK	141	}
9cc2c471 PK	142
1a048cd6	143	int wriop_get_phy_address(int dpmac_id, int phy_num)
9cc2c471 PK	144	{
	145	int i = wriop_dpmac_to_index(dpmac_id);
	146
	147	if (i == -1)
1a048cd6 PB	148	return -ENODEV;
	149	if (phy_num < 0 \|\| phy_num >= WRIOP_MAX_PHY_NUM)
	150	return -EINVAL;
9cc2c471	151
1a048cd6	152	return dpmac_info[i].phy_addr[phy_num];
9cc2c471 PK	153	}
9cc2c471 PK	154
1a048cd6	155	int wriop_set_phy_dev(int dpmac_id, int phy_num, struct phy_device *phydev)
9cc2c471 PK	156	{
	157	int i = wriop_dpmac_to_index(dpmac_id);
	158
	159	if (i == -1)
1a048cd6 PB	160	return -ENODEV;
	161	if (phy_num < 0 \|\| phy_num >= WRIOP_MAX_PHY_NUM)
	162	return -EINVAL;
9cc2c471	163
1a048cd6 PB	164	dpmac_info[i].phydev[phy_num] = phydev;
	165
	166	return 0;
9cc2c471 PK	167	}
9cc2c471 PK	168
1a048cd6	169	struct phy_device *wriop_get_phy_dev(int dpmac_id, int phy_num)
9cc2c471 PK	170	{
	171	int i = wriop_dpmac_to_index(dpmac_id);
	172
	173	if (i == -1)
	174	return NULL;
1a048cd6 PB	175	if (phy_num < 0 \|\| phy_num >= WRIOP_MAX_PHY_NUM)
1a048cd6 PB	176	return NULL;
9cc2c471	177
1a048cd6	178	return dpmac_info[i].phydev[phy_num];
9cc2c471 PK	179	}
	180
	181	phy_interface_t wriop_get_enet_if(int dpmac_id)
	182	{
	183	int i = wriop_dpmac_to_index(dpmac_id);
	184
	185	if (i == -1)
ffb0f6f4	186	return PHY_INTERFACE_MODE_NA;
9cc2c471 PK	187
	188	if (dpmac_info[i].enabled)
	189	return dpmac_info[i].enet_if;
	190
ffb0f6f4	191	return PHY_INTERFACE_MODE_NA;
9cc2c471	192	}