[thirdparty/u-boot.git] / drivers / net / ldpaa_eth / ls1088a.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2017 NXP
 */
#include <common.h>
#include <phy.h>
#include <fsl-mc/ldpaa_wriop.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <linux/mii.h>

u32 dpmac_to_devdisr[] = {
	[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
	[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
	[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
	[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
	[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
	[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
	[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
	[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
	[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
	[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
};

static int is_device_disabled(int dpmac_id)
{
	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
	u32 devdisr2 = in_le32(&gur->devdisr2);

	return dpmac_to_devdisr[dpmac_id] & devdisr2;
}

void wriop_dpmac_disable(int dpmac_id)
{
	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;

	setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}

void wriop_dpmac_enable(int dpmac_id)
{
	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;

	clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}

phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
{
	enum srds_prtcl;

	if (is_device_disabled(dpmac_id + 1))
		return PHY_INTERFACE_MODE_NA;

	switch (lane_prtcl) {
	case SGMII1:
	case SGMII2:
	case SGMII3:
	case SGMII7:
		return PHY_INTERFACE_MODE_SGMII;
	}

	if (lane_prtcl >= XFI1 && lane_prtcl <= XFI2)
		return PHY_INTERFACE_MODE_XGMII;

	if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_B)
		return PHY_INTERFACE_MODE_QSGMII;

	return PHY_INTERFACE_MODE_NA;
}

void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
{
	switch (lane_prtcl) {
	case QSGMII_A:
		wriop_init_dpmac(sd, 3, (int)lane_prtcl);
		wriop_init_dpmac(sd, 4, (int)lane_prtcl);
		wriop_init_dpmac(sd, 5, (int)lane_prtcl);
		wriop_init_dpmac(sd, 6, (int)lane_prtcl);
		break;
	case QSGMII_B:
		wriop_init_dpmac(sd, 7, (int)lane_prtcl);
		wriop_init_dpmac(sd, 8, (int)lane_prtcl);
		wriop_init_dpmac(sd, 9, (int)lane_prtcl);
		wriop_init_dpmac(sd, 10, (int)lane_prtcl);
		break;
	}
}

#ifdef CONFIG_SYS_FSL_HAS_RGMII
void fsl_rgmii_init(void)
{
	struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
	u32 ec;

#ifdef CONFIG_SYS_FSL_EC1
	ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR])
		& FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;
	ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;

	if (!ec)
		wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII_ID);
#endif

#ifdef CONFIG_SYS_FSL_EC2
	ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR])
		& FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;
	ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;

	if (!ec)
		wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII_ID);
#endif
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
6d9b82d0 AK	2	/*
6d9b82d0 AK	3	* Copyright 2017 NXP
6d9b82d0	4	*/
d678a59d	5	#include <common.h>
6d9b82d0 AK	6	#include <phy.h>
	7	#include <fsl-mc/ldpaa_wriop.h>
	8	#include <asm/io.h>
	9	#include <asm/arch/fsl_serdes.h>
17d066fc	10	#include <asm/arch/soc.h>
68a6aa85	11	#include <linux/mii.h>
6d9b82d0 AK	12
	13	u32 dpmac_to_devdisr[] = {
	14	[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
	15	[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
	16	[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
	17	[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
	18	[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
	19	[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
	20	[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
	21	[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
	22	[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
	23	[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
	24	};
	25
	26	static int is_device_disabled(int dpmac_id)
	27	{
6cc04547	28	struct ccsr_gur __iomem gur = (void )CFG_SYS_FSL_GUTS_ADDR;
6d9b82d0 AK	29	u32 devdisr2 = in_le32(&gur->devdisr2);
	30
	31	return dpmac_to_devdisr[dpmac_id] & devdisr2;
	32	}
	33
	34	void wriop_dpmac_disable(int dpmac_id)
	35	{
6cc04547	36	struct ccsr_gur __iomem gur = (void )CFG_SYS_FSL_GUTS_ADDR;
6d9b82d0 AK	37
	38	setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
	39	}
	40
	41	void wriop_dpmac_enable(int dpmac_id)
	42	{
6cc04547	43	struct ccsr_gur __iomem gur = (void )CFG_SYS_FSL_GUTS_ADDR;
6d9b82d0 AK	44
	45	clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
	46	}
	47
	48	phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
	49	{
	50	enum srds_prtcl;
	51
	52	if (is_device_disabled(dpmac_id + 1))
ffb0f6f4	53	return PHY_INTERFACE_MODE_NA;
6d9b82d0 AK	54
	55	switch (lane_prtcl) {
	56	case SGMII1:
	57	case SGMII2:
	58	case SGMII3:
	59	case SGMII7:
	60	return PHY_INTERFACE_MODE_SGMII;
	61	}
	62
	63	if (lane_prtcl >= XFI1 && lane_prtcl <= XFI2)
	64	return PHY_INTERFACE_MODE_XGMII;
	65
	66	if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_B)
	67	return PHY_INTERFACE_MODE_QSGMII;
	68
ffb0f6f4	69	return PHY_INTERFACE_MODE_NA;
6d9b82d0 AK	70	}
	71
	72	void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
	73	{
	74	switch (lane_prtcl) {
	75	case QSGMII_A:
	76	wriop_init_dpmac(sd, 3, (int)lane_prtcl);
	77	wriop_init_dpmac(sd, 4, (int)lane_prtcl);
	78	wriop_init_dpmac(sd, 5, (int)lane_prtcl);
	79	wriop_init_dpmac(sd, 6, (int)lane_prtcl);
	80	break;
	81	case QSGMII_B:
	82	wriop_init_dpmac(sd, 7, (int)lane_prtcl);
	83	wriop_init_dpmac(sd, 8, (int)lane_prtcl);
	84	wriop_init_dpmac(sd, 9, (int)lane_prtcl);
	85	wriop_init_dpmac(sd, 10, (int)lane_prtcl);
	86	break;
	87	}
	88	}
17d066fc AK	89
	90	#ifdef CONFIG_SYS_FSL_HAS_RGMII
	91	void fsl_rgmii_init(void)
	92	{
6cc04547	93	struct ccsr_gur __iomem gur = (void )(CFG_SYS_FSL_GUTS_ADDR);
17d066fc AK	94	u32 ec;
	95
	96	#ifdef CONFIG_SYS_FSL_EC1
ba7eadd8	97	ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR])
17d066fc AK	98	& FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;
	99	ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
	100
	101	if (!ec)
2af1b08a	102	wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII_ID);
17d066fc AK	103	#endif
	104
	105	#ifdef CONFIG_SYS_FSL_EC2
ba7eadd8	106	ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR])
17d066fc AK	107	& FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;
	108	ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
	109
	110	if (!ec)
2af1b08a	111	wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII_ID);
17d066fc AK	112	#endif
	113	}
	114	#endif