[thirdparty/u-boot.git] / drivers / net / ldpaa_eth / ls2080a.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 */
#include <common.h>
#include <phy.h>
#include <fsl-mc/ldpaa_wriop.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>

u32 dpmac_to_devdisr[] = {
	[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
	[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
	[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
	[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
	[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
	[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
	[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
	[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
	[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
	[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
	[WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
	[WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
	[WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
	[WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
	[WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
	[WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
	[WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
	[WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
	[WRIOP1_DPMAC19] = FSL_CHASSIS3_DEVDISR2_DPMAC19,
	[WRIOP1_DPMAC20] = FSL_CHASSIS3_DEVDISR2_DPMAC20,
	[WRIOP1_DPMAC21] = FSL_CHASSIS3_DEVDISR2_DPMAC21,
	[WRIOP1_DPMAC22] = FSL_CHASSIS3_DEVDISR2_DPMAC22,
	[WRIOP1_DPMAC23] = FSL_CHASSIS3_DEVDISR2_DPMAC23,
	[WRIOP1_DPMAC24] = FSL_CHASSIS3_DEVDISR2_DPMAC24,
};

static int is_device_disabled(int dpmac_id)
{
	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
	u32 devdisr2 = in_le32(&gur->devdisr2);

	return dpmac_to_devdisr[dpmac_id] & devdisr2;
}

void wriop_dpmac_disable(int dpmac_id)
{
	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;

	setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}

void wriop_dpmac_enable(int dpmac_id)
{
	struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;

	clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
}

phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
{
	enum srds_prtcl;

	if (is_device_disabled(dpmac_id + 1))
		return PHY_INTERFACE_MODE_NA;

	if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16)
		return PHY_INTERFACE_MODE_SGMII;

	if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
		return PHY_INTERFACE_MODE_XGMII;

	if (lane_prtcl >= XAUI1 && lane_prtcl <= XAUI2)
		return PHY_INTERFACE_MODE_XGMII;

	if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D)
		return PHY_INTERFACE_MODE_QSGMII;

	return PHY_INTERFACE_MODE_NA;
}

void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
{
	switch (lane_prtcl) {
	case QSGMII_A:
		wriop_init_dpmac(sd, 5, (int)lane_prtcl);
		wriop_init_dpmac(sd, 6, (int)lane_prtcl);
		wriop_init_dpmac(sd, 7, (int)lane_prtcl);
		wriop_init_dpmac(sd, 8, (int)lane_prtcl);
		break;
	case QSGMII_B:
		wriop_init_dpmac(sd, 1, (int)lane_prtcl);
		wriop_init_dpmac(sd, 2, (int)lane_prtcl);
		wriop_init_dpmac(sd, 3, (int)lane_prtcl);
		wriop_init_dpmac(sd, 4, (int)lane_prtcl);
		break;
	case QSGMII_C:
		wriop_init_dpmac(sd, 13, (int)lane_prtcl);
		wriop_init_dpmac(sd, 14, (int)lane_prtcl);
		wriop_init_dpmac(sd, 15, (int)lane_prtcl);
		wriop_init_dpmac(sd, 16, (int)lane_prtcl);
		break;
	case QSGMII_D:
		wriop_init_dpmac(sd, 9, (int)lane_prtcl);
		wriop_init_dpmac(sd, 10, (int)lane_prtcl);
		wriop_init_dpmac(sd, 11, (int)lane_prtcl);
		wriop_init_dpmac(sd, 12, (int)lane_prtcl);
		break;
	}
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
e60476a0 PK	2	/*
e60476a0 PK	3	* Copyright 2015 Freescale Semiconductor, Inc.
e60476a0	4	*/
d678a59d	5	#include <common.h>
e60476a0 PK	6	#include <phy.h>
	7	#include <fsl-mc/ldpaa_wriop.h>
	8	#include <asm/io.h>
e60476a0	9	#include <asm/arch/fsl_serdes.h>
e60476a0 PK	10
	11	u32 dpmac_to_devdisr[] = {
	12	[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
	13	[WRIOP1_DPMAC2] = FSL_CHASSIS3_DEVDISR2_DPMAC2,
	14	[WRIOP1_DPMAC3] = FSL_CHASSIS3_DEVDISR2_DPMAC3,
	15	[WRIOP1_DPMAC4] = FSL_CHASSIS3_DEVDISR2_DPMAC4,
	16	[WRIOP1_DPMAC5] = FSL_CHASSIS3_DEVDISR2_DPMAC5,
	17	[WRIOP1_DPMAC6] = FSL_CHASSIS3_DEVDISR2_DPMAC6,
	18	[WRIOP1_DPMAC7] = FSL_CHASSIS3_DEVDISR2_DPMAC7,
	19	[WRIOP1_DPMAC8] = FSL_CHASSIS3_DEVDISR2_DPMAC8,
	20	[WRIOP1_DPMAC9] = FSL_CHASSIS3_DEVDISR2_DPMAC9,
	21	[WRIOP1_DPMAC10] = FSL_CHASSIS3_DEVDISR2_DPMAC10,
	22	[WRIOP1_DPMAC11] = FSL_CHASSIS3_DEVDISR2_DPMAC11,
	23	[WRIOP1_DPMAC12] = FSL_CHASSIS3_DEVDISR2_DPMAC12,
	24	[WRIOP1_DPMAC13] = FSL_CHASSIS3_DEVDISR2_DPMAC13,
	25	[WRIOP1_DPMAC14] = FSL_CHASSIS3_DEVDISR2_DPMAC14,
	26	[WRIOP1_DPMAC15] = FSL_CHASSIS3_DEVDISR2_DPMAC15,
	27	[WRIOP1_DPMAC16] = FSL_CHASSIS3_DEVDISR2_DPMAC16,
	28	[WRIOP1_DPMAC17] = FSL_CHASSIS3_DEVDISR2_DPMAC17,
	29	[WRIOP1_DPMAC18] = FSL_CHASSIS3_DEVDISR2_DPMAC18,
	30	[WRIOP1_DPMAC19] = FSL_CHASSIS3_DEVDISR2_DPMAC19,
	31	[WRIOP1_DPMAC20] = FSL_CHASSIS3_DEVDISR2_DPMAC20,
	32	[WRIOP1_DPMAC21] = FSL_CHASSIS3_DEVDISR2_DPMAC21,
	33	[WRIOP1_DPMAC22] = FSL_CHASSIS3_DEVDISR2_DPMAC22,
	34	[WRIOP1_DPMAC23] = FSL_CHASSIS3_DEVDISR2_DPMAC23,
	35	[WRIOP1_DPMAC24] = FSL_CHASSIS3_DEVDISR2_DPMAC24,
	36	};
	37
	38	static int is_device_disabled(int dpmac_id)
	39	{
6cc04547	40	struct ccsr_gur __iomem gur = (void )CFG_SYS_FSL_GUTS_ADDR;
e60476a0 PK	41	u32 devdisr2 = in_le32(&gur->devdisr2);
	42
	43	return dpmac_to_devdisr[dpmac_id] & devdisr2;
	44	}
	45
	46	void wriop_dpmac_disable(int dpmac_id)
	47	{
6cc04547	48	struct ccsr_gur __iomem gur = (void )CFG_SYS_FSL_GUTS_ADDR;
e60476a0 PK	49
	50	setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
	51	}
	52
	53	void wriop_dpmac_enable(int dpmac_id)
	54	{
6cc04547	55	struct ccsr_gur __iomem gur = (void )CFG_SYS_FSL_GUTS_ADDR;
e60476a0 PK	56
	57	clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]);
	58	}
	59
	60	phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl)
	61	{
	62	enum srds_prtcl;
	63
	64	if (is_device_disabled(dpmac_id + 1))
ffb0f6f4	65	return PHY_INTERFACE_MODE_NA;
e60476a0 PK	66
	67	if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16)
	68	return PHY_INTERFACE_MODE_SGMII;
	69
	70	if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
	71	return PHY_INTERFACE_MODE_XGMII;
	72
	73	if (lane_prtcl >= XAUI1 && lane_prtcl <= XAUI2)
	74	return PHY_INTERFACE_MODE_XGMII;
	75
	76	if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D)
	77	return PHY_INTERFACE_MODE_QSGMII;
	78
ffb0f6f4	79	return PHY_INTERFACE_MODE_NA;
e60476a0	80	}
1b7dba99 PK	81
	82	void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
	83	{
	84	switch (lane_prtcl) {
	85	case QSGMII_A:
	86	wriop_init_dpmac(sd, 5, (int)lane_prtcl);
	87	wriop_init_dpmac(sd, 6, (int)lane_prtcl);
	88	wriop_init_dpmac(sd, 7, (int)lane_prtcl);
	89	wriop_init_dpmac(sd, 8, (int)lane_prtcl);
	90	break;
	91	case QSGMII_B:
	92	wriop_init_dpmac(sd, 1, (int)lane_prtcl);
	93	wriop_init_dpmac(sd, 2, (int)lane_prtcl);
	94	wriop_init_dpmac(sd, 3, (int)lane_prtcl);
	95	wriop_init_dpmac(sd, 4, (int)lane_prtcl);
	96	break;
	97	case QSGMII_C:
	98	wriop_init_dpmac(sd, 13, (int)lane_prtcl);
	99	wriop_init_dpmac(sd, 14, (int)lane_prtcl);
	100	wriop_init_dpmac(sd, 15, (int)lane_prtcl);
	101	wriop_init_dpmac(sd, 16, (int)lane_prtcl);
	102	break;
	103	case QSGMII_D:
	104	wriop_init_dpmac(sd, 9, (int)lane_prtcl);
	105	wriop_init_dpmac(sd, 10, (int)lane_prtcl);
	106	wriop_init_dpmac(sd, 11, (int)lane_prtcl);
	107	wriop_init_dpmac(sd, 12, (int)lane_prtcl);
	108	break;
	109	}
	110	}