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5c1fe1ff HS |
1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | #include <common.h> | |
19 | ||
5c1fe1ff HS |
20 | /* |
21 | * The u-boot networking stack is a little weird. It seems like the | |
22 | * networking core allocates receive buffers up front without any | |
23 | * regard to the hardware that's supposed to actually receive those | |
24 | * packets. | |
25 | * | |
26 | * The MACB receives packets into 128-byte receive buffers, so the | |
27 | * buffers allocated by the core isn't very practical to use. We'll | |
28 | * allocate our own, but we need one such buffer in case a packet | |
29 | * wraps around the DMA ring so that we have to copy it. | |
30 | * | |
6d0f6bcf | 31 | * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific |
5c1fe1ff HS |
32 | * configuration header. This way, the core allocates one RX buffer |
33 | * and one TX buffer, each of which can hold a ethernet packet of | |
34 | * maximum size. | |
35 | * | |
36 | * For some reason, the networking core unconditionally specifies a | |
37 | * 32-byte packet "alignment" (which really should be called | |
38 | * "padding"). MACB shouldn't need that, but we'll refrain from any | |
39 | * core modifications here... | |
40 | */ | |
41 | ||
42 | #include <net.h> | |
89973f8a | 43 | #include <netdev.h> |
5c1fe1ff HS |
44 | #include <malloc.h> |
45 | ||
46 | #include <linux/mii.h> | |
47 | #include <asm/io.h> | |
48 | #include <asm/dma-mapping.h> | |
49 | #include <asm/arch/clk.h> | |
50 | ||
51 | #include "macb.h" | |
52 | ||
04fcb5d3 HS |
53 | #define barrier() asm volatile("" ::: "memory") |
54 | ||
6d0f6bcf JCPV |
55 | #define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096 |
56 | #define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128) | |
57 | #define CONFIG_SYS_MACB_TX_RING_SIZE 16 | |
58 | #define CONFIG_SYS_MACB_TX_TIMEOUT 1000 | |
59 | #define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000 | |
5c1fe1ff HS |
60 | |
61 | struct macb_dma_desc { | |
62 | u32 addr; | |
63 | u32 ctrl; | |
64 | }; | |
65 | ||
66 | #define RXADDR_USED 0x00000001 | |
67 | #define RXADDR_WRAP 0x00000002 | |
68 | ||
69 | #define RXBUF_FRMLEN_MASK 0x00000fff | |
70 | #define RXBUF_FRAME_START 0x00004000 | |
71 | #define RXBUF_FRAME_END 0x00008000 | |
72 | #define RXBUF_TYPEID_MATCH 0x00400000 | |
73 | #define RXBUF_ADDR4_MATCH 0x00800000 | |
74 | #define RXBUF_ADDR3_MATCH 0x01000000 | |
75 | #define RXBUF_ADDR2_MATCH 0x02000000 | |
76 | #define RXBUF_ADDR1_MATCH 0x04000000 | |
77 | #define RXBUF_BROADCAST 0x80000000 | |
78 | ||
79 | #define TXBUF_FRMLEN_MASK 0x000007ff | |
80 | #define TXBUF_FRAME_END 0x00008000 | |
81 | #define TXBUF_NOCRC 0x00010000 | |
82 | #define TXBUF_EXHAUSTED 0x08000000 | |
83 | #define TXBUF_UNDERRUN 0x10000000 | |
84 | #define TXBUF_MAXRETRY 0x20000000 | |
85 | #define TXBUF_WRAP 0x40000000 | |
86 | #define TXBUF_USED 0x80000000 | |
87 | ||
88 | struct macb_device { | |
89 | void *regs; | |
90 | ||
91 | unsigned int rx_tail; | |
92 | unsigned int tx_head; | |
93 | unsigned int tx_tail; | |
94 | ||
95 | void *rx_buffer; | |
96 | void *tx_buffer; | |
97 | struct macb_dma_desc *rx_ring; | |
98 | struct macb_dma_desc *tx_ring; | |
99 | ||
100 | unsigned long rx_buffer_dma; | |
101 | unsigned long rx_ring_dma; | |
102 | unsigned long tx_ring_dma; | |
103 | ||
104 | const struct device *dev; | |
105 | struct eth_device netdev; | |
106 | unsigned short phy_addr; | |
107 | }; | |
108 | #define to_macb(_nd) container_of(_nd, struct macb_device, netdev) | |
109 | ||
110 | static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) | |
111 | { | |
112 | unsigned long netctl; | |
113 | unsigned long netstat; | |
114 | unsigned long frame; | |
115 | ||
116 | netctl = macb_readl(macb, NCR); | |
117 | netctl |= MACB_BIT(MPE); | |
118 | macb_writel(macb, NCR, netctl); | |
119 | ||
120 | frame = (MACB_BF(SOF, 1) | |
121 | | MACB_BF(RW, 1) | |
122 | | MACB_BF(PHYA, macb->phy_addr) | |
123 | | MACB_BF(REGA, reg) | |
124 | | MACB_BF(CODE, 2) | |
125 | | MACB_BF(DATA, value)); | |
126 | macb_writel(macb, MAN, frame); | |
127 | ||
128 | do { | |
129 | netstat = macb_readl(macb, NSR); | |
130 | } while (!(netstat & MACB_BIT(IDLE))); | |
131 | ||
132 | netctl = macb_readl(macb, NCR); | |
133 | netctl &= ~MACB_BIT(MPE); | |
134 | macb_writel(macb, NCR, netctl); | |
135 | } | |
136 | ||
137 | static u16 macb_mdio_read(struct macb_device *macb, u8 reg) | |
138 | { | |
139 | unsigned long netctl; | |
140 | unsigned long netstat; | |
141 | unsigned long frame; | |
142 | ||
143 | netctl = macb_readl(macb, NCR); | |
144 | netctl |= MACB_BIT(MPE); | |
145 | macb_writel(macb, NCR, netctl); | |
146 | ||
147 | frame = (MACB_BF(SOF, 1) | |
148 | | MACB_BF(RW, 2) | |
149 | | MACB_BF(PHYA, macb->phy_addr) | |
150 | | MACB_BF(REGA, reg) | |
151 | | MACB_BF(CODE, 2)); | |
152 | macb_writel(macb, MAN, frame); | |
153 | ||
154 | do { | |
155 | netstat = macb_readl(macb, NSR); | |
156 | } while (!(netstat & MACB_BIT(IDLE))); | |
157 | ||
158 | frame = macb_readl(macb, MAN); | |
159 | ||
160 | netctl = macb_readl(macb, NCR); | |
161 | netctl &= ~MACB_BIT(MPE); | |
162 | macb_writel(macb, NCR, netctl); | |
163 | ||
164 | return MACB_BFEXT(DATA, frame); | |
165 | } | |
166 | ||
07d38a17 | 167 | #if defined(CONFIG_CMD_NET) |
5c1fe1ff HS |
168 | |
169 | static int macb_send(struct eth_device *netdev, volatile void *packet, | |
170 | int length) | |
171 | { | |
172 | struct macb_device *macb = to_macb(netdev); | |
173 | unsigned long paddr, ctrl; | |
174 | unsigned int tx_head = macb->tx_head; | |
175 | int i; | |
176 | ||
177 | paddr = dma_map_single(packet, length, DMA_TO_DEVICE); | |
178 | ||
179 | ctrl = length & TXBUF_FRMLEN_MASK; | |
180 | ctrl |= TXBUF_FRAME_END; | |
6d0f6bcf | 181 | if (tx_head == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) { |
5c1fe1ff HS |
182 | ctrl |= TXBUF_WRAP; |
183 | macb->tx_head = 0; | |
184 | } else | |
185 | macb->tx_head++; | |
186 | ||
187 | macb->tx_ring[tx_head].ctrl = ctrl; | |
188 | macb->tx_ring[tx_head].addr = paddr; | |
04fcb5d3 | 189 | barrier(); |
5c1fe1ff HS |
190 | macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); |
191 | ||
192 | /* | |
193 | * I guess this is necessary because the networking core may | |
194 | * re-use the transmit buffer as soon as we return... | |
195 | */ | |
6d0f6bcf | 196 | for (i = 0; i <= CONFIG_SYS_MACB_TX_TIMEOUT; i++) { |
04fcb5d3 HS |
197 | barrier(); |
198 | ctrl = macb->tx_ring[tx_head].ctrl; | |
199 | if (ctrl & TXBUF_USED) | |
5c1fe1ff | 200 | break; |
5c1fe1ff | 201 | udelay(1); |
5c1fe1ff HS |
202 | } |
203 | ||
204 | dma_unmap_single(packet, length, paddr); | |
205 | ||
6d0f6bcf | 206 | if (i <= CONFIG_SYS_MACB_TX_TIMEOUT) { |
5c1fe1ff HS |
207 | if (ctrl & TXBUF_UNDERRUN) |
208 | printf("%s: TX underrun\n", netdev->name); | |
209 | if (ctrl & TXBUF_EXHAUSTED) | |
210 | printf("%s: TX buffers exhausted in mid frame\n", | |
211 | netdev->name); | |
04fcb5d3 HS |
212 | } else { |
213 | printf("%s: TX timeout\n", netdev->name); | |
5c1fe1ff HS |
214 | } |
215 | ||
216 | /* No one cares anyway */ | |
217 | return 0; | |
218 | } | |
219 | ||
220 | static void reclaim_rx_buffers(struct macb_device *macb, | |
221 | unsigned int new_tail) | |
222 | { | |
223 | unsigned int i; | |
224 | ||
225 | i = macb->rx_tail; | |
226 | while (i > new_tail) { | |
227 | macb->rx_ring[i].addr &= ~RXADDR_USED; | |
228 | i++; | |
6d0f6bcf | 229 | if (i > CONFIG_SYS_MACB_RX_RING_SIZE) |
5c1fe1ff HS |
230 | i = 0; |
231 | } | |
232 | ||
233 | while (i < new_tail) { | |
234 | macb->rx_ring[i].addr &= ~RXADDR_USED; | |
235 | i++; | |
236 | } | |
237 | ||
04fcb5d3 | 238 | barrier(); |
5c1fe1ff HS |
239 | macb->rx_tail = new_tail; |
240 | } | |
241 | ||
242 | static int macb_recv(struct eth_device *netdev) | |
243 | { | |
244 | struct macb_device *macb = to_macb(netdev); | |
245 | unsigned int rx_tail = macb->rx_tail; | |
246 | void *buffer; | |
247 | int length; | |
248 | int wrapped = 0; | |
249 | u32 status; | |
250 | ||
251 | for (;;) { | |
252 | if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) | |
253 | return -1; | |
254 | ||
255 | status = macb->rx_ring[rx_tail].ctrl; | |
256 | if (status & RXBUF_FRAME_START) { | |
257 | if (rx_tail != macb->rx_tail) | |
258 | reclaim_rx_buffers(macb, rx_tail); | |
259 | wrapped = 0; | |
260 | } | |
261 | ||
262 | if (status & RXBUF_FRAME_END) { | |
263 | buffer = macb->rx_buffer + 128 * macb->rx_tail; | |
264 | length = status & RXBUF_FRMLEN_MASK; | |
265 | if (wrapped) { | |
266 | unsigned int headlen, taillen; | |
267 | ||
6d0f6bcf | 268 | headlen = 128 * (CONFIG_SYS_MACB_RX_RING_SIZE |
5c1fe1ff HS |
269 | - macb->rx_tail); |
270 | taillen = length - headlen; | |
271 | memcpy((void *)NetRxPackets[0], | |
272 | buffer, headlen); | |
273 | memcpy((void *)NetRxPackets[0] + headlen, | |
274 | macb->rx_buffer, taillen); | |
275 | buffer = (void *)NetRxPackets[0]; | |
276 | } | |
277 | ||
278 | NetReceive(buffer, length); | |
6d0f6bcf | 279 | if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) |
5c1fe1ff HS |
280 | rx_tail = 0; |
281 | reclaim_rx_buffers(macb, rx_tail); | |
282 | } else { | |
6d0f6bcf | 283 | if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) { |
5c1fe1ff HS |
284 | wrapped = 1; |
285 | rx_tail = 0; | |
286 | } | |
287 | } | |
04fcb5d3 | 288 | barrier(); |
5c1fe1ff HS |
289 | } |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
f2134f8e | 294 | static void macb_phy_reset(struct macb_device *macb) |
5c1fe1ff HS |
295 | { |
296 | struct eth_device *netdev = &macb->netdev; | |
5c1fe1ff | 297 | int i; |
f2134f8e | 298 | u16 status, adv; |
5c1fe1ff HS |
299 | |
300 | adv = ADVERTISE_CSMA | ADVERTISE_ALL; | |
301 | macb_mdio_write(macb, MII_ADVERTISE, adv); | |
302 | printf("%s: Starting autonegotiation...\n", netdev->name); | |
303 | macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE | |
304 | | BMCR_ANRESTART)); | |
305 | ||
6d0f6bcf | 306 | for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) { |
5c1fe1ff HS |
307 | status = macb_mdio_read(macb, MII_BMSR); |
308 | if (status & BMSR_ANEGCOMPLETE) | |
309 | break; | |
310 | udelay(100); | |
311 | } | |
312 | ||
313 | if (status & BMSR_ANEGCOMPLETE) | |
314 | printf("%s: Autonegotiation complete\n", netdev->name); | |
315 | else | |
316 | printf("%s: Autonegotiation timed out (status=0x%04x)\n", | |
317 | netdev->name, status); | |
f2134f8e | 318 | } |
5c1fe1ff | 319 | |
f2134f8e HS |
320 | static int macb_phy_init(struct macb_device *macb) |
321 | { | |
322 | struct eth_device *netdev = &macb->netdev; | |
323 | u32 ncfgr; | |
324 | u16 phy_id, status, adv, lpa; | |
325 | int media, speed, duplex; | |
326 | int i; | |
327 | ||
328 | /* Check if the PHY is up to snuff... */ | |
329 | phy_id = macb_mdio_read(macb, MII_PHYSID1); | |
330 | if (phy_id == 0xffff) { | |
331 | printf("%s: No PHY present\n", netdev->name); | |
332 | return 0; | |
333 | } | |
334 | ||
335 | status = macb_mdio_read(macb, MII_BMSR); | |
5c1fe1ff | 336 | if (!(status & BMSR_LSTATUS)) { |
f2134f8e HS |
337 | /* Try to re-negotiate if we don't have link already. */ |
338 | macb_phy_reset(macb); | |
339 | ||
6d0f6bcf | 340 | for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) { |
5c1fe1ff HS |
341 | status = macb_mdio_read(macb, MII_BMSR); |
342 | if (status & BMSR_LSTATUS) | |
343 | break; | |
f2134f8e | 344 | udelay(100); |
5c1fe1ff HS |
345 | } |
346 | } | |
347 | ||
348 | if (!(status & BMSR_LSTATUS)) { | |
349 | printf("%s: link down (status: 0x%04x)\n", | |
350 | netdev->name, status); | |
351 | return 0; | |
352 | } else { | |
f2134f8e | 353 | adv = macb_mdio_read(macb, MII_ADVERTISE); |
5c1fe1ff HS |
354 | lpa = macb_mdio_read(macb, MII_LPA); |
355 | media = mii_nway_result(lpa & adv); | |
356 | speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) | |
357 | ? 1 : 0); | |
358 | duplex = (media & ADVERTISE_FULL) ? 1 : 0; | |
359 | printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", | |
360 | netdev->name, | |
361 | speed ? "100" : "10", | |
362 | duplex ? "full" : "half", | |
363 | lpa); | |
364 | ||
365 | ncfgr = macb_readl(macb, NCFGR); | |
366 | ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); | |
367 | if (speed) | |
368 | ncfgr |= MACB_BIT(SPD); | |
369 | if (duplex) | |
370 | ncfgr |= MACB_BIT(FD); | |
371 | macb_writel(macb, NCFGR, ncfgr); | |
372 | return 1; | |
373 | } | |
374 | } | |
375 | ||
376 | static int macb_init(struct eth_device *netdev, bd_t *bd) | |
377 | { | |
378 | struct macb_device *macb = to_macb(netdev); | |
379 | unsigned long paddr; | |
380 | u32 hwaddr_bottom; | |
381 | u16 hwaddr_top; | |
382 | int i; | |
383 | ||
384 | /* | |
385 | * macb_halt should have been called at some point before now, | |
386 | * so we'll assume the controller is idle. | |
387 | */ | |
388 | ||
389 | /* initialize DMA descriptors */ | |
390 | paddr = macb->rx_buffer_dma; | |
6d0f6bcf JCPV |
391 | for (i = 0; i < CONFIG_SYS_MACB_RX_RING_SIZE; i++) { |
392 | if (i == (CONFIG_SYS_MACB_RX_RING_SIZE - 1)) | |
5c1fe1ff HS |
393 | paddr |= RXADDR_WRAP; |
394 | macb->rx_ring[i].addr = paddr; | |
395 | macb->rx_ring[i].ctrl = 0; | |
396 | paddr += 128; | |
397 | } | |
6d0f6bcf | 398 | for (i = 0; i < CONFIG_SYS_MACB_TX_RING_SIZE; i++) { |
5c1fe1ff | 399 | macb->tx_ring[i].addr = 0; |
6d0f6bcf | 400 | if (i == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) |
5c1fe1ff HS |
401 | macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; |
402 | else | |
403 | macb->tx_ring[i].ctrl = TXBUF_USED; | |
404 | } | |
405 | macb->rx_tail = macb->tx_head = macb->tx_tail = 0; | |
406 | ||
407 | macb_writel(macb, RBQP, macb->rx_ring_dma); | |
408 | macb_writel(macb, TBQP, macb->tx_ring_dma); | |
409 | ||
410 | /* set hardware address */ | |
411 | hwaddr_bottom = cpu_to_le32(*((u32 *)netdev->enetaddr)); | |
412 | macb_writel(macb, SA1B, hwaddr_bottom); | |
413 | hwaddr_top = cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))); | |
414 | macb_writel(macb, SA1T, hwaddr_top); | |
415 | ||
416 | /* choose RMII or MII mode. This depends on the board */ | |
417 | #ifdef CONFIG_RMII | |
8e429b3e SP |
418 | #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ |
419 | defined(CONFIG_AT91SAM9263) | |
7263ef19 SP |
420 | macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); |
421 | #else | |
5c1fe1ff | 422 | macb_writel(macb, USRIO, 0); |
7263ef19 SP |
423 | #endif |
424 | #else | |
8e429b3e SP |
425 | #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ |
426 | defined(CONFIG_AT91SAM9263) | |
7263ef19 | 427 | macb_writel(macb, USRIO, MACB_BIT(CLKEN)); |
5c1fe1ff HS |
428 | #else |
429 | macb_writel(macb, USRIO, MACB_BIT(MII)); | |
430 | #endif | |
7263ef19 | 431 | #endif /* CONFIG_RMII */ |
5c1fe1ff HS |
432 | |
433 | if (!macb_phy_init(macb)) | |
422b1a01 | 434 | return -1; |
5c1fe1ff HS |
435 | |
436 | /* Enable TX and RX */ | |
437 | macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); | |
438 | ||
422b1a01 | 439 | return 0; |
5c1fe1ff HS |
440 | } |
441 | ||
442 | static void macb_halt(struct eth_device *netdev) | |
443 | { | |
444 | struct macb_device *macb = to_macb(netdev); | |
445 | u32 ncr, tsr; | |
446 | ||
447 | /* Halt the controller and wait for any ongoing transmission to end. */ | |
448 | ncr = macb_readl(macb, NCR); | |
449 | ncr |= MACB_BIT(THALT); | |
450 | macb_writel(macb, NCR, ncr); | |
451 | ||
452 | do { | |
453 | tsr = macb_readl(macb, TSR); | |
454 | } while (tsr & MACB_BIT(TGO)); | |
455 | ||
456 | /* Disable TX and RX, and clear statistics */ | |
457 | macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); | |
458 | } | |
459 | ||
460 | int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) | |
461 | { | |
462 | struct macb_device *macb; | |
463 | struct eth_device *netdev; | |
464 | unsigned long macb_hz; | |
465 | u32 ncfgr; | |
466 | ||
467 | macb = malloc(sizeof(struct macb_device)); | |
468 | if (!macb) { | |
469 | printf("Error: Failed to allocate memory for MACB%d\n", id); | |
470 | return -1; | |
471 | } | |
472 | memset(macb, 0, sizeof(struct macb_device)); | |
473 | ||
474 | netdev = &macb->netdev; | |
475 | ||
6d0f6bcf | 476 | macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE, |
5c1fe1ff | 477 | &macb->rx_buffer_dma); |
6d0f6bcf | 478 | macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE |
5c1fe1ff HS |
479 | * sizeof(struct macb_dma_desc), |
480 | &macb->rx_ring_dma); | |
6d0f6bcf | 481 | macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE |
5c1fe1ff HS |
482 | * sizeof(struct macb_dma_desc), |
483 | &macb->tx_ring_dma); | |
484 | ||
485 | macb->regs = regs; | |
486 | macb->phy_addr = phy_addr; | |
487 | ||
488 | sprintf(netdev->name, "macb%d", id); | |
489 | netdev->init = macb_init; | |
490 | netdev->halt = macb_halt; | |
491 | netdev->send = macb_send; | |
492 | netdev->recv = macb_recv; | |
493 | ||
494 | /* | |
495 | * Do some basic initialization so that we at least can talk | |
496 | * to the PHY | |
497 | */ | |
498 | macb_hz = get_macb_pclk_rate(id); | |
499 | if (macb_hz < 20000000) | |
500 | ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); | |
501 | else if (macb_hz < 40000000) | |
502 | ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); | |
503 | else if (macb_hz < 80000000) | |
504 | ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); | |
505 | else | |
506 | ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); | |
507 | ||
508 | macb_writel(macb, NCFGR, ncfgr); | |
509 | ||
510 | eth_register(netdev); | |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
07d38a17 | 515 | #endif |
5c1fe1ff | 516 | |
07d38a17 | 517 | #if defined(CONFIG_CMD_MII) |
5c1fe1ff HS |
518 | |
519 | int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value) | |
520 | { | |
521 | unsigned long netctl; | |
522 | unsigned long netstat; | |
523 | unsigned long frame; | |
524 | int iflag; | |
525 | ||
526 | iflag = disable_interrupts(); | |
527 | netctl = macb_readl(&macb, EMACB_NCR); | |
528 | netctl |= MACB_BIT(MPE); | |
529 | macb_writel(&macb, EMACB_NCR, netctl); | |
530 | if (iflag) | |
531 | enable_interrupts(); | |
532 | ||
533 | frame = (MACB_BF(SOF, 1) | |
534 | | MACB_BF(RW, 2) | |
535 | | MACB_BF(PHYA, addr) | |
536 | | MACB_BF(REGA, reg) | |
537 | | MACB_BF(CODE, 2)); | |
538 | macb_writel(&macb, EMACB_MAN, frame); | |
539 | ||
540 | do { | |
541 | netstat = macb_readl(&macb, EMACB_NSR); | |
542 | } while (!(netstat & MACB_BIT(IDLE))); | |
543 | ||
544 | frame = macb_readl(&macb, EMACB_MAN); | |
545 | *value = MACB_BFEXT(DATA, frame); | |
546 | ||
547 | iflag = disable_interrupts(); | |
548 | netctl = macb_readl(&macb, EMACB_NCR); | |
549 | netctl &= ~MACB_BIT(MPE); | |
550 | macb_writel(&macb, EMACB_NCR, netctl); | |
551 | if (iflag) | |
552 | enable_interrupts(); | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
557 | int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value) | |
558 | { | |
559 | unsigned long netctl; | |
560 | unsigned long netstat; | |
561 | unsigned long frame; | |
562 | int iflag; | |
563 | ||
564 | iflag = disable_interrupts(); | |
565 | netctl = macb_readl(&macb, EMACB_NCR); | |
566 | netctl |= MACB_BIT(MPE); | |
567 | macb_writel(&macb, EMACB_NCR, netctl); | |
568 | if (iflag) | |
569 | enable_interrupts(); | |
570 | ||
571 | frame = (MACB_BF(SOF, 1) | |
572 | | MACB_BF(RW, 1) | |
573 | | MACB_BF(PHYA, addr) | |
574 | | MACB_BF(REGA, reg) | |
575 | | MACB_BF(CODE, 2) | |
576 | | MACB_BF(DATA, value)); | |
577 | macb_writel(&macb, EMACB_MAN, frame); | |
578 | ||
579 | do { | |
580 | netstat = macb_readl(&macb, EMACB_NSR); | |
581 | } while (!(netstat & MACB_BIT(IDLE))); | |
582 | ||
583 | iflag = disable_interrupts(); | |
584 | netctl = macb_readl(&macb, EMACB_NCR); | |
585 | netctl &= ~MACB_BIT(MPE); | |
586 | macb_writel(&macb, EMACB_NCR, netctl); | |
587 | if (iflag) | |
588 | enable_interrupts(); | |
589 | ||
590 | return 0; | |
591 | } | |
592 | ||
07d38a17 | 593 | #endif |