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8e585f02
TL		 1/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
f2208fbc 5 * (C) Copyright 2007 Freescale Semiconductor, Inc.
8e585f02
TL		 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <malloc.h>
29
3e66c078
WD		 30#ifdef CONFIG_MCFFEC
31
8e585f02 32#include <asm/fec.h>
f2208fbc 33#include <asm/immap.h>
8e585f02
TL		 34
35#include <command.h>
8e585f02
TL		 36#include <net.h>
37#include <miiphy.h>
38
8e585f02
TL		 39#undef ET_DEBUG
40#undef MII_DEBUG
41
42/* Ethernet Transmit and Receive Buffers */
f2208fbc
TL		 43#define DBUF_LENGTH 1520
44#define TX_BUF_CNT 2
8e585f02
TL		 45#define PKT_MAXBUF_SIZE 1518
46#define PKT_MINBUF_SIZE 64
47#define PKT_MAXBLR_SIZE 1520
48#define LAST_PKTBUFSRX PKTBUFSRX - 1
49#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
50#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
51
52DECLARE_GLOBAL_DATA_PTR;
53
ab77bc54 54#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI)
8e585f02
TL		 55
56struct fec_info_s fec_info[] = {
57#ifdef CFG_FEC0_IOBASE
58 {
59 0, /* index */
60 CFG_FEC0_IOBASE, /* io base */
61 CFG_FEC0_PINMUX, /* gpio pin muxing */
62 CFG_FEC0_MIIBASE, /* mii base */
63 -1, /* phy_addr */
64 0, /* duplex and speed */
65 0, /* phy name */
66 0, /* phyname init */
67 0, /* RX BD */
68 0, /* TX BD */
69 0, /* rx Index */
70 0, /* tx Index */
71 0, /* tx buffer */
72 0, /* initialized flag */
73 },
74#endif
75#ifdef CFG_FEC1_IOBASE
76 {
77 1, /* index */
78 CFG_FEC1_IOBASE, /* io base */
79 CFG_FEC1_PINMUX, /* gpio pin muxing */
80 CFG_FEC1_MIIBASE, /* mii base */
81 -1, /* phy_addr */
82 0, /* duplex and speed */
83 0, /* phy name */
84 0, /* phy name init */
85 0, /* RX BD */
86 0, /* TX BD */
87 0, /* rx Index */
88 0, /* tx Index */
89 0, /* tx buffer */
90 0, /* initialized flag */
91 }
92#endif
93};
94
8e585f02
TL		 95int fec_send(struct eth_device *dev, volatile void *packet, int length);
96int fec_recv(struct eth_device *dev);
97int fec_init(struct eth_device *dev, bd_t * bd);
98void fec_halt(struct eth_device *dev);
99void fec_reset(struct eth_device *dev);
100
101extern int fecpin_setclear(struct eth_device *dev, int setclear);
102
103#ifdef CFG_DISCOVER_PHY
9e737d84 104extern void __mii_init(void);
8e585f02
TL		 105extern uint mii_send(uint mii_cmd);
106extern int mii_discover_phy(struct eth_device *dev);
107extern int mcffec_miiphy_read(char *devname, unsigned char addr,
108 unsigned char reg, unsigned short *value);
109extern int mcffec_miiphy_write(char *devname, unsigned char addr,
110 unsigned char reg, unsigned short value);
111#endif
112
113void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
114{
115 if ((dup_spd >> 16) == FULL) {
116 /* Set maximum frame length */
117 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
118 FEC_RCR_PROM | 0x100;
119 fecp->tcr = FEC_TCR_FDEN;
120 } else {
121 /* Half duplex mode */
122 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
123 FEC_RCR_MII_MODE | FEC_RCR_DRT;
124 fecp->tcr &= ~FEC_TCR_FDEN;
125 }
126
127 if ((dup_spd & 0xFFFF) == _100BASET) {
128#ifdef MII_DEBUG
129 printf("100Mbps\n");
130#endif
131 bd->bi_ethspeed = 100;
132 } else {
133#ifdef MII_DEBUG
134 printf("10Mbps\n");
135#endif
136 bd->bi_ethspeed = 10;
137 }
138}
139
140int fec_send(struct eth_device *dev, volatile void *packet, int length)
141{
142 struct fec_info_s *info = dev->priv;
143 volatile fec_t *fecp = (fec_t *) (info->iobase);
144 int j, rc;
145 u16 phyStatus;
146
147 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);
148
149 /* section 16.9.23.3
150 * Wait for ready
151 */
152 j = 0;
153 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
154 (j < MCFFEC_TOUT_LOOP)) {
155 udelay(1);
156 j++;
157 }
158 if (j >= MCFFEC_TOUT_LOOP) {
159 printf("TX not ready\n");
160 }
0dca874d 161
8e585f02
TL		 162 info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
163 info->txbd[info->txIdx].cbd_datlen = length;
164 info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
165
166 /* Activate transmit Buffer Descriptor polling */
167 fecp->tdar = 0x01000000; /* Descriptor polling active */
168
f605479d
TL		 169 /* FEC fix for MCF5275, FEC unable to initial transmit data packet.
170 * A nop will ensure the descriptor polling active completed.
171 */
172#ifdef CONFIG_M5275
173 __asm__ ("nop");
174#endif
175
0dca874d 176#ifdef CFG_UNIFY_CACHE
f2208fbc
TL		 177 icache_invalid();
178#endif
0dca874d 179 j = 0;
8e585f02
TL		 180 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
181 (j < MCFFEC_TOUT_LOOP)) {
182 udelay(1);
183 j++;
184 }
185 if (j >= MCFFEC_TOUT_LOOP) {
186 printf("TX timeout\n");
187 }
0dca874d 188
8e585f02
TL		 189#ifdef ET_DEBUG
190 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
191 __FILE__, __LINE__, __FUNCTION__, j,
192 info->txbd[info->txIdx].cbd_sc,
193 (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
194#endif
195
0dca874d 196 /* return only status bits */
8e585f02
TL		 197 rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
198 info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
199
200 return rc;
201}
202
203int fec_recv(struct eth_device *dev)
204{
205 struct fec_info_s *info = dev->priv;
206 volatile fec_t *fecp = (fec_t *) (info->iobase);
207 int length;
208
209 for (;;) {
0dca874d 210#ifdef CFG_UNIFY_CACHE
53677ef1 211 icache_invalid();
0dca874d 212#endif
8e585f02
TL		 213 /* section 16.9.23.2 */
214 if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
215 length = -1;
216 break; /* nothing received - leave for() loop */
217 }
218
219 length = info->rxbd[info->rxIdx].cbd_datlen;
220
221 if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
222 printf("%s[%d] err: %x\n",
223 __FUNCTION__, __LINE__,
224 info->rxbd[info->rxIdx].cbd_sc);
225#ifdef ET_DEBUG
226 printf("%s[%d] err: %x\n",
227 __FUNCTION__, __LINE__,
228 info->rxbd[info->rxIdx].cbd_sc);
229#endif
230 } else {
231
232 length -= 4;
233 /* Pass the packet up to the protocol layers. */
234 NetReceive(NetRxPackets[info->rxIdx], length);
235
236 fecp->eir |= FEC_EIR_RXF;
237 }
238
239 /* Give the buffer back to the FEC. */
240 info->rxbd[info->rxIdx].cbd_datlen = 0;
241
242 /* wrap around buffer index when necessary */
243 if (info->rxIdx == LAST_PKTBUFSRX) {
244 info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
245 info->rxIdx = 0;
246 } else {
247 info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
248 info->rxIdx++;
249 }
250
251 /* Try to fill Buffer Descriptors */
252 fecp->rdar = 0x01000000; /* Descriptor polling active */
253 }
254
255 return length;
256}
257
8e585f02
TL		 258#ifdef ET_DEBUG
259void dbgFecRegs(struct eth_device *dev)
260{
261 struct fec_info_s *info = dev->priv;
262 volatile fec_t *fecp = (fec_t *) (info->iobase);
263
264 printf("=====\n");
265 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
266 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
267 printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
268 printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
269 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
270 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
271 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
272 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
273 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
274 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
275 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
276 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
277 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
278 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
279 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
280 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
281 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
282 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
283 printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr);
284 printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr);
285 printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
286 printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
287 printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
288
289 printf("\n");
290 printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop,
291 fecp->rmon_t_drop);
292 printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets,
293 fecp->rmon_t_packets);
294 printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
295 fecp->rmon_t_bc_pkt);
296 printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
297 fecp->rmon_t_mc_pkt);
298 printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align,
299 fecp->rmon_t_crc_align);
300 printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize,
301 fecp->rmon_t_undersize);
302 printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize,
303 fecp->rmon_t_oversize);
304 printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag,
305 fecp->rmon_t_frag);
306 printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab,
307 fecp->rmon_t_jab);
308 printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col,
309 fecp->rmon_t_col);
310 printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64,
311 fecp->rmon_t_p64);
312 printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127,
313 fecp->rmon_t_p65to127);
314 printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255,
315 fecp->rmon_t_p128to255);
316 printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511,
317 fecp->rmon_t_p256to511);
318 printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023,
319 fecp->rmon_t_p512to1023);
320 printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
321 fecp->rmon_t_p1024to2047);
322 printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
323 fecp->rmon_t_p_gte2048);
324 printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets,
325 fecp->rmon_t_octets);
326
327 printf("\n");
328 printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop,
329 fecp->ieee_t_drop);
330 printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok,
331 fecp->ieee_t_frame_ok);
332 printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col,
333 fecp->ieee_t_1col);
334 printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol,
335 fecp->ieee_t_mcol);
336 printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def,
337 fecp->ieee_t_def);
338 printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol,
339 fecp->ieee_t_lcol);
340 printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol,
341 fecp->ieee_t_excol);
342 printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr,
343 fecp->ieee_t_macerr);
344 printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr,
345 fecp->ieee_t_cserr);
346 printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe,
347 fecp->ieee_t_sqe);
348 printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc,
349 fecp->ieee_t_fdxfc);
350 printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
351 fecp->ieee_t_octets_ok);
352
353 printf("\n");
354 printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop,
355 fecp->rmon_r_drop);
356 printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets,
357 fecp->rmon_r_packets);
358 printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
359 fecp->rmon_r_bc_pkt);
360 printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
361 fecp->rmon_r_mc_pkt);
362 printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align,
363 fecp->rmon_r_crc_align);
364 printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize,
365 fecp->rmon_r_undersize);
366 printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize,
367 fecp->rmon_r_oversize);
368 printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag,
369 fecp->rmon_r_frag);
370 printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab,
371 fecp->rmon_r_jab);
372 printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64,
373 fecp->rmon_r_p64);
374 printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127,
375 fecp->rmon_r_p65to127);
376 printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255,
377 fecp->rmon_r_p128to255);
378 printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511,
379 fecp->rmon_r_p256to511);
380 printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023,
381 fecp->rmon_r_p512to1023);
382 printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
383 fecp->rmon_r_p1024to2047);
384 printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
385 fecp->rmon_r_p_gte2048);
386 printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets,
387 fecp->rmon_r_octets);
388
389 printf("\n");
390 printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop,
391 fecp->ieee_r_drop);
392 printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok,
393 fecp->ieee_r_frame_ok);
394 printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc,
395 fecp->ieee_r_crc);
396 printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align,
397 fecp->ieee_r_align);
398 printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr,
399 fecp->ieee_r_macerr);
400 printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc,
401 fecp->ieee_r_fdxfc);
402 printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
403 fecp->ieee_r_octets_ok);
404
405 printf("\n\n\n");
406}
407#endif
408
409int fec_init(struct eth_device *dev, bd_t * bd)
410{
411 struct fec_info_s *info = dev->priv;
412 volatile fec_t *fecp = (fec_t *) (info->iobase);
413 int i;
f2208fbc 414 u8 *ea = NULL;
8e585f02
TL		 415
416 fecpin_setclear(dev, 1);
417
418 fec_reset(dev);
419
ab77bc54 420#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
8e585f02
TL		 421 defined (CFG_DISCOVER_PHY)
422
423 mii_init();
424
425 setFecDuplexSpeed(fecp, bd, info->dup_spd);
426#else
427#ifndef CFG_DISCOVER_PHY
428 setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
429#endif /* ifndef CFG_DISCOVER_PHY */
ab77bc54 430#endif /* CONFIG_CMD_MII || CONFIG_MII */
8e585f02
TL		 431
432 /* We use strictly polling mode only */
433 fecp->eimr = 0;
434
435 /* Clear any pending interrupt */
436 fecp->eir = 0xffffffff;
437
438 /* Set station address */
439 if ((u32) fecp == CFG_FEC0_IOBASE) {
8ae158cd
TL		 440#ifdef CFG_FEC1_IOBASE
441 volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE);
442 ea = &bd->bi_enet1addr[0];
443 fecp1->palr =
444 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
445 fecp1->paur = (ea[4] << 24) | (ea[5] << 16);
446#endif
8e585f02 447 ea = &bd->bi_enetaddr[0];
8ae158cd
TL		 448 fecp->palr =
449 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
450 fecp->paur = (ea[4] << 24) | (ea[5] << 16);
8e585f02 451 } else {
8ae158cd
TL		 452#ifdef CFG_FEC0_IOBASE
453 volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE);
454 ea = &bd->bi_enetaddr[0];
455 fecp0->palr =
456 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
457 fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
458#endif
8e585f02
TL		 459#ifdef CFG_FEC1_IOBASE
460 ea = &bd->bi_enet1addr[0];
8ae158cd
TL		 461 fecp->palr =
462 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
463 fecp->paur = (ea[4] << 24) | (ea[5] << 16);
8e585f02
TL		 464#endif
465 }
466
8e585f02
TL		 467 /* Clear unicast address hash table */
468 fecp->iaur = 0;
469 fecp->ialr = 0;
470
471 /* Clear multicast address hash table */
472 fecp->gaur = 0;
473 fecp->galr = 0;
474
475 /* Set maximum receive buffer size. */
476 fecp->emrbr = PKT_MAXBLR_SIZE;
477
478 /*
479 * Setup Buffers and Buffer Desriptors
480 */
481 info->rxIdx = 0;
482 info->txIdx = 0;
483
484 /*
485 * Setup Receiver Buffer Descriptors (13.14.24.18)
486 * Settings:
487 * Empty, Wrap
488 */
489 for (i = 0; i < PKTBUFSRX; i++) {
490 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
491 info->rxbd[i].cbd_datlen = 0; /* Reset */
492 info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
493 }
494 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
495
496 /*
497 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
498 * Settings:
499 * Last, Tx CRC
500 */
501 for (i = 0; i < TX_BUF_CNT; i++) {
502 info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
503 info->txbd[i].cbd_datlen = 0; /* Reset */
504 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
505 }
506 info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
507
508 /* Set receive and transmit descriptor base */
509 fecp->erdsr = (unsigned int)(&info->rxbd[0]);
510 fecp->etdsr = (unsigned int)(&info->txbd[0]);
511
512 /* Now enable the transmit and receive processing */
513 fecp->ecr |= FEC_ECR_ETHER_EN;
514
515 /* And last, try to fill Rx Buffer Descriptors */
516 fecp->rdar = 0x01000000; /* Descriptor polling active */
517
518 return 1;
519}
520
521void fec_reset(struct eth_device *dev)
522{
523 struct fec_info_s *info = dev->priv;
524 volatile fec_t *fecp = (fec_t *) (info->iobase);
525 int i;
526
527 fecp->ecr = FEC_ECR_RESET;
528 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
529 udelay(1);
530 }
531 if (i == FEC_RESET_DELAY) {
532 printf("FEC_RESET_DELAY timeout\n");
533 }
534}
535
536void fec_halt(struct eth_device *dev)
537{
538 struct fec_info_s *info = dev->priv;
539
540 fec_reset(dev);
541
542 fecpin_setclear(dev, 0);
543
544 info->rxIdx = info->txIdx = 0;
545 memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
546 memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
547 memset(info->txbuf, 0, DBUF_LENGTH);
548}
549
550int mcffec_initialize(bd_t * bis)
551{
552 struct eth_device *dev;
553 int i;
554
555 for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
556
f2208fbc
TL		 557 dev =
558 (struct eth_device *)memalign(CFG_CACHELINE_SIZE,
559 sizeof *dev);
8e585f02
TL		 560 if (dev == NULL)
561 hang();
562
563 memset(dev, 0, sizeof(*dev));
564
565 sprintf(dev->name, "FEC%d", fec_info[i].index);
566
567 dev->priv = &fec_info[i];
568 dev->init = fec_init;
569 dev->halt = fec_halt;
570 dev->send = fec_send;
571 dev->recv = fec_recv;
572
573 /* setup Receive and Transmit buffer descriptor */
574 fec_info[i].rxbd =
f2208fbc
TL		 575 (cbd_t *) memalign(CFG_CACHELINE_SIZE,
576 (PKTBUFSRX * sizeof(cbd_t)));
8e585f02 577 fec_info[i].txbd =
f2208fbc
TL		 578 (cbd_t *) memalign(CFG_CACHELINE_SIZE,
579 (TX_BUF_CNT * sizeof(cbd_t)));
580 fec_info[i].txbuf =
581 (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH);
8e585f02
TL		 582#ifdef ET_DEBUG
583 printf("rxbd %x txbd %x\n",
584 (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
585#endif
586
f2208fbc 587 fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32);
8e585f02
TL		 588
589 eth_register(dev);
590
ab77bc54 591#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
8e585f02
TL		 592 miiphy_register(dev->name,
593 mcffec_miiphy_read, mcffec_miiphy_write);
594#endif
595 }
596
597 /* default speed */
598 bis->bi_ethspeed = 10;
599
600 return 1;
601}
602
ab77bc54 603#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */
8e585f02 604#endif /* CONFIG_MCFFEC */
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