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c8546163 GC |
1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
2 | /* | |
3 | * Copyright (c) 2018 Microsemi Corporation | |
4 | */ | |
5 | ||
d678a59d | 6 | #include <common.h> |
c8546163 GC |
7 | #include <config.h> |
8 | #include <dm.h> | |
f7ae49fc | 9 | #include <log.h> |
336d4615 | 10 | #include <malloc.h> |
c8546163 GC |
11 | #include <dm/of_access.h> |
12 | #include <dm/of_addr.h> | |
13 | #include <fdt_support.h> | |
cd93d625 | 14 | #include <linux/bitops.h> |
c8546163 GC |
15 | #include <linux/io.h> |
16 | #include <linux/ioport.h> | |
17 | #include <miiphy.h> | |
18 | #include <net.h> | |
19 | #include <wait_bit.h> | |
1e94b46f | 20 | #include <linux/printk.h> |
c8546163 | 21 | |
36d04f52 | 22 | #include "mscc_xfer.h" |
45f2748c | 23 | #include "mscc_mac_table.h" |
61243678 | 24 | #include "mscc_miim.h" |
c8546163 GC |
25 | |
26 | #define PHY_CFG 0x0 | |
27 | #define PHY_CFG_ENA 0xF | |
28 | #define PHY_CFG_COMMON_RST BIT(4) | |
29 | #define PHY_CFG_RST (0xF << 5) | |
30 | #define PHY_STAT 0x4 | |
31 | #define PHY_STAT_SUPERVISOR_COMPLETE BIT(0) | |
32 | ||
33 | #define ANA_PORT_VLAN_CFG(x) (0x7000 + 0x100 * (x)) | |
34 | #define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20) | |
35 | #define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18) | |
36 | #define ANA_PORT_PORT_CFG(x) (0x7070 + 0x100 * (x)) | |
37 | #define ANA_PORT_PORT_CFG_RECV_ENA BIT(6) | |
c8546163 GC |
38 | #define ANA_PGID(x) (0x8c00 + 4 * (x)) |
39 | ||
6390da4a HV |
40 | #define HSIO_ANA_SERDES1G_DES_CFG 0x4c |
41 | #define HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x) ((x) << 1) | |
42 | #define HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5) | |
43 | #define HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8) | |
44 | #define HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13) | |
45 | #define HSIO_ANA_SERDES1G_IB_CFG 0x50 | |
46 | #define HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x) | |
47 | #define HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6) | |
48 | #define HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP BIT(9) | |
49 | #define HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11) | |
50 | #define HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13) | |
51 | #define HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24) | |
52 | #define HSIO_ANA_SERDES1G_OB_CFG 0x54 | |
53 | #define HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x) | |
54 | #define HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x) ((x) << 4) | |
55 | #define HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10) | |
56 | #define HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x) ((x) << 13) | |
57 | #define HSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17) | |
58 | #define HSIO_ANA_SERDES1G_SER_CFG 0x58 | |
59 | #define HSIO_ANA_SERDES1G_COMMON_CFG 0x5c | |
60 | #define HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE BIT(0) | |
61 | #define HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18) | |
62 | #define HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST BIT(31) | |
63 | #define HSIO_ANA_SERDES1G_PLL_CFG 0x60 | |
64 | #define HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7) | |
65 | #define HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8) | |
66 | #define HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21) | |
67 | #define HSIO_DIG_SERDES1G_DFT_CFG0 0x68 | |
68 | #define HSIO_DIG_SERDES1G_MISC_CFG 0x7c | |
69 | #define HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0) | |
70 | #define HSIO_MCB_SERDES1G_CFG 0x88 | |
71 | #define HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31) | |
72 | #define HSIO_MCB_SERDES1G_CFG_ADDR(x) (x) | |
73 | #define HSIO_HW_CFGSTAT_HW_CFG 0x10c | |
74 | ||
c8546163 GC |
75 | #define SYS_FRM_AGING 0x574 |
76 | #define SYS_FRM_AGING_ENA BIT(20) | |
77 | ||
78 | #define SYS_SYSTEM_RST_CFG 0x508 | |
79 | #define SYS_SYSTEM_RST_MEM_INIT BIT(0) | |
80 | #define SYS_SYSTEM_RST_MEM_ENA BIT(1) | |
81 | #define SYS_SYSTEM_RST_CORE_ENA BIT(2) | |
82 | #define SYS_PORT_MODE(x) (0x514 + 0x4 * (x)) | |
83 | #define SYS_PORT_MODE_INCL_INJ_HDR(x) ((x) << 3) | |
84 | #define SYS_PORT_MODE_INCL_INJ_HDR_M GENMASK(4, 3) | |
85 | #define SYS_PORT_MODE_INCL_XTR_HDR(x) ((x) << 1) | |
86 | #define SYS_PORT_MODE_INCL_XTR_HDR_M GENMASK(2, 1) | |
87 | #define SYS_PAUSE_CFG(x) (0x608 + 0x4 * (x)) | |
88 | #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0) | |
89 | ||
90 | #define QSYS_SWITCH_PORT_MODE(x) (0x11234 + 0x4 * (x)) | |
91 | #define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(14) | |
92 | #define QSYS_QMAP 0x112d8 | |
93 | #define QSYS_EGR_NO_SHARING 0x1129c | |
94 | ||
95 | /* Port registers */ | |
96 | #define DEV_CLOCK_CFG 0x0 | |
97 | #define DEV_CLOCK_CFG_LINK_SPEED_1000 1 | |
98 | #define DEV_MAC_ENA_CFG 0x1c | |
99 | #define DEV_MAC_ENA_CFG_RX_ENA BIT(4) | |
100 | #define DEV_MAC_ENA_CFG_TX_ENA BIT(0) | |
101 | ||
102 | #define DEV_MAC_IFG_CFG 0x30 | |
103 | #define DEV_MAC_IFG_CFG_TX_IFG(x) ((x) << 8) | |
104 | #define DEV_MAC_IFG_CFG_RX_IFG2(x) ((x) << 4) | |
105 | #define DEV_MAC_IFG_CFG_RX_IFG1(x) (x) | |
106 | ||
107 | #define PCS1G_CFG 0x48 | |
108 | #define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) | |
109 | #define PCS1G_MODE_CFG 0x4c | |
110 | #define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4) | |
111 | #define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) | |
112 | #define PCS1G_SD_CFG 0x50 | |
113 | #define PCS1G_ANEG_CFG 0x54 | |
114 | #define PCS1G_ANEG_CFG_ADV_ABILITY(x) ((x) << 16) | |
115 | ||
116 | #define QS_XTR_GRP_CFG(x) (4 * (x)) | |
117 | #define QS_XTR_GRP_CFG_MODE(x) ((x) << 2) | |
118 | #define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1) | |
119 | #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) | |
c8546163 GC |
120 | #define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4) |
121 | #define QS_INJ_GRP_CFG_MODE(x) ((x) << 2) | |
122 | #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) | |
c8546163 GC |
123 | |
124 | #define IFH_INJ_BYPASS BIT(31) | |
6390da4a HV |
125 | #define IFH_TAG_TYPE_C 0 |
126 | #define MAC_VID 1 | |
c8546163 | 127 | #define CPU_PORT 11 |
6390da4a | 128 | #define INTERNAL_PORT_MSK 0x2FF |
c8546163 | 129 | #define IFH_LEN 4 |
c8546163 | 130 | #define ETH_ALEN 6 |
6390da4a HV |
131 | #define PGID_BROADCAST 13 |
132 | #define PGID_UNICAST 14 | |
133 | #define PGID_SRC 80 | |
c8546163 | 134 | |
6390da4a HV |
135 | static const char * const regs_names[] = { |
136 | "port0", "port1", "port2", "port3", "port4", "port5", "port6", "port7", | |
137 | "port8", "port9", "port10", "sys", "rew", "qs", "hsio", "qsys", "ana", | |
138 | }; | |
139 | ||
140 | #define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1 | |
141 | #define MAX_PORT 11 | |
142 | ||
143 | enum ocelot_ctrl_regs { | |
144 | SYS = MAX_PORT, | |
c8546163 | 145 | REW, |
6390da4a | 146 | QS, |
c8546163 | 147 | HSIO, |
6390da4a HV |
148 | QSYS, |
149 | ANA, | |
c8546163 GC |
150 | }; |
151 | ||
6390da4a | 152 | #define OCELOT_MIIM_BUS_COUNT 2 |
c8546163 | 153 | |
6390da4a HV |
154 | struct ocelot_phy_port_t { |
155 | size_t phy_addr; | |
156 | struct mii_dev *bus; | |
157 | u8 serdes_index; | |
158 | u8 phy_mode; | |
c8546163 GC |
159 | }; |
160 | ||
6390da4a HV |
161 | struct ocelot_private { |
162 | void __iomem *regs[REGS_NAMES_COUNT]; | |
163 | struct mii_dev *bus[OCELOT_MIIM_BUS_COUNT]; | |
164 | struct ocelot_phy_port_t ports[MAX_PORT]; | |
c8546163 GC |
165 | }; |
166 | ||
6390da4a HV |
167 | static struct mscc_miim_dev miim[OCELOT_MIIM_BUS_COUNT]; |
168 | static int miim_count = -1; | |
169 | ||
36d04f52 HV |
170 | static const unsigned long ocelot_regs_qs[] = { |
171 | [MSCC_QS_XTR_RD] = 0x8, | |
172 | [MSCC_QS_XTR_FLUSH] = 0x18, | |
173 | [MSCC_QS_XTR_DATA_PRESENT] = 0x1c, | |
174 | [MSCC_QS_INJ_WR] = 0x2c, | |
175 | [MSCC_QS_INJ_CTRL] = 0x34, | |
176 | }; | |
177 | ||
45f2748c HV |
178 | static const unsigned long ocelot_regs_ana_table[] = { |
179 | [MSCC_ANA_TABLES_MACHDATA] = 0x8b34, | |
180 | [MSCC_ANA_TABLES_MACLDATA] = 0x8b38, | |
181 | [MSCC_ANA_TABLES_MACACCESS] = 0x8b3c, | |
182 | }; | |
183 | ||
cd424f35 | 184 | static void mscc_phy_reset(void) |
c8546163 | 185 | { |
6390da4a | 186 | writel(0, BASE_DEVCPU_GCB + PERF_PHY_CFG + PHY_CFG); |
cd424f35 | 187 | writel(PHY_CFG_RST | PHY_CFG_COMMON_RST |
6390da4a HV |
188 | | PHY_CFG_ENA, BASE_DEVCPU_GCB + PERF_PHY_CFG + PHY_CFG); |
189 | if (wait_for_bit_le32((const void *)(BASE_DEVCPU_GCB + PERF_PHY_CFG) + | |
190 | PHY_STAT, PHY_STAT_SUPERVISOR_COMPLETE, | |
cd424f35 HV |
191 | true, 2000, false)) { |
192 | pr_err("Timeout in phy reset\n"); | |
c8546163 | 193 | } |
c8546163 GC |
194 | } |
195 | ||
c8546163 GC |
196 | __weak void mscc_switch_reset(void) |
197 | { | |
198 | } | |
199 | ||
200 | static void ocelot_stop(struct udevice *dev) | |
201 | { | |
c8546163 | 202 | mscc_switch_reset(); |
cd424f35 | 203 | mscc_phy_reset(); |
c8546163 GC |
204 | } |
205 | ||
206 | static void ocelot_cpu_capture_setup(struct ocelot_private *priv) | |
207 | { | |
208 | int i; | |
209 | ||
210 | /* map the 8 CPU extraction queues to CPU port 11 */ | |
211 | writel(0, priv->regs[QSYS] + QSYS_QMAP); | |
212 | ||
213 | for (i = 0; i <= 1; i++) { | |
214 | /* | |
215 | * Do byte-swap and expect status after last data word | |
216 | * Extraction: Mode: manual extraction) | Byte_swap | |
217 | */ | |
218 | writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP, | |
219 | priv->regs[QS] + QS_XTR_GRP_CFG(i)); | |
220 | /* | |
221 | * Injection: Mode: manual extraction | Byte_swap | |
222 | */ | |
223 | writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP, | |
224 | priv->regs[QS] + QS_INJ_GRP_CFG(i)); | |
225 | } | |
226 | ||
227 | for (i = 0; i <= 1; i++) | |
228 | /* Enable IFH insertion/parsing on CPU ports */ | |
229 | writel(SYS_PORT_MODE_INCL_INJ_HDR(1) | | |
230 | SYS_PORT_MODE_INCL_XTR_HDR(1), | |
231 | priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i)); | |
232 | /* | |
233 | * Setup the CPU port as VLAN aware to support switching frames | |
234 | * based on tags | |
235 | */ | |
236 | writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) | | |
237 | MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT)); | |
238 | ||
239 | /* Disable learning (only RECV_ENA must be set) */ | |
240 | writel(ANA_PORT_PORT_CFG_RECV_ENA, | |
241 | priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT)); | |
242 | ||
243 | /* Enable switching to/from cpu port */ | |
244 | setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT), | |
245 | QSYS_SWITCH_PORT_MODE_PORT_ENA); | |
246 | ||
247 | /* No pause on CPU port - not needed (off by default) */ | |
248 | clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT), | |
249 | SYS_PAUSE_CFG_PAUSE_ENA); | |
250 | ||
251 | setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT)); | |
252 | } | |
253 | ||
254 | static void ocelot_port_init(struct ocelot_private *priv, int port) | |
255 | { | |
256 | void __iomem *regs = priv->regs[port]; | |
257 | ||
258 | /* Enable PCS */ | |
259 | writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG); | |
260 | ||
261 | /* Disable Signal Detect */ | |
262 | writel(0, regs + PCS1G_SD_CFG); | |
263 | ||
264 | /* Enable MAC RX and TX */ | |
265 | writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA, | |
266 | regs + DEV_MAC_ENA_CFG); | |
267 | ||
268 | /* Clear sgmii_mode_ena */ | |
269 | writel(0, regs + PCS1G_MODE_CFG); | |
270 | ||
271 | /* | |
272 | * Clear sw_resolve_ena(bit 0) and set adv_ability to | |
273 | * something meaningful just in case | |
274 | */ | |
275 | writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG); | |
276 | ||
277 | /* Set MAC IFG Gaps */ | |
278 | writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) | | |
279 | DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG); | |
280 | ||
281 | /* Set link speed and release all resets */ | |
282 | writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG); | |
283 | ||
284 | /* Make VLAN aware for CPU traffic */ | |
285 | writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) | | |
6390da4a | 286 | MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port)); |
c8546163 GC |
287 | |
288 | /* Enable the port in the core */ | |
6390da4a | 289 | setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port), |
c8546163 GC |
290 | QSYS_SWITCH_PORT_MODE_PORT_ENA); |
291 | } | |
292 | ||
6390da4a HV |
293 | static void serdes1g_write(void __iomem *base, u32 addr) |
294 | { | |
295 | u32 data; | |
296 | ||
297 | writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT | | |
298 | HSIO_MCB_SERDES1G_CFG_ADDR(addr), | |
299 | base + HSIO_MCB_SERDES1G_CFG); | |
300 | ||
301 | do { | |
302 | data = readl(base + HSIO_MCB_SERDES1G_CFG); | |
303 | } while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT); | |
304 | } | |
305 | ||
306 | static void serdes1g_setup(void __iomem *base, uint32_t addr, | |
307 | phy_interface_t interface) | |
308 | { | |
309 | writel(0x34, base + HSIO_HW_CFGSTAT_HW_CFG); | |
310 | ||
311 | writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG); | |
312 | writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0); | |
313 | writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) | | |
314 | HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) | | |
315 | HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP | | |
316 | HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM | | |
317 | HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1), | |
318 | base + HSIO_ANA_SERDES1G_IB_CFG); | |
319 | writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) | | |
320 | HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) | | |
321 | HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) | | |
322 | HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6), | |
323 | base + HSIO_ANA_SERDES1G_DES_CFG); | |
324 | writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) | | |
325 | HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) | | |
326 | HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) | | |
327 | HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) | | |
328 | HSIO_ANA_SERDES1G_OB_CFG_SLP(3), | |
329 | base + HSIO_ANA_SERDES1G_OB_CFG); | |
330 | writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE | | |
331 | HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE, | |
332 | base + HSIO_ANA_SERDES1G_COMMON_CFG); | |
333 | writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA | | |
334 | HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) | | |
335 | HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2, | |
336 | base + HSIO_ANA_SERDES1G_PLL_CFG); | |
337 | writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST, | |
338 | base + HSIO_DIG_SERDES1G_MISC_CFG); | |
339 | ||
340 | serdes1g_write(base, addr); | |
341 | ||
342 | writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE | | |
343 | HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE | | |
344 | HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST, | |
345 | base + HSIO_ANA_SERDES1G_COMMON_CFG); | |
346 | serdes1g_write(base, addr); | |
347 | ||
348 | writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG); | |
349 | serdes1g_write(base, addr); | |
350 | } | |
351 | ||
352 | static void serdes_setup(struct ocelot_private *priv) | |
353 | { | |
354 | size_t mask; | |
355 | int i = 0; | |
356 | ||
357 | for (i = 0; i < MAX_PORT; ++i) { | |
358 | if (!priv->ports[i].bus || priv->ports[i].serdes_index == 0xff) | |
359 | continue; | |
360 | ||
361 | mask = BIT(priv->ports[i].serdes_index); | |
362 | serdes1g_setup(priv->regs[HSIO], mask, | |
363 | priv->ports[i].phy_mode); | |
364 | } | |
365 | } | |
366 | ||
c8546163 GC |
367 | static int ocelot_switch_init(struct ocelot_private *priv) |
368 | { | |
369 | /* Reset switch & memories */ | |
370 | writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT, | |
371 | priv->regs[SYS] + SYS_SYSTEM_RST_CFG); | |
372 | ||
373 | /* Wait to complete */ | |
374 | if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG, | |
375 | SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) { | |
376 | pr_err("Timeout in memory reset\n"); | |
377 | return -EIO; | |
378 | } | |
379 | ||
380 | /* Enable switch core */ | |
381 | setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG, | |
382 | SYS_SYSTEM_RST_CORE_ENA); | |
383 | ||
6390da4a | 384 | serdes_setup(priv); |
c8546163 GC |
385 | return 0; |
386 | } | |
387 | ||
c8546163 GC |
388 | static int ocelot_initialize(struct ocelot_private *priv) |
389 | { | |
390 | int ret, i; | |
391 | ||
392 | /* Initialize switch memories, enable core */ | |
393 | ret = ocelot_switch_init(priv); | |
394 | if (ret) | |
395 | return ret; | |
396 | /* | |
397 | * Disable port-to-port by switching | |
398 | * Put fron ports in "port isolation modes" - i.e. they cant send | |
399 | * to other ports - via the PGID sorce masks. | |
400 | */ | |
6390da4a | 401 | for (i = 0; i < MAX_PORT; i++) |
c8546163 GC |
402 | writel(0, priv->regs[ANA] + ANA_PGID(PGID_SRC + i)); |
403 | ||
404 | /* Flush queues */ | |
36d04f52 | 405 | mscc_flush(priv->regs[QS], ocelot_regs_qs); |
c8546163 GC |
406 | |
407 | /* Setup frame ageing - "2 sec" - The unit is 6.5us on Ocelot */ | |
408 | writel(SYS_FRM_AGING_ENA | (20000000 / 65), | |
409 | priv->regs[SYS] + SYS_FRM_AGING); | |
410 | ||
6390da4a | 411 | for (i = 0; i < MAX_PORT; i++) |
c8546163 GC |
412 | ocelot_port_init(priv, i); |
413 | ||
414 | ocelot_cpu_capture_setup(priv); | |
415 | ||
416 | debug("Ports enabled\n"); | |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
c8546163 GC |
421 | static int ocelot_write_hwaddr(struct udevice *dev) |
422 | { | |
423 | struct ocelot_private *priv = dev_get_priv(dev); | |
c69cda25 | 424 | struct eth_pdata *pdata = dev_get_plat(dev); |
c8546163 | 425 | |
45f2748c HV |
426 | mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table, |
427 | pdata->enetaddr, PGID_UNICAST); | |
c8546163 GC |
428 | |
429 | writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST)); | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
434 | static int ocelot_start(struct udevice *dev) | |
435 | { | |
436 | struct ocelot_private *priv = dev_get_priv(dev); | |
c69cda25 | 437 | struct eth_pdata *pdata = dev_get_plat(dev); |
c8546163 GC |
438 | const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, |
439 | 0xff }; | |
440 | int ret; | |
441 | ||
442 | ret = ocelot_initialize(priv); | |
443 | if (ret) | |
444 | return ret; | |
445 | ||
446 | /* Set MAC address tables entries for CPU redirection */ | |
45f2748c HV |
447 | mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table, mac, |
448 | PGID_BROADCAST); | |
c8546163 GC |
449 | |
450 | writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK, | |
451 | priv->regs[ANA] + ANA_PGID(PGID_BROADCAST)); | |
452 | ||
453 | /* It should be setup latter in ocelot_write_hwaddr */ | |
45f2748c HV |
454 | mscc_mac_table_add(priv->regs[ANA], ocelot_regs_ana_table, |
455 | pdata->enetaddr, PGID_UNICAST); | |
c8546163 GC |
456 | |
457 | writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST)); | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
462 | static int ocelot_send(struct udevice *dev, void *packet, int length) | |
463 | { | |
464 | struct ocelot_private *priv = dev_get_priv(dev); | |
465 | u32 ifh[IFH_LEN]; | |
466 | int port = BIT(0); /* use port 0 */ | |
c8546163 GC |
467 | u32 *buf = packet; |
468 | ||
c8546163 GC |
469 | /* |
470 | * Generate the IFH for frame injection | |
471 | * | |
472 | * The IFH is a 128bit-value | |
473 | * bit 127: bypass the analyzer processing | |
474 | * bit 56-67: destination mask | |
475 | * bit 28-29: pop_cnt: 3 disables all rewriting of the frame | |
476 | * bit 20-27: cpu extraction queue mask | |
477 | * bit 16: tag type 0: C-tag, 1: S-tag | |
478 | * bit 0-11: VID | |
479 | */ | |
480 | ifh[0] = IFH_INJ_BYPASS; | |
481 | ifh[1] = (0xf00 & port) >> 8; | |
482 | ifh[2] = (0xff & port) << 24; | |
483 | ifh[3] = (IFH_TAG_TYPE_C << 16); | |
484 | ||
36d04f52 HV |
485 | return mscc_send(priv->regs[QS], ocelot_regs_qs, |
486 | ifh, IFH_LEN, buf, length); | |
c8546163 GC |
487 | } |
488 | ||
489 | static int ocelot_recv(struct udevice *dev, int flags, uchar **packetp) | |
490 | { | |
491 | struct ocelot_private *priv = dev_get_priv(dev); | |
c8546163 | 492 | u32 *rxbuf = (u32 *)net_rx_packets[0]; |
36d04f52 | 493 | int byte_cnt; |
c8546163 | 494 | |
36d04f52 HV |
495 | byte_cnt = mscc_recv(priv->regs[QS], ocelot_regs_qs, rxbuf, IFH_LEN, |
496 | false); | |
c8546163 GC |
497 | |
498 | *packetp = net_rx_packets[0]; | |
499 | ||
500 | return byte_cnt; | |
501 | } | |
502 | ||
6390da4a HV |
503 | static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size) |
504 | { | |
505 | int i = 0; | |
506 | ||
507 | for (i = 0; i < OCELOT_MIIM_BUS_COUNT; ++i) | |
508 | if (miim[i].miim_base == base && miim[i].miim_size == size) | |
509 | return miim[i].bus; | |
510 | ||
511 | return NULL; | |
512 | } | |
513 | ||
514 | static void add_port_entry(struct ocelot_private *priv, size_t index, | |
515 | size_t phy_addr, struct mii_dev *bus, | |
516 | u8 serdes_index, u8 phy_mode) | |
517 | { | |
518 | priv->ports[index].phy_addr = phy_addr; | |
519 | priv->ports[index].bus = bus; | |
520 | priv->ports[index].serdes_index = serdes_index; | |
521 | priv->ports[index].phy_mode = phy_mode; | |
522 | } | |
523 | ||
524 | static int external_bus(struct ocelot_private *priv, size_t port_index) | |
525 | { | |
526 | return priv->ports[port_index].serdes_index != 0xff; | |
527 | } | |
528 | ||
c8546163 GC |
529 | static int ocelot_probe(struct udevice *dev) |
530 | { | |
531 | struct ocelot_private *priv = dev_get_priv(dev); | |
6390da4a HV |
532 | int i, ret; |
533 | struct resource res; | |
6390da4a HV |
534 | phys_addr_t addr_base; |
535 | unsigned long addr_size; | |
536 | ofnode eth_node, node, mdio_node; | |
537 | size_t phy_addr; | |
538 | struct mii_dev *bus; | |
539 | struct ofnode_phandle_args phandle; | |
540 | struct phy_device *phy; | |
541 | ||
542 | if (!priv) | |
543 | return -EINVAL; | |
c8546163 | 544 | |
6390da4a HV |
545 | for (i = 0; i < ARRAY_SIZE(regs_names); i++) { |
546 | priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]); | |
547 | if (!priv->regs[i]) { | |
548 | debug | |
549 | ("Error can't get regs base addresses for %s\n", | |
550 | regs_names[i]); | |
c8546163 GC |
551 | return -ENOMEM; |
552 | } | |
553 | } | |
554 | ||
6390da4a HV |
555 | /* Initialize miim buses */ |
556 | memset(&miim, 0x0, sizeof(struct mscc_miim_dev) * | |
557 | OCELOT_MIIM_BUS_COUNT); | |
558 | ||
559 | /* iterate all the ports and find out on which bus they are */ | |
560 | i = 0; | |
561 | eth_node = dev_read_first_subnode(dev); | |
562 | for (node = ofnode_first_subnode(eth_node); ofnode_valid(node); | |
563 | node = ofnode_next_subnode(node)) { | |
564 | if (ofnode_read_resource(node, 0, &res)) | |
565 | return -ENOMEM; | |
566 | i = res.start; | |
567 | ||
568 | ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0, | |
569 | &phandle); | |
570 | ||
571 | /* Get phy address on mdio bus */ | |
572 | if (ofnode_read_resource(phandle.node, 0, &res)) | |
573 | return -ENOMEM; | |
574 | phy_addr = res.start; | |
575 | ||
576 | /* Get mdio node */ | |
577 | mdio_node = ofnode_get_parent(phandle.node); | |
578 | ||
579 | if (ofnode_read_resource(mdio_node, 0, &res)) | |
580 | return -ENOMEM; | |
6390da4a | 581 | |
feb7ac45 | 582 | addr_base = res.start; |
6390da4a HV |
583 | addr_size = res.end - res.start; |
584 | ||
585 | /* If the bus is new then create a new bus */ | |
586 | if (!get_mdiobus(addr_base, addr_size)) | |
587 | priv->bus[miim_count] = | |
61243678 HV |
588 | mscc_mdiobus_init(miim, &miim_count, addr_base, |
589 | addr_size); | |
6390da4a HV |
590 | |
591 | /* Connect mdio bus with the port */ | |
592 | bus = get_mdiobus(addr_base, addr_size); | |
593 | ||
594 | /* Get serdes info */ | |
595 | ret = ofnode_parse_phandle_with_args(node, "phys", NULL, | |
596 | 3, 0, &phandle); | |
597 | if (ret) | |
598 | add_port_entry(priv, i, phy_addr, bus, 0xff, 0xff); | |
599 | else | |
600 | add_port_entry(priv, i, phy_addr, bus, phandle.args[1], | |
601 | phandle.args[2]); | |
602 | } | |
603 | ||
cd424f35 | 604 | mscc_phy_reset(); |
c8546163 | 605 | |
6390da4a HV |
606 | for (i = 0; i < MAX_PORT; i++) { |
607 | if (!priv->ports[i].bus) | |
608 | continue; | |
609 | ||
610 | phy = phy_connect(priv->ports[i].bus, | |
611 | priv->ports[i].phy_addr, dev, | |
ffb0f6f4 | 612 | PHY_INTERFACE_MODE_NA); |
6390da4a HV |
613 | if (phy && external_bus(priv, i)) |
614 | board_phy_config(phy); | |
c8546163 GC |
615 | } |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
620 | static int ocelot_remove(struct udevice *dev) | |
621 | { | |
622 | struct ocelot_private *priv = dev_get_priv(dev); | |
623 | int i; | |
624 | ||
6390da4a | 625 | for (i = 0; i < OCELOT_MIIM_BUS_COUNT; i++) { |
c8546163 GC |
626 | mdio_unregister(priv->bus[i]); |
627 | mdio_free(priv->bus[i]); | |
628 | } | |
629 | ||
630 | return 0; | |
631 | } | |
632 | ||
633 | static const struct eth_ops ocelot_ops = { | |
634 | .start = ocelot_start, | |
635 | .stop = ocelot_stop, | |
636 | .send = ocelot_send, | |
637 | .recv = ocelot_recv, | |
638 | .write_hwaddr = ocelot_write_hwaddr, | |
639 | }; | |
640 | ||
641 | static const struct udevice_id mscc_ocelot_ids[] = { | |
642 | {.compatible = "mscc,vsc7514-switch"}, | |
643 | { /* Sentinel */ } | |
644 | }; | |
645 | ||
646 | U_BOOT_DRIVER(ocelot) = { | |
647 | .name = "ocelot-switch", | |
648 | .id = UCLASS_ETH, | |
649 | .of_match = mscc_ocelot_ids, | |
650 | .probe = ocelot_probe, | |
651 | .remove = ocelot_remove, | |
652 | .ops = &ocelot_ops, | |
41575d8e | 653 | .priv_auto = sizeof(struct ocelot_private), |
caa4daa2 | 654 | .plat_auto = sizeof(struct eth_pdata), |
c8546163 | 655 | }; |