[thirdparty/u-boot.git] / drivers / net / mscc_eswitch / serval_switch.c

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Microsemi Corporation
 */

#include <common.h>
#include <config.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
#include <dm/of_access.h>
#include <dm/of_addr.h>
#include <fdt_support.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <miiphy.h>
#include <net.h>
#include <wait_bit.h>
#include <linux/printk.h>

#include "mscc_xfer.h"
#include "mscc_mac_table.h"
#include "mscc_miim.h"

#define ANA_PORT_VLAN_CFG(x)			(0xc000 + 0x100 * (x))
#define		ANA_PORT_VLAN_CFG_AWARE_ENA		BIT(20)
#define		ANA_PORT_VLAN_CFG_POP_CNT(x)		((x) << 18)
#define ANA_PORT_PORT_CFG(x)			(0xc070 + 0x100 * (x))
#define		ANA_PORT_PORT_CFG_RECV_ENA		BIT(6)
#define ANA_PGID(x)				(0x9c00 + 4 * (x))

#define HSIO_ANA_SERDES1G_DES_CFG		0x3c
#define		HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x)		((x) << 1)
#define		HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x)		((x) << 5)
#define		HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x)		((x) << 8)
#define		HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x)		((x) << 13)
#define HSIO_ANA_SERDES1G_IB_CFG		0x40
#define		HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x)	(x)
#define		HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x)		((x) << 6)
#define		HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP	BIT(9)
#define		HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV		BIT(11)
#define		HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM		BIT(13)
#define		HSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x)		((x) << 19)
#define		HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x)		((x) << 24)
#define HSIO_ANA_SERDES1G_OB_CFG		0x44
#define		HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x)	(x)
#define		HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x)		((x) << 4)
#define		HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x)	((x) << 10)
#define		HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x)		((x) << 13)
#define		HSIO_ANA_SERDES1G_OB_CFG_SLP(x)			((x) << 17)
#define HSIO_ANA_SERDES1G_SER_CFG		0x48
#define HSIO_ANA_SERDES1G_COMMON_CFG		0x4c
#define		HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE		BIT(0)
#define		HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE		BIT(18)
#define		HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST		BIT(31)
#define HSIO_ANA_SERDES1G_PLL_CFG		0x50
#define		HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA		BIT(7)
#define		HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x)	((x) << 8)
#define		HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2		BIT(21)
#define HSIO_DIG_SERDES1G_DFT_CFG0		0x58
#define HSIO_DIG_SERDES1G_MISC_CFG		0x6c
#define		HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST		BIT(0)
#define HSIO_MCB_SERDES1G_CFG			0x74
#define		HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT	BIT(31)
#define		HSIO_MCB_SERDES1G_CFG_ADDR(x)		(x)

#define SYS_FRM_AGING				0x584
#define		SYS_FRM_AGING_ENA			BIT(20)
#define SYS_SYSTEM_RST_CFG			0x518
#define		SYS_SYSTEM_RST_MEM_INIT			BIT(5)
#define		SYS_SYSTEM_RST_MEM_ENA			BIT(6)
#define		SYS_SYSTEM_RST_CORE_ENA			BIT(7)
#define SYS_PORT_MODE(x)			(0x524 + 0x4 * (x))
#define		SYS_PORT_MODE_INCL_INJ_HDR(x)		((x) << 4)
#define		SYS_PORT_MODE_INCL_XTR_HDR(x)		((x) << 2)
#define SYS_PAUSE_CFG(x)			(0x65c + 0x4 * (x))
#define		SYS_PAUSE_CFG_PAUSE_ENA			BIT(0)

#define QSYS_SWITCH_PORT_MODE(x)		(0x15a34 + 0x4 * (x))
#define		QSYS_SWITCH_PORT_MODE_PORT_ENA		BIT(13)
#define QSYS_EGR_NO_SHARING			0x15a9c
#define QSYS_QMAP				0x15adc

/* Port registers */
#define DEV_CLOCK_CFG				0x0
#define DEV_CLOCK_CFG_LINK_SPEED_1000			1
#define DEV_MAC_ENA_CFG				0x10
#define		DEV_MAC_ENA_CFG_RX_ENA			BIT(4)
#define		DEV_MAC_ENA_CFG_TX_ENA			BIT(0)
#define DEV_MAC_IFG_CFG				0x24
#define		DEV_MAC_IFG_CFG_TX_IFG(x)		((x) << 8)
#define		DEV_MAC_IFG_CFG_RX_IFG2(x)		((x) << 4)
#define		DEV_MAC_IFG_CFG_RX_IFG1(x)		(x)
#define PCS1G_CFG				0x3c
#define		PCS1G_MODE_CFG_SGMII_MODE_ENA		BIT(0)
#define PCS1G_MODE_CFG				0x40
#define PCS1G_SD_CFG				0x44
#define PCS1G_ANEG_CFG				0x48
#define		PCS1G_ANEG_CFG_ADV_ABILITY(x)		((x) << 16)

#define QS_XTR_GRP_CFG(x)			(4 * (x))
#define		QS_XTR_GRP_CFG_MODE(x)			((x) << 2)
#define		QS_XTR_GRP_CFG_BYTE_SWAP		BIT(0)
#define QS_INJ_GRP_CFG(x)			(0x24 + (x) * 4)
#define		QS_INJ_GRP_CFG_MODE(x)			((x) << 2)
#define		QS_INJ_GRP_CFG_BYTE_SWAP		BIT(0)

#define IFH_INJ_BYPASS		BIT(31)
#define IFH_TAG_TYPE_C		0
#define MAC_VID			1
#define CPU_PORT		11
#define INTERNAL_PORT_MSK	0xFF
#define IFH_LEN			4
#define ETH_ALEN		6
#define PGID_BROADCAST		13
#define PGID_UNICAST		14

static const char *const regs_names[] = {
	"port0", "port1", "port2", "port3", "port4", "port5", "port6",
	"port7", "port8", "port9", "port10",
	"ana", "qs", "qsys", "rew", "sys", "hsio",
};

#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
#define MAX_PORT 11

enum serval_ctrl_regs {
	ANA = MAX_PORT,
	QS,
	QSYS,
	REW,
	SYS,
	HSIO,
};

#define SERVAL_MIIM_BUS_COUNT 2

struct serval_phy_port_t {
	size_t phy_addr;
	struct mii_dev *bus;
	u8 serdes_index;
	u8 phy_mode;
};

struct serval_private {
	void __iomem *regs[REGS_NAMES_COUNT];
	struct mii_dev *bus[SERVAL_MIIM_BUS_COUNT];
	struct serval_phy_port_t ports[MAX_PORT];
};

static const unsigned long serval_regs_qs[] = {
	[MSCC_QS_XTR_RD] = 0x8,
	[MSCC_QS_XTR_FLUSH] = 0x18,
	[MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
	[MSCC_QS_INJ_WR] = 0x2c,
	[MSCC_QS_INJ_CTRL] = 0x34,
};

static const unsigned long serval_regs_ana_table[] = {
	[MSCC_ANA_TABLES_MACHDATA] = 0x9b34,
	[MSCC_ANA_TABLES_MACLDATA] = 0x9b38,
	[MSCC_ANA_TABLES_MACACCESS] = 0x9b3c,
};

static struct mscc_miim_dev miim[SERVAL_MIIM_BUS_COUNT];
static int miim_count = -1;

static void serval_cpu_capture_setup(struct serval_private *priv)
{
	int i;

	/* map the 8 CPU extraction queues to CPU port 11 */
	writel(0, priv->regs[QSYS] + QSYS_QMAP);

	for (i = 0; i <= 1; i++) {
		/*
		 * Do byte-swap and expect status after last data word
		 * Extraction: Mode: manual extraction) | Byte_swap
		 */
		writel(QS_XTR_GRP_CFG_MODE(1) | QS_XTR_GRP_CFG_BYTE_SWAP,
		       priv->regs[QS] + QS_XTR_GRP_CFG(i));
		/*
		 * Injection: Mode: manual extraction | Byte_swap
		 */
		writel(QS_INJ_GRP_CFG_MODE(1) | QS_INJ_GRP_CFG_BYTE_SWAP,
		       priv->regs[QS] + QS_INJ_GRP_CFG(i));
	}

	for (i = 0; i <= 1; i++)
		/* Enable IFH insertion/parsing on CPU ports */
		writel(SYS_PORT_MODE_INCL_INJ_HDR(1) |
		       SYS_PORT_MODE_INCL_XTR_HDR(1),
		       priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));
	/*
	 * Setup the CPU port as VLAN aware to support switching frames
	 * based on tags
	 */
	writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
	       MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));

	/* Disable learning (only RECV_ENA must be set) */
	writel(ANA_PORT_PORT_CFG_RECV_ENA,
	       priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));

	/* Enable switching to/from cpu port */
	setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),
		     QSYS_SWITCH_PORT_MODE_PORT_ENA);

	/* No pause on CPU port - not needed (off by default) */
	clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),
		     SYS_PAUSE_CFG_PAUSE_ENA);

	setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));
}

static void serval_port_init(struct serval_private *priv, int port)
{
	void __iomem *regs = priv->regs[port];

	/* Enable PCS */
	writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG);

	/* Disable Signal Detect */
	writel(0, regs + PCS1G_SD_CFG);

	/* Enable MAC RX and TX */
	writel(DEV_MAC_ENA_CFG_RX_ENA | DEV_MAC_ENA_CFG_TX_ENA,
	       regs + DEV_MAC_ENA_CFG);

	/* Clear sgmii_mode_ena */
	writel(0, regs + PCS1G_MODE_CFG);

	/*
	 * Clear sw_resolve_ena(bit 0) and set adv_ability to
	 * something meaningful just in case
	 */
	writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG);

	/* Set MAC IFG Gaps */
	writel(DEV_MAC_IFG_CFG_TX_IFG(5) | DEV_MAC_IFG_CFG_RX_IFG1(5) |
	       DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG);

	/* Set link speed and release all resets */
	writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG);

	/* Make VLAN aware for CPU traffic */
	writel(ANA_PORT_VLAN_CFG_AWARE_ENA | ANA_PORT_VLAN_CFG_POP_CNT(1) |
	       MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));

	/* Enable the port in the core */
	setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port),
		     QSYS_SWITCH_PORT_MODE_PORT_ENA);
}

static void serdes_write(void __iomem *base, u32 addr)
{
	u32 data;

	writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT |
	       HSIO_MCB_SERDES1G_CFG_ADDR(addr),
	       base + HSIO_MCB_SERDES1G_CFG);

	do {
		data = readl(base + HSIO_MCB_SERDES1G_CFG);
	} while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
}

static void serdes1g_setup(void __iomem *base, uint32_t addr,
			   phy_interface_t interface)
{
	writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG);
	writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0);
	writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) |
	       HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) |
	       HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP |
	       HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM |
	       HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1),
	       base + HSIO_ANA_SERDES1G_IB_CFG);
	writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) |
	       HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) |
	       HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) |
	       HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6),
	       base + HSIO_ANA_SERDES1G_DES_CFG);
	writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) |
	       HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) |
	       HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) |
	       HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) |
	       HSIO_ANA_SERDES1G_OB_CFG_SLP(3),
	       base + HSIO_ANA_SERDES1G_OB_CFG);
	writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
	       HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE,
	       base + HSIO_ANA_SERDES1G_COMMON_CFG);
	writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA |
	       HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) |
	       HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2,
	       base + HSIO_ANA_SERDES1G_PLL_CFG);
	writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST,
	       base + HSIO_DIG_SERDES1G_MISC_CFG);
	serdes_write(base, addr);

	writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE |
	       HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE |
	       HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST,
	       base + HSIO_ANA_SERDES1G_COMMON_CFG);
	serdes_write(base, addr);

	writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG);
	serdes_write(base, addr);
}

static void serdes_setup(struct serval_private *priv)
{
	size_t mask;
	int i = 0;

	for (i = 0; i < MAX_PORT; ++i) {
		if (!priv->ports[i].bus)
			continue;

		mask = BIT(priv->ports[i].serdes_index);
		serdes1g_setup(priv->regs[HSIO], mask,
			       priv->ports[i].phy_mode);
	}
}

static int serval_switch_init(struct serval_private *priv)
{
	/* Reset switch & memories */
	writel(SYS_SYSTEM_RST_MEM_ENA | SYS_SYSTEM_RST_MEM_INIT,
	       priv->regs[SYS] + SYS_SYSTEM_RST_CFG);

	if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
			      SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
		pr_err("Timeout in memory reset\n");
		return -EIO;
	}

	/* Enable switch core */
	setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
		     SYS_SYSTEM_RST_CORE_ENA);

	serdes_setup(priv);

	return 0;
}

static int serval_initialize(struct serval_private *priv)
{
	int ret, i;

	/* Initialize switch memories, enable core */
	ret = serval_switch_init(priv);
	if (ret)
		return ret;

	/* Flush queues */
	mscc_flush(priv->regs[QS], serval_regs_qs);

	/* Setup frame ageing - "2 sec" - The unit is 6.5us on serval */
	writel(SYS_FRM_AGING_ENA | (20000000 / 65),
	       priv->regs[SYS] + SYS_FRM_AGING);

	for (i = 0; i < MAX_PORT; i++)
		serval_port_init(priv, i);

	serval_cpu_capture_setup(priv);

	debug("Ports enabled\n");

	return 0;
}

static int serval_write_hwaddr(struct udevice *dev)
{
	struct serval_private *priv = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);

	mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
			   pdata->enetaddr, PGID_UNICAST);

	writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));

	return 0;
}

static int serval_start(struct udevice *dev)
{
	struct serval_private *priv = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
					      0xff };
	int ret;

	ret = serval_initialize(priv);
	if (ret)
		return ret;

	/* Set MAC address tables entries for CPU redirection */
	mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table, mac,
			   PGID_BROADCAST);

	writel(BIT(CPU_PORT) | INTERNAL_PORT_MSK,
	       priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));

	/* It should be setup latter in serval_write_hwaddr */
	mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
			   pdata->enetaddr, PGID_UNICAST);

	writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
	return 0;
}

static void serval_stop(struct udevice *dev)
{
	writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
	writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
}

static int serval_send(struct udevice *dev, void *packet, int length)
{
	struct serval_private *priv = dev_get_priv(dev);
	u32 ifh[IFH_LEN];
	u32 *buf = packet;

	/*
	 * Generate the IFH for frame injection
	 *
	 * The IFH is a 128bit-value
	 * bit 127: bypass the analyzer processing
	 * bit 57-67: destination mask
	 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame
	 * bit 20-27: cpu extraction queue mask
	 * bit 16: tag type 0: C-tag, 1: S-tag
	 * bit 0-11: VID
	 */
	ifh[0] = IFH_INJ_BYPASS;
	ifh[1] = (0x07);
	ifh[2] = (0x7f) << 25;
	ifh[3] = (IFH_TAG_TYPE_C << 16);

	return mscc_send(priv->regs[QS], serval_regs_qs,
			 ifh, IFH_LEN, buf, length);
}

static int serval_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct serval_private *priv = dev_get_priv(dev);
	u32 *rxbuf = (u32 *)net_rx_packets[0];
	int byte_cnt = 0;

	byte_cnt = mscc_recv(priv->regs[QS], serval_regs_qs, rxbuf, IFH_LEN,
			     false);

	*packetp = net_rx_packets[0];

	return byte_cnt;
}

static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
{
	int i = 0;

	for (i = 0; i < SERVAL_MIIM_BUS_COUNT; ++i)
		if (miim[i].miim_base == base && miim[i].miim_size == size)
			return miim[i].bus;

	return NULL;
}

static void add_port_entry(struct serval_private *priv, size_t index,
			   size_t phy_addr, struct mii_dev *bus,
			   u8 serdes_index, u8 phy_mode)
{
	priv->ports[index].phy_addr = phy_addr;
	priv->ports[index].bus = bus;
	priv->ports[index].serdes_index = serdes_index;
	priv->ports[index].phy_mode = phy_mode;
}

static int serval_probe(struct udevice *dev)
{
	struct serval_private *priv = dev_get_priv(dev);
	int i, ret;
	struct resource res;
	phys_addr_t addr_base;
	unsigned long addr_size;
	ofnode eth_node, node, mdio_node;
	size_t phy_addr;
	struct mii_dev *bus;
	struct ofnode_phandle_args phandle;
	struct phy_device *phy;

	if (!priv)
		return -EINVAL;

	/* Get registers and map them to the private structure */
	for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
		priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
		if (!priv->regs[i]) {
			debug
			    ("Error can't get regs base addresses for %s\n",
			     regs_names[i]);
			return -ENOMEM;
		}
	}

	/* Initialize miim buses */
	memset(&miim, 0x0, sizeof(miim) * SERVAL_MIIM_BUS_COUNT);

	/* iterate all the ports and find out on which bus they are */
	i = 0;
	eth_node = dev_read_first_subnode(dev);
	for (node = ofnode_first_subnode(eth_node);
	     ofnode_valid(node);
	     node = ofnode_next_subnode(node)) {
		if (ofnode_read_resource(node, 0, &res))
			return -ENOMEM;
		i = res.start;

		ret = ofnode_parse_phandle_with_args(node, "phy-handle", NULL,
						     0, 0, &phandle);
		if (ret)
			continue;

		/* Get phy address on mdio bus */
		if (ofnode_read_resource(phandle.node, 0, &res))
			return -ENOMEM;
		phy_addr = res.start;

		/* Get mdio node */
		mdio_node = ofnode_get_parent(phandle.node);

		if (ofnode_read_resource(mdio_node, 0, &res))
			return -ENOMEM;

		addr_base = res.start;
		addr_size = res.end - res.start;

		/* If the bus is new then create a new bus */
		if (!get_mdiobus(addr_base, addr_size))
			priv->bus[miim_count] =
				mscc_mdiobus_init(miim, &miim_count, addr_base,
						  addr_size);

		/* Connect mdio bus with the port */
		bus = get_mdiobus(addr_base, addr_size);

		/* Get serdes info */
		ret = ofnode_parse_phandle_with_args(node, "phys", NULL,
						     3, 0, &phandle);
		if (ret)
			return -ENOMEM;

		add_port_entry(priv, i, phy_addr, bus, phandle.args[1],
			       phandle.args[2]);
	}

	for (i = 0; i < MAX_PORT; i++) {
		if (!priv->ports[i].bus)
			continue;

		phy = phy_connect(priv->ports[i].bus,
				  priv->ports[i].phy_addr, dev,
				  PHY_INTERFACE_MODE_NA);
		if (phy)
			board_phy_config(phy);
	}

	return 0;
}

static int serval_remove(struct udevice *dev)
{
	struct serval_private *priv = dev_get_priv(dev);
	int i;

	for (i = 0; i < SERVAL_MIIM_BUS_COUNT; i++) {
		mdio_unregister(priv->bus[i]);
		mdio_free(priv->bus[i]);
	}

	return 0;
}

static const struct eth_ops serval_ops = {
	.start        = serval_start,
	.stop         = serval_stop,
	.send         = serval_send,
	.recv         = serval_recv,
	.write_hwaddr = serval_write_hwaddr,
};

static const struct udevice_id mscc_serval_ids[] = {
	{.compatible = "mscc,vsc7418-switch"},
	{ /* Sentinel */ }
};

U_BOOT_DRIVER(serval) = {
	.name				= "serval-switch",
	.id				= UCLASS_ETH,
	.of_match			= mscc_serval_ids,
	.probe				= serval_probe,
	.remove				= serval_remove,
	.ops				= &serval_ops,
	.priv_auto		= sizeof(struct serval_private),
	.plat_auto	= sizeof(struct eth_pdata),
};
Commit	Line	Data
8cf94732 HV	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2019 Microsemi Corporation
	4	*/
	5
d678a59d	6	#include <common.h>
8cf94732 HV	7	#include <config.h>
8cf94732 HV	8	#include <dm.h>
f7ae49fc	9	#include <log.h>
336d4615	10	#include <malloc.h>
8cf94732 HV	11	#include <dm/of_access.h>
	12	#include <dm/of_addr.h>
	13	#include <fdt_support.h>
cd93d625	14	#include <linux/bitops.h>
8cf94732 HV	15	#include <linux/io.h>
	16	#include <linux/ioport.h>
	17	#include <miiphy.h>
	18	#include <net.h>
	19	#include <wait_bit.h>
1e94b46f	20	#include <linux/printk.h>
8cf94732 HV	21
	22	#include "mscc_xfer.h"
	23	#include "mscc_mac_table.h"
61243678	24	#include "mscc_miim.h"
8cf94732 HV	25
	26	#define ANA_PORT_VLAN_CFG(x) (0xc000 + 0x100 * (x))
	27	#define ANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
	28	#define ANA_PORT_VLAN_CFG_POP_CNT(x) ((x) << 18)
	29	#define ANA_PORT_PORT_CFG(x) (0xc070 + 0x100 * (x))
	30	#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
	31	#define ANA_PGID(x) (0x9c00 + 4 * (x))
	32
	33	#define HSIO_ANA_SERDES1G_DES_CFG 0x3c
	34	#define HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(x) ((x) << 1)
	35	#define HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(x) ((x) << 5)
	36	#define HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(x) ((x) << 8)
	37	#define HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(x) ((x) << 13)
	38	#define HSIO_ANA_SERDES1G_IB_CFG 0x40
	39	#define HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(x) (x)
	40	#define HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(x) ((x) << 6)
	41	#define HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP BIT(9)
	42	#define HSIO_ANA_SERDES1G_IB_CFG_ENA_DETLEV BIT(11)
	43	#define HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM BIT(13)
	44	#define HSIO_ANA_SERDES1G_IB_CFG_DET_LEV(x) ((x) << 19)
	45	#define HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(x) ((x) << 24)
	46	#define HSIO_ANA_SERDES1G_OB_CFG 0x44
	47	#define HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(x) (x)
	48	#define HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(x) ((x) << 4)
	49	#define HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(x) ((x) << 10)
	50	#define HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(x) ((x) << 13)
	51	#define HSIO_ANA_SERDES1G_OB_CFG_SLP(x) ((x) << 17)
	52	#define HSIO_ANA_SERDES1G_SER_CFG 0x48
	53	#define HSIO_ANA_SERDES1G_COMMON_CFG 0x4c
	54	#define HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE BIT(0)
	55	#define HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE BIT(18)
	56	#define HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST BIT(31)
	57	#define HSIO_ANA_SERDES1G_PLL_CFG 0x50
	58	#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA BIT(7)
	59	#define HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(x) ((x) << 8)
	60	#define HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2 BIT(21)
	61	#define HSIO_DIG_SERDES1G_DFT_CFG0 0x58
	62	#define HSIO_DIG_SERDES1G_MISC_CFG 0x6c
	63	#define HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST BIT(0)
	64	#define HSIO_MCB_SERDES1G_CFG 0x74
	65	#define HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT BIT(31)
	66	#define HSIO_MCB_SERDES1G_CFG_ADDR(x) (x)
	67
	68	#define SYS_FRM_AGING 0x584
	69	#define SYS_FRM_AGING_ENA BIT(20)
	70	#define SYS_SYSTEM_RST_CFG 0x518
	71	#define SYS_SYSTEM_RST_MEM_INIT BIT(5)
	72	#define SYS_SYSTEM_RST_MEM_ENA BIT(6)
	73	#define SYS_SYSTEM_RST_CORE_ENA BIT(7)
	74	#define SYS_PORT_MODE(x) (0x524 + 0x4 * (x))
	75	#define SYS_PORT_MODE_INCL_INJ_HDR(x) ((x) << 4)
	76	#define SYS_PORT_MODE_INCL_XTR_HDR(x) ((x) << 2)
	77	#define SYS_PAUSE_CFG(x) (0x65c + 0x4 * (x))
	78	#define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
	79
	80	#define QSYS_SWITCH_PORT_MODE(x) (0x15a34 + 0x4 * (x))
	81	#define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(13)
	82	#define QSYS_EGR_NO_SHARING 0x15a9c
	83	#define QSYS_QMAP 0x15adc
	84
	85	/* Port registers */
	86	#define DEV_CLOCK_CFG 0x0
	87	#define DEV_CLOCK_CFG_LINK_SPEED_1000 1
	88	#define DEV_MAC_ENA_CFG 0x10
89	#define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
90	#define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
91	#define DEV_MAC_IFG_CFG 0x24
92	#define DEV_MAC_IFG_CFG_TX_IFG(x) ((x) << 8)
93	#define DEV_MAC_IFG_CFG_RX_IFG2(x) ((x) << 4)
94	#define DEV_MAC_IFG_CFG_RX_IFG1(x) (x)
95	#define PCS1G_CFG 0x3c
96	#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
97	#define PCS1G_MODE_CFG 0x40
98	#define PCS1G_SD_CFG 0x44
99	#define PCS1G_ANEG_CFG 0x48
100	#define PCS1G_ANEG_CFG_ADV_ABILITY(x) ((x) << 16)
101
102	#define QS_XTR_GRP_CFG(x) (4 * (x))
103	#define QS_XTR_GRP_CFG_MODE(x) ((x) << 2)
104	#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)
105	#define QS_INJ_GRP_CFG(x) (0x24 + (x) * 4)
106	#define QS_INJ_GRP_CFG_MODE(x) ((x) << 2)
107	#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)
108
109	#define IFH_INJ_BYPASS BIT(31)
110	#define IFH_TAG_TYPE_C 0
111	#define MAC_VID 1
112	#define CPU_PORT 11
113	#define INTERNAL_PORT_MSK 0xFF
114	#define IFH_LEN 4
115	#define ETH_ALEN 6
116	#define PGID_BROADCAST 13
117	#define PGID_UNICAST 14
118
119	static const char *const regs_names[] = {
120	"port0", "port1", "port2", "port3", "port4", "port5", "port6",
121	"port7", "port8", "port9", "port10",
122	"ana", "qs", "qsys", "rew", "sys", "hsio",
123	};
124
125	#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
126	#define MAX_PORT 11
127
128	enum serval_ctrl_regs {
129	ANA = MAX_PORT,
130	QS,
131	QSYS,
132	REW,
133	SYS,
134	HSIO,
135	};
136
137	#define SERVAL_MIIM_BUS_COUNT 2
138
139	struct serval_phy_port_t {
140	size_t phy_addr;
141	struct mii_dev *bus;
142	u8 serdes_index;
143	u8 phy_mode;
144	};
145
146	struct serval_private {
147	void __iomem *regs[REGS_NAMES_COUNT];
148	struct mii_dev *bus[SERVAL_MIIM_BUS_COUNT];
149	struct serval_phy_port_t ports[MAX_PORT];
150	};
151
8cf94732 HV	152	static const unsigned long serval_regs_qs[] = {
	153	[MSCC_QS_XTR_RD] = 0x8,
	154	[MSCC_QS_XTR_FLUSH] = 0x18,
	155	[MSCC_QS_XTR_DATA_PRESENT] = 0x1c,
	156	[MSCC_QS_INJ_WR] = 0x2c,
	157	[MSCC_QS_INJ_CTRL] = 0x34,
	158	};
	159
	160	static const unsigned long serval_regs_ana_table[] = {
	161	[MSCC_ANA_TABLES_MACHDATA] = 0x9b34,
	162	[MSCC_ANA_TABLES_MACLDATA] = 0x9b38,
	163	[MSCC_ANA_TABLES_MACACCESS] = 0x9b3c,
	164	};
	165
	166	static struct mscc_miim_dev miim[SERVAL_MIIM_BUS_COUNT];
	167	static int miim_count = -1;
	168
8cf94732 HV	169	static void serval_cpu_capture_setup(struct serval_private *priv)
	170	{
	171	int i;
	172
	173	/* map the 8 CPU extraction queues to CPU port 11 */
	174	writel(0, priv->regs[QSYS] + QSYS_QMAP);
	175
	176	for (i = 0; i <= 1; i++) {
	177	/*
	178	* Do byte-swap and expect status after last data word
	179	* Extraction: Mode: manual extraction) \| Byte_swap
	180	*/
	181	writel(QS_XTR_GRP_CFG_MODE(1) \| QS_XTR_GRP_CFG_BYTE_SWAP,
	182	priv->regs[QS] + QS_XTR_GRP_CFG(i));
	183	/*
	184	* Injection: Mode: manual extraction \| Byte_swap
	185	*/
	186	writel(QS_INJ_GRP_CFG_MODE(1) \| QS_INJ_GRP_CFG_BYTE_SWAP,
	187	priv->regs[QS] + QS_INJ_GRP_CFG(i));
	188	}
	189
	190	for (i = 0; i <= 1; i++)
	191	/* Enable IFH insertion/parsing on CPU ports */
	192	writel(SYS_PORT_MODE_INCL_INJ_HDR(1) \|
	193	SYS_PORT_MODE_INCL_XTR_HDR(1),
	194	priv->regs[SYS] + SYS_PORT_MODE(CPU_PORT + i));
	195	/*
	196	* Setup the CPU port as VLAN aware to support switching frames
	197	* based on tags
	198	*/
	199	writel(ANA_PORT_VLAN_CFG_AWARE_ENA \| ANA_PORT_VLAN_CFG_POP_CNT(1) \|
	200	MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(CPU_PORT));
	201
	202	/* Disable learning (only RECV_ENA must be set) */
	203	writel(ANA_PORT_PORT_CFG_RECV_ENA,
	204	priv->regs[ANA] + ANA_PORT_PORT_CFG(CPU_PORT));
	205
	206	/* Enable switching to/from cpu port */
	207	setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(CPU_PORT),
	208	QSYS_SWITCH_PORT_MODE_PORT_ENA);
	209
	210	/* No pause on CPU port - not needed (off by default) */
	211	clrbits_le32(priv->regs[SYS] + SYS_PAUSE_CFG(CPU_PORT),
	212	SYS_PAUSE_CFG_PAUSE_ENA);
	213
	214	setbits_le32(priv->regs[QSYS] + QSYS_EGR_NO_SHARING, BIT(CPU_PORT));
	215	}
	216
	217	static void serval_port_init(struct serval_private *priv, int port)
	218	{
	219	void __iomem *regs = priv->regs[port];
	220
	221	/* Enable PCS */
	222	writel(PCS1G_MODE_CFG_SGMII_MODE_ENA, regs + PCS1G_CFG);
	223
	224	/* Disable Signal Detect */
	225	writel(0, regs + PCS1G_SD_CFG);
	226
	227	/* Enable MAC RX and TX */
	228	writel(DEV_MAC_ENA_CFG_RX_ENA \| DEV_MAC_ENA_CFG_TX_ENA,
	229	regs + DEV_MAC_ENA_CFG);
	230
	231	/* Clear sgmii_mode_ena */
	232	writel(0, regs + PCS1G_MODE_CFG);
233
234	/*
235	* Clear sw_resolve_ena(bit 0) and set adv_ability to
236	* something meaningful just in case
237	*/
238	writel(PCS1G_ANEG_CFG_ADV_ABILITY(0x20), regs + PCS1G_ANEG_CFG);
239
240	/* Set MAC IFG Gaps */
241	writel(DEV_MAC_IFG_CFG_TX_IFG(5) \| DEV_MAC_IFG_CFG_RX_IFG1(5) \|
242	DEV_MAC_IFG_CFG_RX_IFG2(1), regs + DEV_MAC_IFG_CFG);
243
244	/* Set link speed and release all resets */
245	writel(DEV_CLOCK_CFG_LINK_SPEED_1000, regs + DEV_CLOCK_CFG);
246
247	/* Make VLAN aware for CPU traffic */
248	writel(ANA_PORT_VLAN_CFG_AWARE_ENA \| ANA_PORT_VLAN_CFG_POP_CNT(1) \|
249	MAC_VID, priv->regs[ANA] + ANA_PORT_VLAN_CFG(port));
250
251	/* Enable the port in the core */
252	setbits_le32(priv->regs[QSYS] + QSYS_SWITCH_PORT_MODE(port),
253	QSYS_SWITCH_PORT_MODE_PORT_ENA);
254	}
255
256	static void serdes_write(void __iomem *base, u32 addr)
257	{
258	u32 data;
259
260	writel(HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT \|
261	HSIO_MCB_SERDES1G_CFG_ADDR(addr),
262	base + HSIO_MCB_SERDES1G_CFG);
263
264	do {
265	data = readl(base + HSIO_MCB_SERDES1G_CFG);
266	} while (data & HSIO_MCB_SERDES1G_CFG_WR_ONE_SHOT);
8cf94732 HV	267	}
	268
	269	static void serdes1g_setup(void __iomem *base, uint32_t addr,
	270	phy_interface_t interface)
	271	{
	272	writel(0x0, base + HSIO_ANA_SERDES1G_SER_CFG);
	273	writel(0x0, base + HSIO_DIG_SERDES1G_DFT_CFG0);
	274	writel(HSIO_ANA_SERDES1G_IB_CFG_RESISTOR_CTRL(11) \|
	275	HSIO_ANA_SERDES1G_IB_CFG_EQ_GAIN(0) \|
	276	HSIO_ANA_SERDES1G_IB_CFG_ENA_OFFSET_COMP \|
	277	HSIO_ANA_SERDES1G_IB_CFG_ENA_CMV_TERM \|
	278	HSIO_ANA_SERDES1G_IB_CFG_ACJTAG_HYST(1),
	279	base + HSIO_ANA_SERDES1G_IB_CFG);
	280	writel(HSIO_ANA_SERDES1G_DES_CFG_BW_HYST(7) \|
	281	HSIO_ANA_SERDES1G_DES_CFG_BW_ANA(6) \|
	282	HSIO_ANA_SERDES1G_DES_CFG_MBTR_CTRL(2) \|
	283	HSIO_ANA_SERDES1G_DES_CFG_PHS_CTRL(6),
	284	base + HSIO_ANA_SERDES1G_DES_CFG);
	285	writel(HSIO_ANA_SERDES1G_OB_CFG_RESISTOR_CTRL(1) \|
	286	HSIO_ANA_SERDES1G_OB_CFG_VCM_CTRL(4) \|
	287	HSIO_ANA_SERDES1G_OB_CFG_CMM_BIAS_CTRL(2) \|
	288	HSIO_ANA_SERDES1G_OB_CFG_AMP_CTRL(12) \|
	289	HSIO_ANA_SERDES1G_OB_CFG_SLP(3),
	290	base + HSIO_ANA_SERDES1G_OB_CFG);
	291	writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE \|
	292	HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE,
	293	base + HSIO_ANA_SERDES1G_COMMON_CFG);
	294	writel(HSIO_ANA_SERDES1G_PLL_CFG_FSM_ENA \|
	295	HSIO_ANA_SERDES1G_PLL_CFG_FSM_CTRL_DATA(200) \|
	296	HSIO_ANA_SERDES1G_PLL_CFG_ENA_RC_DIV2,
	297	base + HSIO_ANA_SERDES1G_PLL_CFG);
	298	writel(HSIO_DIG_SERDES1G_MISC_CFG_LANE_RST,
	299	base + HSIO_DIG_SERDES1G_MISC_CFG);
	300	serdes_write(base, addr);
	301
	302	writel(HSIO_ANA_SERDES1G_COMMON_CFG_IF_MODE \|
	303	HSIO_ANA_SERDES1G_COMMON_CFG_ENA_LANE \|
	304	HSIO_ANA_SERDES1G_COMMON_CFG_SYS_RST,
	305	base + HSIO_ANA_SERDES1G_COMMON_CFG);
	306	serdes_write(base, addr);
	307
	308	writel(0x0, base + HSIO_DIG_SERDES1G_MISC_CFG);
	309	serdes_write(base, addr);
	310	}
	311
	312	static void serdes_setup(struct serval_private *priv)
	313	{
	314	size_t mask;
	315	int i = 0;
	316
	317	for (i = 0; i < MAX_PORT; ++i) {
	318	if (!priv->ports[i].bus)
	319	continue;
	320
	321	mask = BIT(priv->ports[i].serdes_index);
	322	serdes1g_setup(priv->regs[HSIO], mask,
	323	priv->ports[i].phy_mode);
	324	}
	325	}
	326
	327	static int serval_switch_init(struct serval_private *priv)
	328	{
	329	/* Reset switch & memories */
	330	writel(SYS_SYSTEM_RST_MEM_ENA \| SYS_SYSTEM_RST_MEM_INIT,
331	priv->regs[SYS] + SYS_SYSTEM_RST_CFG);
332
333	if (wait_for_bit_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
334	SYS_SYSTEM_RST_MEM_INIT, false, 2000, false)) {
335	pr_err("Timeout in memory reset\n");
336	return -EIO;
337	}
338
339	/* Enable switch core */
340	setbits_le32(priv->regs[SYS] + SYS_SYSTEM_RST_CFG,
341	SYS_SYSTEM_RST_CORE_ENA);
342
343	serdes_setup(priv);
344
345	return 0;
346	}
347
348	static int serval_initialize(struct serval_private *priv)
349	{
350	int ret, i;
351
352	/* Initialize switch memories, enable core */
353	ret = serval_switch_init(priv);
354	if (ret)
355	return ret;
356
357	/* Flush queues */
358	mscc_flush(priv->regs[QS], serval_regs_qs);
359
360	/* Setup frame ageing - "2 sec" - The unit is 6.5us on serval */
361	writel(SYS_FRM_AGING_ENA \| (20000000 / 65),
362	priv->regs[SYS] + SYS_FRM_AGING);
363
364	for (i = 0; i < MAX_PORT; i++)
365	serval_port_init(priv, i);
366
367	serval_cpu_capture_setup(priv);
368
369	debug("Ports enabled\n");
370
371	return 0;
372	}
373
374	static int serval_write_hwaddr(struct udevice *dev)
375	{
376	struct serval_private *priv = dev_get_priv(dev);
c69cda25	377	struct eth_pdata *pdata = dev_get_plat(dev);
8cf94732 HV	378
	379	mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
	380	pdata->enetaddr, PGID_UNICAST);
	381
	382	writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
	383
	384	return 0;
	385	}
	386
	387	static int serval_start(struct udevice *dev)
	388	{
	389	struct serval_private *priv = dev_get_priv(dev);
c69cda25	390	struct eth_pdata *pdata = dev_get_plat(dev);
8cf94732 HV	391	const unsigned char mac[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff,
	392	0xff };
	393	int ret;
	394
	395	ret = serval_initialize(priv);
	396	if (ret)
	397	return ret;
	398
	399	/* Set MAC address tables entries for CPU redirection */
	400	mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table, mac,
	401	PGID_BROADCAST);
	402
	403	writel(BIT(CPU_PORT) \| INTERNAL_PORT_MSK,
	404	priv->regs[ANA] + ANA_PGID(PGID_BROADCAST));
	405
	406	/* It should be setup latter in serval_write_hwaddr */
	407	mscc_mac_table_add(priv->regs[ANA], serval_regs_ana_table,
	408	pdata->enetaddr, PGID_UNICAST);
	409
	410	writel(BIT(CPU_PORT), priv->regs[ANA] + ANA_PGID(PGID_UNICAST));
	411	return 0;
	412	}
	413
	414	static void serval_stop(struct udevice *dev)
	415	{
	416	writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
	417	writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
	418	}
	419
	420	static int serval_send(struct udevice dev, void packet, int length)
	421	{
	422	struct serval_private *priv = dev_get_priv(dev);
	423	u32 ifh[IFH_LEN];
	424	u32 *buf = packet;
	425
	426	/*
	427	* Generate the IFH for frame injection
	428	*
	429	* The IFH is a 128bit-value
	430	* bit 127: bypass the analyzer processing
	431	* bit 57-67: destination mask
	432	* bit 28-29: pop_cnt: 3 disables all rewriting of the frame
	433	* bit 20-27: cpu extraction queue mask
	434	* bit 16: tag type 0: C-tag, 1: S-tag
	435	* bit 0-11: VID
	436	*/
	437	ifh[0] = IFH_INJ_BYPASS;
	438	ifh[1] = (0x07);
	439	ifh[2] = (0x7f) << 25;
	440	ifh[3] = (IFH_TAG_TYPE_C << 16);
	441
	442	return mscc_send(priv->regs[QS], serval_regs_qs,
	443	ifh, IFH_LEN, buf, length);
	444	}
	445
	446	static int serval_recv(struct udevice dev, int flags, uchar *packetp)
	447	{
	448	struct serval_private *priv = dev_get_priv(dev);
	449	u32 rxbuf = (u32 )net_rx_packets[0];
	450	int byte_cnt = 0;
	451
	452	byte_cnt = mscc_recv(priv->regs[QS], serval_regs_qs, rxbuf, IFH_LEN,
	453	false);
	454
455	*packetp = net_rx_packets[0];
456
457	return byte_cnt;
458	}
459
460	static struct mii_dev *get_mdiobus(phys_addr_t base, unsigned long size)
461	{
462	int i = 0;
463
464	for (i = 0; i < SERVAL_MIIM_BUS_COUNT; ++i)
465	if (miim[i].miim_base == base && miim[i].miim_size == size)
466	return miim[i].bus;
467
468	return NULL;
469	}
470
471	static void add_port_entry(struct serval_private *priv, size_t index,
472	size_t phy_addr, struct mii_dev *bus,
473	u8 serdes_index, u8 phy_mode)
474	{
475	priv->ports[index].phy_addr = phy_addr;
476	priv->ports[index].bus = bus;
477	priv->ports[index].serdes_index = serdes_index;
478	priv->ports[index].phy_mode = phy_mode;
479	}
480
481	static int serval_probe(struct udevice *dev)
482	{
483	struct serval_private *priv = dev_get_priv(dev);
484	int i, ret;
485	struct resource res;
8cf94732 HV	486	phys_addr_t addr_base;
	487	unsigned long addr_size;
	488	ofnode eth_node, node, mdio_node;
	489	size_t phy_addr;
	490	struct mii_dev *bus;
	491	struct ofnode_phandle_args phandle;
	492	struct phy_device *phy;
	493
	494	if (!priv)
	495	return -EINVAL;
	496
	497	/* Get registers and map them to the private structure */
	498	for (i = 0; i < ARRAY_SIZE(regs_names); i++) {
	499	priv->regs[i] = dev_remap_addr_name(dev, regs_names[i]);
	500	if (!priv->regs[i]) {
	501	debug
	502	("Error can't get regs base addresses for %s\n",
	503	regs_names[i]);
	504	return -ENOMEM;
	505	}
	506	}
	507
	508	/* Initialize miim buses */
	509	memset(&miim, 0x0, sizeof(miim) * SERVAL_MIIM_BUS_COUNT);
	510
	511	/* iterate all the ports and find out on which bus they are */
	512	i = 0;
	513	eth_node = dev_read_first_subnode(dev);
	514	for (node = ofnode_first_subnode(eth_node);
	515	ofnode_valid(node);
	516	node = ofnode_next_subnode(node)) {
	517	if (ofnode_read_resource(node, 0, &res))
	518	return -ENOMEM;
	519	i = res.start;
	520
	521	ret = ofnode_parse_phandle_with_args(node, "phy-handle", NULL,
	522	0, 0, &phandle);
	523	if (ret)
	524	continue;
	525
	526	/* Get phy address on mdio bus */
	527	if (ofnode_read_resource(phandle.node, 0, &res))
	528	return -ENOMEM;
	529	phy_addr = res.start;
	530
	531	/* Get mdio node */
	532	mdio_node = ofnode_get_parent(phandle.node);
	533
	534	if (ofnode_read_resource(mdio_node, 0, &res))
	535	return -ENOMEM;
8cf94732	536
feb7ac45	537	addr_base = res.start;
8cf94732 HV	538	addr_size = res.end - res.start;
	539
	540	/* If the bus is new then create a new bus */
	541	if (!get_mdiobus(addr_base, addr_size))
	542	priv->bus[miim_count] =
61243678 HV	543	mscc_mdiobus_init(miim, &miim_count, addr_base,
61243678 HV	544	addr_size);
8cf94732 HV	545
	546	/* Connect mdio bus with the port */
	547	bus = get_mdiobus(addr_base, addr_size);
	548
	549	/* Get serdes info */
	550	ret = ofnode_parse_phandle_with_args(node, "phys", NULL,
	551	3, 0, &phandle);
	552	if (ret)
	553	return -ENOMEM;
	554
	555	add_port_entry(priv, i, phy_addr, bus, phandle.args[1],
	556	phandle.args[2]);
	557	}
	558
	559	for (i = 0; i < MAX_PORT; i++) {
	560	if (!priv->ports[i].bus)
	561	continue;
	562
	563	phy = phy_connect(priv->ports[i].bus,
	564	priv->ports[i].phy_addr, dev,
ffb0f6f4	565	PHY_INTERFACE_MODE_NA);
8cf94732 HV	566	if (phy)
	567	board_phy_config(phy);
	568	}
	569
	570	return 0;
	571	}
	572
	573	static int serval_remove(struct udevice *dev)
	574	{
	575	struct serval_private *priv = dev_get_priv(dev);
	576	int i;
	577
	578	for (i = 0; i < SERVAL_MIIM_BUS_COUNT; i++) {
	579	mdio_unregister(priv->bus[i]);
	580	mdio_free(priv->bus[i]);
	581	}
	582
	583	return 0;
	584	}
	585
	586	static const struct eth_ops serval_ops = {
	587	.start = serval_start,
	588	.stop = serval_stop,
	589	.send = serval_send,
	590	.recv = serval_recv,
	591	.write_hwaddr = serval_write_hwaddr,
	592	};
	593
	594	static const struct udevice_id mscc_serval_ids[] = {
	595	{.compatible = "mscc,vsc7418-switch"},
	596	{ /* Sentinel */ }
	597	};
	598
	599	U_BOOT_DRIVER(serval) = {
	600	.name = "serval-switch",
	601	.id = UCLASS_ETH,
	602	.of_match = mscc_serval_ids,
	603	.probe = serval_probe,
	604	.remove = serval_remove,
	605	.ops = &serval_ops,
41575d8e	606	.priv_auto = sizeof(struct serval_private),
caa4daa2	607	.plat_auto = sizeof(struct eth_pdata),
8cf94732	608	};