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19fc2eae SR |
1 | /* |
2 | * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. | |
3 | * | |
4 | * U-Boot version: | |
e3b9c98a | 5 | * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> |
19fc2eae SR |
6 | * |
7 | * Based on the Linux version which is: | |
8 | * Copyright (C) 2012 Marvell | |
9 | * | |
10 | * Rami Rosen <rosenr@marvell.com> | |
11 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
12 | * | |
13 | * SPDX-License-Identifier: GPL-2.0 | |
14 | */ | |
15 | ||
16 | #include <common.h> | |
e3b9c98a | 17 | #include <dm.h> |
19fc2eae SR |
18 | #include <net.h> |
19 | #include <netdev.h> | |
20 | #include <config.h> | |
21 | #include <malloc.h> | |
22 | #include <asm/io.h> | |
1221ce45 | 23 | #include <linux/errno.h> |
19fc2eae SR |
24 | #include <phy.h> |
25 | #include <miiphy.h> | |
26 | #include <watchdog.h> | |
27 | #include <asm/arch/cpu.h> | |
28 | #include <asm/arch/soc.h> | |
29 | #include <linux/compat.h> | |
30 | #include <linux/mbus.h> | |
31 | ||
e3b9c98a SR |
32 | DECLARE_GLOBAL_DATA_PTR; |
33 | ||
19fc2eae SR |
34 | #if !defined(CONFIG_PHYLIB) |
35 | # error Marvell mvneta requires PHYLIB | |
36 | #endif | |
37 | ||
38 | /* Some linux -> U-Boot compatibility stuff */ | |
39 | #define netdev_err(dev, fmt, args...) \ | |
40 | printf(fmt, ##args) | |
41 | #define netdev_warn(dev, fmt, args...) \ | |
42 | printf(fmt, ##args) | |
43 | #define netdev_info(dev, fmt, args...) \ | |
44 | printf(fmt, ##args) | |
45 | ||
46 | #define CONFIG_NR_CPUS 1 | |
19fc2eae SR |
47 | #define ETH_HLEN 14 /* Total octets in header */ |
48 | ||
49 | /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */ | |
50 | #define WRAP (2 + ETH_HLEN + 4 + 32) | |
51 | #define MTU 1500 | |
52 | #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN)) | |
53 | ||
54 | #define MVNETA_SMI_TIMEOUT 10000 | |
55 | ||
56 | /* Registers */ | |
57 | #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) | |
58 | #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) | |
59 | #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) | |
60 | #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) | |
61 | #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) | |
62 | #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) | |
63 | #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) | |
64 | #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) | |
65 | #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 | |
66 | #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) | |
67 | #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) | |
68 | #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff | |
69 | #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) | |
70 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 | |
71 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 | |
72 | #define MVNETA_PORT_RX_RESET 0x1cc0 | |
73 | #define MVNETA_PORT_RX_DMA_RESET BIT(0) | |
74 | #define MVNETA_PHY_ADDR 0x2000 | |
75 | #define MVNETA_PHY_ADDR_MASK 0x1f | |
76 | #define MVNETA_SMI 0x2004 | |
77 | #define MVNETA_PHY_REG_MASK 0x1f | |
78 | /* SMI register fields */ | |
79 | #define MVNETA_SMI_DATA_OFFS 0 /* Data */ | |
80 | #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS) | |
81 | #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ | |
82 | #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/ | |
83 | #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ | |
84 | #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS) | |
85 | #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */ | |
86 | #define MVNETA_SMI_BUSY (1 << 28) /* Busy */ | |
87 | #define MVNETA_MBUS_RETRY 0x2010 | |
88 | #define MVNETA_UNIT_INTR_CAUSE 0x2080 | |
89 | #define MVNETA_UNIT_CONTROL 0x20B0 | |
90 | #define MVNETA_PHY_POLLING_ENABLE BIT(1) | |
91 | #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) | |
92 | #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) | |
93 | #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) | |
94 | #define MVNETA_BASE_ADDR_ENABLE 0x2290 | |
95 | #define MVNETA_PORT_CONFIG 0x2400 | |
96 | #define MVNETA_UNI_PROMISC_MODE BIT(0) | |
97 | #define MVNETA_DEF_RXQ(q) ((q) << 1) | |
98 | #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) | |
99 | #define MVNETA_TX_UNSET_ERR_SUM BIT(12) | |
100 | #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) | |
101 | #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) | |
102 | #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) | |
103 | #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) | |
104 | #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ | |
105 | MVNETA_DEF_RXQ_ARP(q) | \ | |
106 | MVNETA_DEF_RXQ_TCP(q) | \ | |
107 | MVNETA_DEF_RXQ_UDP(q) | \ | |
108 | MVNETA_DEF_RXQ_BPDU(q) | \ | |
109 | MVNETA_TX_UNSET_ERR_SUM | \ | |
110 | MVNETA_RX_CSUM_WITH_PSEUDO_HDR) | |
111 | #define MVNETA_PORT_CONFIG_EXTEND 0x2404 | |
112 | #define MVNETA_MAC_ADDR_LOW 0x2414 | |
113 | #define MVNETA_MAC_ADDR_HIGH 0x2418 | |
114 | #define MVNETA_SDMA_CONFIG 0x241c | |
115 | #define MVNETA_SDMA_BRST_SIZE_16 4 | |
116 | #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) | |
117 | #define MVNETA_RX_NO_DATA_SWAP BIT(4) | |
118 | #define MVNETA_TX_NO_DATA_SWAP BIT(5) | |
119 | #define MVNETA_DESC_SWAP BIT(6) | |
120 | #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) | |
121 | #define MVNETA_PORT_STATUS 0x2444 | |
122 | #define MVNETA_TX_IN_PRGRS BIT(1) | |
123 | #define MVNETA_TX_FIFO_EMPTY BIT(8) | |
124 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c | |
125 | #define MVNETA_SERDES_CFG 0x24A0 | |
126 | #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 | |
127 | #define MVNETA_QSGMII_SERDES_PROTO 0x0667 | |
128 | #define MVNETA_TYPE_PRIO 0x24bc | |
129 | #define MVNETA_FORCE_UNI BIT(21) | |
130 | #define MVNETA_TXQ_CMD_1 0x24e4 | |
131 | #define MVNETA_TXQ_CMD 0x2448 | |
132 | #define MVNETA_TXQ_DISABLE_SHIFT 8 | |
133 | #define MVNETA_TXQ_ENABLE_MASK 0x000000ff | |
134 | #define MVNETA_ACC_MODE 0x2500 | |
135 | #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) | |
136 | #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff | |
137 | #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 | |
138 | #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) | |
139 | ||
140 | /* Exception Interrupt Port/Queue Cause register */ | |
141 | ||
142 | #define MVNETA_INTR_NEW_CAUSE 0x25a0 | |
143 | #define MVNETA_INTR_NEW_MASK 0x25a4 | |
144 | ||
145 | /* bits 0..7 = TXQ SENT, one bit per queue. | |
146 | * bits 8..15 = RXQ OCCUP, one bit per queue. | |
147 | * bits 16..23 = RXQ FREE, one bit per queue. | |
148 | * bit 29 = OLD_REG_SUM, see old reg ? | |
149 | * bit 30 = TX_ERR_SUM, one bit for 4 ports | |
150 | * bit 31 = MISC_SUM, one bit for 4 ports | |
151 | */ | |
152 | #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) | |
153 | #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) | |
154 | #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) | |
155 | #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) | |
156 | ||
157 | #define MVNETA_INTR_OLD_CAUSE 0x25a8 | |
158 | #define MVNETA_INTR_OLD_MASK 0x25ac | |
159 | ||
160 | /* Data Path Port/Queue Cause Register */ | |
161 | #define MVNETA_INTR_MISC_CAUSE 0x25b0 | |
162 | #define MVNETA_INTR_MISC_MASK 0x25b4 | |
163 | #define MVNETA_INTR_ENABLE 0x25b8 | |
164 | ||
165 | #define MVNETA_RXQ_CMD 0x2680 | |
166 | #define MVNETA_RXQ_DISABLE_SHIFT 8 | |
167 | #define MVNETA_RXQ_ENABLE_MASK 0x000000ff | |
168 | #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) | |
169 | #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) | |
170 | #define MVNETA_GMAC_CTRL_0 0x2c00 | |
171 | #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 | |
172 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
173 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) | |
174 | #define MVNETA_GMAC_CTRL_2 0x2c08 | |
175 | #define MVNETA_GMAC2_PCS_ENABLE BIT(3) | |
176 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) | |
177 | #define MVNETA_GMAC2_PORT_RESET BIT(6) | |
178 | #define MVNETA_GMAC_STATUS 0x2c10 | |
179 | #define MVNETA_GMAC_LINK_UP BIT(0) | |
180 | #define MVNETA_GMAC_SPEED_1000 BIT(1) | |
181 | #define MVNETA_GMAC_SPEED_100 BIT(2) | |
182 | #define MVNETA_GMAC_FULL_DUPLEX BIT(3) | |
183 | #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) | |
184 | #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) | |
185 | #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) | |
186 | #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) | |
187 | #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c | |
188 | #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) | |
189 | #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) | |
190 | #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) | |
191 | #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) | |
192 | #define MVNETA_GMAC_AN_SPEED_EN BIT(7) | |
193 | #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) | |
194 | #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) | |
195 | #define MVNETA_MIB_COUNTERS_BASE 0x3080 | |
196 | #define MVNETA_MIB_LATE_COLLISION 0x7c | |
197 | #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 | |
198 | #define MVNETA_DA_FILT_OTH_MCAST 0x3500 | |
199 | #define MVNETA_DA_FILT_UCAST_BASE 0x3600 | |
200 | #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) | |
201 | #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) | |
202 | #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 | |
203 | #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) | |
204 | #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) | |
205 | #define MVNETA_TXQ_DEC_SENT_SHIFT 16 | |
206 | #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) | |
207 | #define MVNETA_TXQ_SENT_DESC_SHIFT 16 | |
208 | #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 | |
209 | #define MVNETA_PORT_TX_RESET 0x3cf0 | |
210 | #define MVNETA_PORT_TX_DMA_RESET BIT(0) | |
211 | #define MVNETA_TX_MTU 0x3e0c | |
212 | #define MVNETA_TX_TOKEN_SIZE 0x3e14 | |
213 | #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff | |
214 | #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) | |
215 | #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
216 | ||
217 | /* Descriptor ring Macros */ | |
218 | #define MVNETA_QUEUE_NEXT_DESC(q, index) \ | |
219 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
220 | ||
221 | /* Various constants */ | |
222 | ||
223 | /* Coalescing */ | |
224 | #define MVNETA_TXDONE_COAL_PKTS 16 | |
225 | #define MVNETA_RX_COAL_PKTS 32 | |
226 | #define MVNETA_RX_COAL_USEC 100 | |
227 | ||
228 | /* The two bytes Marvell header. Either contains a special value used | |
229 | * by Marvell switches when a specific hardware mode is enabled (not | |
230 | * supported by this driver) or is filled automatically by zeroes on | |
231 | * the RX side. Those two bytes being at the front of the Ethernet | |
232 | * header, they allow to have the IP header aligned on a 4 bytes | |
233 | * boundary automatically: the hardware skips those two bytes on its | |
234 | * own. | |
235 | */ | |
236 | #define MVNETA_MH_SIZE 2 | |
237 | ||
238 | #define MVNETA_VLAN_TAG_LEN 4 | |
239 | ||
240 | #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 | |
241 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 | |
242 | #define MVNETA_ACC_MODE_EXT 1 | |
243 | ||
244 | /* Timeout constants */ | |
245 | #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 | |
246 | #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 | |
247 | #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 | |
248 | ||
249 | #define MVNETA_TX_MTU_MAX 0x3ffff | |
250 | ||
251 | /* Max number of Rx descriptors */ | |
252 | #define MVNETA_MAX_RXD 16 | |
253 | ||
254 | /* Max number of Tx descriptors */ | |
255 | #define MVNETA_MAX_TXD 16 | |
256 | ||
257 | /* descriptor aligned size */ | |
258 | #define MVNETA_DESC_ALIGNED_SIZE 32 | |
259 | ||
260 | struct mvneta_port { | |
261 | void __iomem *base; | |
262 | struct mvneta_rx_queue *rxqs; | |
263 | struct mvneta_tx_queue *txqs; | |
264 | ||
265 | u8 mcast_count[256]; | |
266 | u16 tx_ring_size; | |
267 | u16 rx_ring_size; | |
268 | ||
269 | phy_interface_t phy_interface; | |
270 | unsigned int link; | |
271 | unsigned int duplex; | |
272 | unsigned int speed; | |
273 | ||
274 | int init; | |
275 | int phyaddr; | |
276 | struct phy_device *phydev; | |
277 | struct mii_dev *bus; | |
278 | }; | |
279 | ||
280 | /* The mvneta_tx_desc and mvneta_rx_desc structures describe the | |
281 | * layout of the transmit and reception DMA descriptors, and their | |
282 | * layout is therefore defined by the hardware design | |
283 | */ | |
284 | ||
285 | #define MVNETA_TX_L3_OFF_SHIFT 0 | |
286 | #define MVNETA_TX_IP_HLEN_SHIFT 8 | |
287 | #define MVNETA_TX_L4_UDP BIT(16) | |
288 | #define MVNETA_TX_L3_IP6 BIT(17) | |
289 | #define MVNETA_TXD_IP_CSUM BIT(18) | |
290 | #define MVNETA_TXD_Z_PAD BIT(19) | |
291 | #define MVNETA_TXD_L_DESC BIT(20) | |
292 | #define MVNETA_TXD_F_DESC BIT(21) | |
293 | #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ | |
294 | MVNETA_TXD_L_DESC | \ | |
295 | MVNETA_TXD_F_DESC) | |
296 | #define MVNETA_TX_L4_CSUM_FULL BIT(30) | |
297 | #define MVNETA_TX_L4_CSUM_NOT BIT(31) | |
298 | ||
299 | #define MVNETA_RXD_ERR_CRC 0x0 | |
300 | #define MVNETA_RXD_ERR_SUMMARY BIT(16) | |
301 | #define MVNETA_RXD_ERR_OVERRUN BIT(17) | |
302 | #define MVNETA_RXD_ERR_LEN BIT(18) | |
303 | #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) | |
304 | #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) | |
305 | #define MVNETA_RXD_L3_IP4 BIT(25) | |
306 | #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) | |
307 | #define MVNETA_RXD_L4_CSUM_OK BIT(30) | |
308 | ||
309 | struct mvneta_tx_desc { | |
310 | u32 command; /* Options used by HW for packet transmitting.*/ | |
311 | u16 reserverd1; /* csum_l4 (for future use) */ | |
312 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
313 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
314 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
315 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
316 | }; | |
317 | ||
318 | struct mvneta_rx_desc { | |
319 | u32 status; /* Info about received packet */ | |
320 | u16 reserved1; /* pnc_info - (for future use, PnC) */ | |
321 | u16 data_size; /* Size of received packet in bytes */ | |
322 | ||
323 | u32 buf_phys_addr; /* Physical address of the buffer */ | |
324 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
325 | ||
326 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ | |
327 | u16 reserved3; /* prefetch_cmd, for future use */ | |
328 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
329 | ||
330 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ | |
331 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
332 | }; | |
333 | ||
334 | struct mvneta_tx_queue { | |
335 | /* Number of this TX queue, in the range 0-7 */ | |
336 | u8 id; | |
337 | ||
338 | /* Number of TX DMA descriptors in the descriptor ring */ | |
339 | int size; | |
340 | ||
341 | /* Index of last TX DMA descriptor that was inserted */ | |
342 | int txq_put_index; | |
343 | ||
344 | /* Index of the TX DMA descriptor to be cleaned up */ | |
345 | int txq_get_index; | |
346 | ||
347 | /* Virtual address of the TX DMA descriptors array */ | |
348 | struct mvneta_tx_desc *descs; | |
349 | ||
350 | /* DMA address of the TX DMA descriptors array */ | |
351 | dma_addr_t descs_phys; | |
352 | ||
353 | /* Index of the last TX DMA descriptor */ | |
354 | int last_desc; | |
355 | ||
356 | /* Index of the next TX DMA descriptor to process */ | |
357 | int next_desc_to_proc; | |
358 | }; | |
359 | ||
360 | struct mvneta_rx_queue { | |
361 | /* rx queue number, in the range 0-7 */ | |
362 | u8 id; | |
363 | ||
364 | /* num of rx descriptors in the rx descriptor ring */ | |
365 | int size; | |
366 | ||
367 | /* Virtual address of the RX DMA descriptors array */ | |
368 | struct mvneta_rx_desc *descs; | |
369 | ||
370 | /* DMA address of the RX DMA descriptors array */ | |
371 | dma_addr_t descs_phys; | |
372 | ||
373 | /* Index of the last RX DMA descriptor */ | |
374 | int last_desc; | |
375 | ||
376 | /* Index of the next RX DMA descriptor to process */ | |
377 | int next_desc_to_proc; | |
378 | }; | |
379 | ||
380 | /* U-Boot doesn't use the queues, so set the number to 1 */ | |
381 | static int rxq_number = 1; | |
382 | static int txq_number = 1; | |
383 | static int rxq_def; | |
384 | ||
385 | struct buffer_location { | |
386 | struct mvneta_tx_desc *tx_descs; | |
387 | struct mvneta_rx_desc *rx_descs; | |
388 | u32 rx_buffers; | |
389 | }; | |
390 | ||
391 | /* | |
392 | * All 4 interfaces use the same global buffer, since only one interface | |
393 | * can be enabled at once | |
394 | */ | |
395 | static struct buffer_location buffer_loc; | |
396 | ||
397 | /* | |
398 | * Page table entries are set to 1MB, or multiples of 1MB | |
399 | * (not < 1MB). driver uses less bd's so use 1MB bdspace. | |
400 | */ | |
401 | #define BD_SPACE (1 << 20) | |
402 | ||
403 | /* Utility/helper methods */ | |
404 | ||
405 | /* Write helper method */ | |
406 | static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) | |
407 | { | |
408 | writel(data, pp->base + offset); | |
409 | } | |
410 | ||
411 | /* Read helper method */ | |
412 | static u32 mvreg_read(struct mvneta_port *pp, u32 offset) | |
413 | { | |
414 | return readl(pp->base + offset); | |
415 | } | |
416 | ||
417 | /* Clear all MIB counters */ | |
418 | static void mvneta_mib_counters_clear(struct mvneta_port *pp) | |
419 | { | |
420 | int i; | |
421 | ||
422 | /* Perform dummy reads from MIB counters */ | |
423 | for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) | |
424 | mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); | |
425 | } | |
426 | ||
427 | /* Rx descriptors helper methods */ | |
428 | ||
429 | /* Checks whether the RX descriptor having this status is both the first | |
430 | * and the last descriptor for the RX packet. Each RX packet is currently | |
431 | * received through a single RX descriptor, so not having each RX | |
432 | * descriptor with its first and last bits set is an error | |
433 | */ | |
434 | static int mvneta_rxq_desc_is_first_last(u32 status) | |
435 | { | |
436 | return (status & MVNETA_RXD_FIRST_LAST_DESC) == | |
437 | MVNETA_RXD_FIRST_LAST_DESC; | |
438 | } | |
439 | ||
440 | /* Add number of descriptors ready to receive new packets */ | |
441 | static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, | |
442 | struct mvneta_rx_queue *rxq, | |
443 | int ndescs) | |
444 | { | |
445 | /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can | |
446 | * be added at once | |
447 | */ | |
448 | while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { | |
449 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
450 | (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << | |
451 | MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
452 | ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; | |
453 | } | |
454 | ||
455 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
456 | (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
457 | } | |
458 | ||
459 | /* Get number of RX descriptors occupied by received packets */ | |
460 | static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, | |
461 | struct mvneta_rx_queue *rxq) | |
462 | { | |
463 | u32 val; | |
464 | ||
465 | val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); | |
466 | return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; | |
467 | } | |
468 | ||
469 | /* Update num of rx desc called upon return from rx path or | |
470 | * from mvneta_rxq_drop_pkts(). | |
471 | */ | |
472 | static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, | |
473 | struct mvneta_rx_queue *rxq, | |
474 | int rx_done, int rx_filled) | |
475 | { | |
476 | u32 val; | |
477 | ||
478 | if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { | |
479 | val = rx_done | | |
480 | (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); | |
481 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
482 | return; | |
483 | } | |
484 | ||
485 | /* Only 255 descriptors can be added at once */ | |
486 | while ((rx_done > 0) || (rx_filled > 0)) { | |
487 | if (rx_done <= 0xff) { | |
488 | val = rx_done; | |
489 | rx_done = 0; | |
490 | } else { | |
491 | val = 0xff; | |
492 | rx_done -= 0xff; | |
493 | } | |
494 | if (rx_filled <= 0xff) { | |
495 | val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
496 | rx_filled = 0; | |
497 | } else { | |
498 | val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
499 | rx_filled -= 0xff; | |
500 | } | |
501 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
502 | } | |
503 | } | |
504 | ||
505 | /* Get pointer to next RX descriptor to be processed by SW */ | |
506 | static struct mvneta_rx_desc * | |
507 | mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) | |
508 | { | |
509 | int rx_desc = rxq->next_desc_to_proc; | |
510 | ||
511 | rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); | |
512 | return rxq->descs + rx_desc; | |
513 | } | |
514 | ||
515 | /* Tx descriptors helper methods */ | |
516 | ||
517 | /* Update HW with number of TX descriptors to be sent */ | |
518 | static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, | |
519 | struct mvneta_tx_queue *txq, | |
520 | int pend_desc) | |
521 | { | |
522 | u32 val; | |
523 | ||
524 | /* Only 255 descriptors can be added at once ; Assume caller | |
525 | * process TX desriptors in quanta less than 256 | |
526 | */ | |
527 | val = pend_desc; | |
528 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
529 | } | |
530 | ||
531 | /* Get pointer to next TX descriptor to be processed (send) by HW */ | |
532 | static struct mvneta_tx_desc * | |
533 | mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) | |
534 | { | |
535 | int tx_desc = txq->next_desc_to_proc; | |
536 | ||
537 | txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); | |
538 | return txq->descs + tx_desc; | |
539 | } | |
540 | ||
541 | /* Set rxq buf size */ | |
542 | static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, | |
543 | struct mvneta_rx_queue *rxq, | |
544 | int buf_size) | |
545 | { | |
546 | u32 val; | |
547 | ||
548 | val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); | |
549 | ||
550 | val &= ~MVNETA_RXQ_BUF_SIZE_MASK; | |
551 | val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); | |
552 | ||
553 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); | |
554 | } | |
555 | ||
556 | /* Start the Ethernet port RX and TX activity */ | |
557 | static void mvneta_port_up(struct mvneta_port *pp) | |
558 | { | |
559 | int queue; | |
560 | u32 q_map; | |
561 | ||
562 | /* Enable all initialized TXs. */ | |
563 | mvneta_mib_counters_clear(pp); | |
564 | q_map = 0; | |
565 | for (queue = 0; queue < txq_number; queue++) { | |
566 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
567 | if (txq->descs != NULL) | |
568 | q_map |= (1 << queue); | |
569 | } | |
570 | mvreg_write(pp, MVNETA_TXQ_CMD, q_map); | |
571 | ||
572 | /* Enable all initialized RXQs. */ | |
573 | q_map = 0; | |
574 | for (queue = 0; queue < rxq_number; queue++) { | |
575 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
576 | if (rxq->descs != NULL) | |
577 | q_map |= (1 << queue); | |
578 | } | |
579 | mvreg_write(pp, MVNETA_RXQ_CMD, q_map); | |
580 | } | |
581 | ||
582 | /* Stop the Ethernet port activity */ | |
583 | static void mvneta_port_down(struct mvneta_port *pp) | |
584 | { | |
585 | u32 val; | |
586 | int count; | |
587 | ||
588 | /* Stop Rx port activity. Check port Rx activity. */ | |
589 | val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; | |
590 | ||
591 | /* Issue stop command for active channels only */ | |
592 | if (val != 0) | |
593 | mvreg_write(pp, MVNETA_RXQ_CMD, | |
594 | val << MVNETA_RXQ_DISABLE_SHIFT); | |
595 | ||
596 | /* Wait for all Rx activity to terminate. */ | |
597 | count = 0; | |
598 | do { | |
599 | if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { | |
600 | netdev_warn(pp->dev, | |
601 | "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", | |
602 | val); | |
603 | break; | |
604 | } | |
605 | mdelay(1); | |
606 | ||
607 | val = mvreg_read(pp, MVNETA_RXQ_CMD); | |
608 | } while (val & 0xff); | |
609 | ||
610 | /* Stop Tx port activity. Check port Tx activity. Issue stop | |
611 | * command for active channels only | |
612 | */ | |
613 | val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; | |
614 | ||
615 | if (val != 0) | |
616 | mvreg_write(pp, MVNETA_TXQ_CMD, | |
617 | (val << MVNETA_TXQ_DISABLE_SHIFT)); | |
618 | ||
619 | /* Wait for all Tx activity to terminate. */ | |
620 | count = 0; | |
621 | do { | |
622 | if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { | |
623 | netdev_warn(pp->dev, | |
624 | "TIMEOUT for TX stopped status=0x%08x\n", | |
625 | val); | |
626 | break; | |
627 | } | |
628 | mdelay(1); | |
629 | ||
630 | /* Check TX Command reg that all Txqs are stopped */ | |
631 | val = mvreg_read(pp, MVNETA_TXQ_CMD); | |
632 | ||
633 | } while (val & 0xff); | |
634 | ||
635 | /* Double check to verify that TX FIFO is empty */ | |
636 | count = 0; | |
637 | do { | |
638 | if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { | |
639 | netdev_warn(pp->dev, | |
640 | "TX FIFO empty timeout status=0x08%x\n", | |
641 | val); | |
642 | break; | |
643 | } | |
644 | mdelay(1); | |
645 | ||
646 | val = mvreg_read(pp, MVNETA_PORT_STATUS); | |
647 | } while (!(val & MVNETA_TX_FIFO_EMPTY) && | |
648 | (val & MVNETA_TX_IN_PRGRS)); | |
649 | ||
650 | udelay(200); | |
651 | } | |
652 | ||
653 | /* Enable the port by setting the port enable bit of the MAC control register */ | |
654 | static void mvneta_port_enable(struct mvneta_port *pp) | |
655 | { | |
656 | u32 val; | |
657 | ||
658 | /* Enable port */ | |
659 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
660 | val |= MVNETA_GMAC0_PORT_ENABLE; | |
661 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
662 | } | |
663 | ||
664 | /* Disable the port and wait for about 200 usec before retuning */ | |
665 | static void mvneta_port_disable(struct mvneta_port *pp) | |
666 | { | |
667 | u32 val; | |
668 | ||
669 | /* Reset the Enable bit in the Serial Control Register */ | |
670 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
671 | val &= ~MVNETA_GMAC0_PORT_ENABLE; | |
672 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
673 | ||
674 | udelay(200); | |
675 | } | |
676 | ||
677 | /* Multicast tables methods */ | |
678 | ||
679 | /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ | |
680 | static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) | |
681 | { | |
682 | int offset; | |
683 | u32 val; | |
684 | ||
685 | if (queue == -1) { | |
686 | val = 0; | |
687 | } else { | |
688 | val = 0x1 | (queue << 1); | |
689 | val |= (val << 24) | (val << 16) | (val << 8); | |
690 | } | |
691 | ||
692 | for (offset = 0; offset <= 0xc; offset += 4) | |
693 | mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); | |
694 | } | |
695 | ||
696 | /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ | |
697 | static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) | |
698 | { | |
699 | int offset; | |
700 | u32 val; | |
701 | ||
702 | if (queue == -1) { | |
703 | val = 0; | |
704 | } else { | |
705 | val = 0x1 | (queue << 1); | |
706 | val |= (val << 24) | (val << 16) | (val << 8); | |
707 | } | |
708 | ||
709 | for (offset = 0; offset <= 0xfc; offset += 4) | |
710 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); | |
711 | } | |
712 | ||
713 | /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ | |
714 | static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) | |
715 | { | |
716 | int offset; | |
717 | u32 val; | |
718 | ||
719 | if (queue == -1) { | |
720 | memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); | |
721 | val = 0; | |
722 | } else { | |
723 | memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); | |
724 | val = 0x1 | (queue << 1); | |
725 | val |= (val << 24) | (val << 16) | (val << 8); | |
726 | } | |
727 | ||
728 | for (offset = 0; offset <= 0xfc; offset += 4) | |
729 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); | |
730 | } | |
731 | ||
732 | /* This method sets defaults to the NETA port: | |
733 | * Clears interrupt Cause and Mask registers. | |
734 | * Clears all MAC tables. | |
735 | * Sets defaults to all registers. | |
736 | * Resets RX and TX descriptor rings. | |
737 | * Resets PHY. | |
738 | * This method can be called after mvneta_port_down() to return the port | |
739 | * settings to defaults. | |
740 | */ | |
741 | static void mvneta_defaults_set(struct mvneta_port *pp) | |
742 | { | |
743 | int cpu; | |
744 | int queue; | |
745 | u32 val; | |
746 | ||
747 | /* Clear all Cause registers */ | |
748 | mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); | |
749 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); | |
750 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
751 | ||
752 | /* Mask all interrupts */ | |
753 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
754 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
755 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
756 | mvreg_write(pp, MVNETA_INTR_ENABLE, 0); | |
757 | ||
758 | /* Enable MBUS Retry bit16 */ | |
759 | mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); | |
760 | ||
761 | /* Set CPU queue access map - all CPUs have access to all RX | |
762 | * queues and to all TX queues | |
763 | */ | |
764 | for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) | |
765 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), | |
766 | (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | | |
767 | MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); | |
768 | ||
769 | /* Reset RX and TX DMAs */ | |
770 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
771 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
772 | ||
773 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
774 | mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); | |
775 | for (queue = 0; queue < txq_number; queue++) { | |
776 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); | |
777 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); | |
778 | } | |
779 | ||
780 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
781 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
782 | ||
783 | /* Set Port Acceleration Mode */ | |
784 | val = MVNETA_ACC_MODE_EXT; | |
785 | mvreg_write(pp, MVNETA_ACC_MODE, val); | |
786 | ||
787 | /* Update val of portCfg register accordingly with all RxQueue types */ | |
788 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); | |
789 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); | |
790 | ||
791 | val = 0; | |
792 | mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); | |
793 | mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); | |
794 | ||
795 | /* Build PORT_SDMA_CONFIG_REG */ | |
796 | val = 0; | |
797 | ||
798 | /* Default burst size */ | |
799 | val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
800 | val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
801 | val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; | |
802 | ||
803 | /* Assign port SDMA configuration */ | |
804 | mvreg_write(pp, MVNETA_SDMA_CONFIG, val); | |
805 | ||
806 | /* Enable PHY polling in hardware for U-Boot */ | |
807 | val = mvreg_read(pp, MVNETA_UNIT_CONTROL); | |
808 | val |= MVNETA_PHY_POLLING_ENABLE; | |
809 | mvreg_write(pp, MVNETA_UNIT_CONTROL, val); | |
810 | ||
811 | mvneta_set_ucast_table(pp, -1); | |
812 | mvneta_set_special_mcast_table(pp, -1); | |
813 | mvneta_set_other_mcast_table(pp, -1); | |
814 | } | |
815 | ||
816 | /* Set unicast address */ | |
817 | static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, | |
818 | int queue) | |
819 | { | |
820 | unsigned int unicast_reg; | |
821 | unsigned int tbl_offset; | |
822 | unsigned int reg_offset; | |
823 | ||
824 | /* Locate the Unicast table entry */ | |
825 | last_nibble = (0xf & last_nibble); | |
826 | ||
827 | /* offset from unicast tbl base */ | |
828 | tbl_offset = (last_nibble / 4) * 4; | |
829 | ||
830 | /* offset within the above reg */ | |
831 | reg_offset = last_nibble % 4; | |
832 | ||
833 | unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); | |
834 | ||
835 | if (queue == -1) { | |
836 | /* Clear accepts frame bit at specified unicast DA tbl entry */ | |
837 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
838 | } else { | |
839 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
840 | unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
841 | } | |
842 | ||
843 | mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); | |
844 | } | |
845 | ||
846 | /* Set mac address */ | |
847 | static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, | |
848 | int queue) | |
849 | { | |
850 | unsigned int mac_h; | |
851 | unsigned int mac_l; | |
852 | ||
853 | if (queue != -1) { | |
854 | mac_l = (addr[4] << 8) | (addr[5]); | |
855 | mac_h = (addr[0] << 24) | (addr[1] << 16) | | |
856 | (addr[2] << 8) | (addr[3] << 0); | |
857 | ||
858 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); | |
859 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); | |
860 | } | |
861 | ||
862 | /* Accept frames of this address */ | |
863 | mvneta_set_ucast_addr(pp, addr[5], queue); | |
864 | } | |
865 | ||
866 | /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ | |
867 | static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, | |
868 | u32 phys_addr, u32 cookie) | |
869 | { | |
870 | rx_desc->buf_cookie = cookie; | |
871 | rx_desc->buf_phys_addr = phys_addr; | |
872 | } | |
873 | ||
874 | /* Decrement sent descriptors counter */ | |
875 | static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, | |
876 | struct mvneta_tx_queue *txq, | |
877 | int sent_desc) | |
878 | { | |
879 | u32 val; | |
880 | ||
881 | /* Only 255 TX descriptors can be updated at once */ | |
882 | while (sent_desc > 0xff) { | |
883 | val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; | |
884 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
885 | sent_desc = sent_desc - 0xff; | |
886 | } | |
887 | ||
888 | val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; | |
889 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
890 | } | |
891 | ||
892 | /* Get number of TX descriptors already sent by HW */ | |
893 | static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, | |
894 | struct mvneta_tx_queue *txq) | |
895 | { | |
896 | u32 val; | |
897 | int sent_desc; | |
898 | ||
899 | val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); | |
900 | sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> | |
901 | MVNETA_TXQ_SENT_DESC_SHIFT; | |
902 | ||
903 | return sent_desc; | |
904 | } | |
905 | ||
906 | /* Display more error info */ | |
907 | static void mvneta_rx_error(struct mvneta_port *pp, | |
908 | struct mvneta_rx_desc *rx_desc) | |
909 | { | |
910 | u32 status = rx_desc->status; | |
911 | ||
912 | if (!mvneta_rxq_desc_is_first_last(status)) { | |
913 | netdev_err(pp->dev, | |
914 | "bad rx status %08x (buffer oversize), size=%d\n", | |
915 | status, rx_desc->data_size); | |
916 | return; | |
917 | } | |
918 | ||
919 | switch (status & MVNETA_RXD_ERR_CODE_MASK) { | |
920 | case MVNETA_RXD_ERR_CRC: | |
921 | netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", | |
922 | status, rx_desc->data_size); | |
923 | break; | |
924 | case MVNETA_RXD_ERR_OVERRUN: | |
925 | netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", | |
926 | status, rx_desc->data_size); | |
927 | break; | |
928 | case MVNETA_RXD_ERR_LEN: | |
929 | netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", | |
930 | status, rx_desc->data_size); | |
931 | break; | |
932 | case MVNETA_RXD_ERR_RESOURCE: | |
933 | netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", | |
934 | status, rx_desc->data_size); | |
935 | break; | |
936 | } | |
937 | } | |
938 | ||
939 | static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp, | |
940 | int rxq) | |
941 | { | |
942 | return &pp->rxqs[rxq]; | |
943 | } | |
944 | ||
945 | ||
946 | /* Drop packets received by the RXQ and free buffers */ | |
947 | static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, | |
948 | struct mvneta_rx_queue *rxq) | |
949 | { | |
950 | int rx_done; | |
951 | ||
952 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
953 | if (rx_done) | |
954 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); | |
955 | } | |
956 | ||
957 | /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ | |
958 | static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
959 | int num) | |
960 | { | |
961 | int i; | |
962 | ||
963 | for (i = 0; i < num; i++) { | |
964 | u32 addr; | |
965 | ||
966 | /* U-Boot special: Fill in the rx buffer addresses */ | |
967 | addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE); | |
968 | mvneta_rx_desc_fill(rxq->descs + i, addr, addr); | |
969 | } | |
970 | ||
971 | /* Add this number of RX descriptors as non occupied (ready to | |
972 | * get packets) | |
973 | */ | |
974 | mvneta_rxq_non_occup_desc_add(pp, rxq, i); | |
975 | ||
976 | return 0; | |
977 | } | |
978 | ||
979 | /* Rx/Tx queue initialization/cleanup methods */ | |
980 | ||
981 | /* Create a specified RX queue */ | |
982 | static int mvneta_rxq_init(struct mvneta_port *pp, | |
983 | struct mvneta_rx_queue *rxq) | |
984 | ||
985 | { | |
986 | rxq->size = pp->rx_ring_size; | |
987 | ||
988 | /* Allocate memory for RX descriptors */ | |
989 | rxq->descs_phys = (dma_addr_t)rxq->descs; | |
990 | if (rxq->descs == NULL) | |
991 | return -ENOMEM; | |
992 | ||
993 | rxq->last_desc = rxq->size - 1; | |
994 | ||
995 | /* Set Rx descriptors queue starting address */ | |
996 | mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); | |
997 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); | |
998 | ||
999 | /* Fill RXQ with buffers from RX pool */ | |
1000 | mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE); | |
1001 | mvneta_rxq_fill(pp, rxq, rxq->size); | |
1002 | ||
1003 | return 0; | |
1004 | } | |
1005 | ||
1006 | /* Cleanup Rx queue */ | |
1007 | static void mvneta_rxq_deinit(struct mvneta_port *pp, | |
1008 | struct mvneta_rx_queue *rxq) | |
1009 | { | |
1010 | mvneta_rxq_drop_pkts(pp, rxq); | |
1011 | ||
1012 | rxq->descs = NULL; | |
1013 | rxq->last_desc = 0; | |
1014 | rxq->next_desc_to_proc = 0; | |
1015 | rxq->descs_phys = 0; | |
1016 | } | |
1017 | ||
1018 | /* Create and initialize a tx queue */ | |
1019 | static int mvneta_txq_init(struct mvneta_port *pp, | |
1020 | struct mvneta_tx_queue *txq) | |
1021 | { | |
1022 | txq->size = pp->tx_ring_size; | |
1023 | ||
1024 | /* Allocate memory for TX descriptors */ | |
1025 | txq->descs_phys = (u32)txq->descs; | |
1026 | if (txq->descs == NULL) | |
1027 | return -ENOMEM; | |
1028 | ||
1029 | txq->last_desc = txq->size - 1; | |
1030 | ||
1031 | /* Set maximum bandwidth for enabled TXQs */ | |
1032 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); | |
1033 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); | |
1034 | ||
1035 | /* Set Tx descriptors queue starting address */ | |
1036 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); | |
1037 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); | |
1038 | ||
1039 | return 0; | |
1040 | } | |
1041 | ||
1042 | /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ | |
1043 | static void mvneta_txq_deinit(struct mvneta_port *pp, | |
1044 | struct mvneta_tx_queue *txq) | |
1045 | { | |
1046 | txq->descs = NULL; | |
1047 | txq->last_desc = 0; | |
1048 | txq->next_desc_to_proc = 0; | |
1049 | txq->descs_phys = 0; | |
1050 | ||
1051 | /* Set minimum bandwidth for disabled TXQs */ | |
1052 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); | |
1053 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); | |
1054 | ||
1055 | /* Set Tx descriptors queue starting address and size */ | |
1056 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); | |
1057 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); | |
1058 | } | |
1059 | ||
1060 | /* Cleanup all Tx queues */ | |
1061 | static void mvneta_cleanup_txqs(struct mvneta_port *pp) | |
1062 | { | |
1063 | int queue; | |
1064 | ||
1065 | for (queue = 0; queue < txq_number; queue++) | |
1066 | mvneta_txq_deinit(pp, &pp->txqs[queue]); | |
1067 | } | |
1068 | ||
1069 | /* Cleanup all Rx queues */ | |
1070 | static void mvneta_cleanup_rxqs(struct mvneta_port *pp) | |
1071 | { | |
1072 | int queue; | |
1073 | ||
1074 | for (queue = 0; queue < rxq_number; queue++) | |
1075 | mvneta_rxq_deinit(pp, &pp->rxqs[queue]); | |
1076 | } | |
1077 | ||
1078 | ||
1079 | /* Init all Rx queues */ | |
1080 | static int mvneta_setup_rxqs(struct mvneta_port *pp) | |
1081 | { | |
1082 | int queue; | |
1083 | ||
1084 | for (queue = 0; queue < rxq_number; queue++) { | |
1085 | int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); | |
1086 | if (err) { | |
1087 | netdev_err(pp->dev, "%s: can't create rxq=%d\n", | |
1088 | __func__, queue); | |
1089 | mvneta_cleanup_rxqs(pp); | |
1090 | return err; | |
1091 | } | |
1092 | } | |
1093 | ||
1094 | return 0; | |
1095 | } | |
1096 | ||
1097 | /* Init all tx queues */ | |
1098 | static int mvneta_setup_txqs(struct mvneta_port *pp) | |
1099 | { | |
1100 | int queue; | |
1101 | ||
1102 | for (queue = 0; queue < txq_number; queue++) { | |
1103 | int err = mvneta_txq_init(pp, &pp->txqs[queue]); | |
1104 | if (err) { | |
1105 | netdev_err(pp->dev, "%s: can't create txq=%d\n", | |
1106 | __func__, queue); | |
1107 | mvneta_cleanup_txqs(pp); | |
1108 | return err; | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | static void mvneta_start_dev(struct mvneta_port *pp) | |
1116 | { | |
1117 | /* start the Rx/Tx activity */ | |
1118 | mvneta_port_enable(pp); | |
1119 | } | |
1120 | ||
e3b9c98a | 1121 | static void mvneta_adjust_link(struct udevice *dev) |
19fc2eae | 1122 | { |
e3b9c98a | 1123 | struct mvneta_port *pp = dev_get_priv(dev); |
19fc2eae SR |
1124 | struct phy_device *phydev = pp->phydev; |
1125 | int status_change = 0; | |
1126 | ||
1127 | if (phydev->link) { | |
1128 | if ((pp->speed != phydev->speed) || | |
1129 | (pp->duplex != phydev->duplex)) { | |
1130 | u32 val; | |
1131 | ||
1132 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
1133 | val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | | |
1134 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
1135 | MVNETA_GMAC_CONFIG_FULL_DUPLEX | | |
1136 | MVNETA_GMAC_AN_SPEED_EN | | |
1137 | MVNETA_GMAC_AN_DUPLEX_EN); | |
1138 | ||
1139 | if (phydev->duplex) | |
1140 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
1141 | ||
1142 | if (phydev->speed == SPEED_1000) | |
1143 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; | |
1144 | else | |
1145 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; | |
1146 | ||
1147 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
1148 | ||
1149 | pp->duplex = phydev->duplex; | |
1150 | pp->speed = phydev->speed; | |
1151 | } | |
1152 | } | |
1153 | ||
1154 | if (phydev->link != pp->link) { | |
1155 | if (!phydev->link) { | |
1156 | pp->duplex = -1; | |
1157 | pp->speed = 0; | |
1158 | } | |
1159 | ||
1160 | pp->link = phydev->link; | |
1161 | status_change = 1; | |
1162 | } | |
1163 | ||
1164 | if (status_change) { | |
1165 | if (phydev->link) { | |
1166 | u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
1167 | val |= (MVNETA_GMAC_FORCE_LINK_PASS | | |
1168 | MVNETA_GMAC_FORCE_LINK_DOWN); | |
1169 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
1170 | mvneta_port_up(pp); | |
1171 | } else { | |
1172 | mvneta_port_down(pp); | |
1173 | } | |
1174 | } | |
1175 | } | |
1176 | ||
e3b9c98a | 1177 | static int mvneta_open(struct udevice *dev) |
19fc2eae | 1178 | { |
e3b9c98a | 1179 | struct mvneta_port *pp = dev_get_priv(dev); |
19fc2eae SR |
1180 | int ret; |
1181 | ||
1182 | ret = mvneta_setup_rxqs(pp); | |
1183 | if (ret) | |
1184 | return ret; | |
1185 | ||
1186 | ret = mvneta_setup_txqs(pp); | |
1187 | if (ret) | |
1188 | return ret; | |
1189 | ||
1190 | mvneta_adjust_link(dev); | |
1191 | ||
1192 | mvneta_start_dev(pp); | |
1193 | ||
1194 | return 0; | |
1195 | } | |
1196 | ||
1197 | /* Initialize hw */ | |
e3b9c98a | 1198 | static int mvneta_init2(struct mvneta_port *pp) |
19fc2eae SR |
1199 | { |
1200 | int queue; | |
1201 | ||
1202 | /* Disable port */ | |
1203 | mvneta_port_disable(pp); | |
1204 | ||
1205 | /* Set port default values */ | |
1206 | mvneta_defaults_set(pp); | |
1207 | ||
1208 | pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue), | |
1209 | GFP_KERNEL); | |
1210 | if (!pp->txqs) | |
1211 | return -ENOMEM; | |
1212 | ||
1213 | /* U-Boot special: use preallocated area */ | |
1214 | pp->txqs[0].descs = buffer_loc.tx_descs; | |
1215 | ||
1216 | /* Initialize TX descriptor rings */ | |
1217 | for (queue = 0; queue < txq_number; queue++) { | |
1218 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
1219 | txq->id = queue; | |
1220 | txq->size = pp->tx_ring_size; | |
1221 | } | |
1222 | ||
1223 | pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue), | |
1224 | GFP_KERNEL); | |
1225 | if (!pp->rxqs) { | |
1226 | kfree(pp->txqs); | |
1227 | return -ENOMEM; | |
1228 | } | |
1229 | ||
1230 | /* U-Boot special: use preallocated area */ | |
1231 | pp->rxqs[0].descs = buffer_loc.rx_descs; | |
1232 | ||
1233 | /* Create Rx descriptor rings */ | |
1234 | for (queue = 0; queue < rxq_number; queue++) { | |
1235 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
1236 | rxq->id = queue; | |
1237 | rxq->size = pp->rx_ring_size; | |
1238 | } | |
1239 | ||
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | /* platform glue : initialize decoding windows */ | |
1244 | static void mvneta_conf_mbus_windows(struct mvneta_port *pp) | |
1245 | { | |
1246 | const struct mbus_dram_target_info *dram; | |
1247 | u32 win_enable; | |
1248 | u32 win_protect; | |
1249 | int i; | |
1250 | ||
1251 | dram = mvebu_mbus_dram_info(); | |
1252 | for (i = 0; i < 6; i++) { | |
1253 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
1254 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
1255 | ||
1256 | if (i < 4) | |
1257 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
1258 | } | |
1259 | ||
1260 | win_enable = 0x3f; | |
1261 | win_protect = 0; | |
1262 | ||
1263 | for (i = 0; i < dram->num_cs; i++) { | |
1264 | const struct mbus_dram_window *cs = dram->cs + i; | |
1265 | mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | | |
1266 | (cs->mbus_attr << 8) | dram->mbus_dram_target_id); | |
1267 | ||
1268 | mvreg_write(pp, MVNETA_WIN_SIZE(i), | |
1269 | (cs->size - 1) & 0xffff0000); | |
1270 | ||
1271 | win_enable &= ~(1 << i); | |
1272 | win_protect |= 3 << (2 * i); | |
1273 | } | |
1274 | ||
1275 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
1276 | } | |
1277 | ||
1278 | /* Power up the port */ | |
1279 | static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) | |
1280 | { | |
1281 | u32 ctrl; | |
1282 | ||
1283 | /* MAC Cause register should be cleared */ | |
1284 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); | |
1285 | ||
1286 | ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | |
1287 | ||
1288 | /* Even though it might look weird, when we're configured in | |
1289 | * SGMII or QSGMII mode, the RGMII bit needs to be set. | |
1290 | */ | |
1291 | switch (phy_mode) { | |
1292 | case PHY_INTERFACE_MODE_QSGMII: | |
1293 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); | |
1294 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; | |
1295 | break; | |
1296 | case PHY_INTERFACE_MODE_SGMII: | |
1297 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); | |
1298 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; | |
1299 | break; | |
1300 | case PHY_INTERFACE_MODE_RGMII: | |
1301 | case PHY_INTERFACE_MODE_RGMII_ID: | |
1302 | ctrl |= MVNETA_GMAC2_PORT_RGMII; | |
1303 | break; | |
1304 | default: | |
1305 | return -EINVAL; | |
1306 | } | |
1307 | ||
1308 | /* Cancel Port Reset */ | |
1309 | ctrl &= ~MVNETA_GMAC2_PORT_RESET; | |
1310 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); | |
1311 | ||
1312 | while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & | |
1313 | MVNETA_GMAC2_PORT_RESET) != 0) | |
1314 | continue; | |
1315 | ||
1316 | return 0; | |
1317 | } | |
1318 | ||
1319 | /* Device initialization routine */ | |
e3b9c98a | 1320 | static int mvneta_init(struct udevice *dev) |
19fc2eae | 1321 | { |
e3b9c98a SR |
1322 | struct eth_pdata *pdata = dev_get_platdata(dev); |
1323 | struct mvneta_port *pp = dev_get_priv(dev); | |
19fc2eae SR |
1324 | int err; |
1325 | ||
1326 | pp->tx_ring_size = MVNETA_MAX_TXD; | |
1327 | pp->rx_ring_size = MVNETA_MAX_RXD; | |
1328 | ||
e3b9c98a | 1329 | err = mvneta_init2(pp); |
19fc2eae SR |
1330 | if (err < 0) { |
1331 | dev_err(&pdev->dev, "can't init eth hal\n"); | |
1332 | return err; | |
1333 | } | |
1334 | ||
e3b9c98a | 1335 | mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def); |
19fc2eae SR |
1336 | |
1337 | err = mvneta_port_power_up(pp, pp->phy_interface); | |
1338 | if (err < 0) { | |
1339 | dev_err(&pdev->dev, "can't power up port\n"); | |
1340 | return err; | |
1341 | } | |
1342 | ||
1343 | /* Call open() now as it needs to be done before runing send() */ | |
1344 | mvneta_open(dev); | |
1345 | ||
1346 | return 0; | |
1347 | } | |
1348 | ||
1349 | /* U-Boot only functions follow here */ | |
1350 | ||
1351 | /* SMI / MDIO functions */ | |
1352 | ||
1353 | static int smi_wait_ready(struct mvneta_port *pp) | |
1354 | { | |
1355 | u32 timeout = MVNETA_SMI_TIMEOUT; | |
1356 | u32 smi_reg; | |
1357 | ||
1358 | /* wait till the SMI is not busy */ | |
1359 | do { | |
1360 | /* read smi register */ | |
1361 | smi_reg = mvreg_read(pp, MVNETA_SMI); | |
1362 | if (timeout-- == 0) { | |
1363 | printf("Error: SMI busy timeout\n"); | |
1364 | return -EFAULT; | |
1365 | } | |
1366 | } while (smi_reg & MVNETA_SMI_BUSY); | |
1367 | ||
1368 | return 0; | |
1369 | } | |
1370 | ||
1371 | /* | |
e3b9c98a | 1372 | * mvneta_mdio_read - miiphy_read callback function. |
19fc2eae SR |
1373 | * |
1374 | * Returns 16bit phy register value, or 0xffff on error | |
1375 | */ | |
e3b9c98a | 1376 | static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) |
19fc2eae | 1377 | { |
e3b9c98a | 1378 | struct mvneta_port *pp = bus->priv; |
19fc2eae SR |
1379 | u32 smi_reg; |
1380 | u32 timeout; | |
1381 | ||
1382 | /* check parameters */ | |
e3b9c98a SR |
1383 | if (addr > MVNETA_PHY_ADDR_MASK) { |
1384 | printf("Error: Invalid PHY address %d\n", addr); | |
19fc2eae SR |
1385 | return -EFAULT; |
1386 | } | |
1387 | ||
e3b9c98a SR |
1388 | if (reg > MVNETA_PHY_REG_MASK) { |
1389 | printf("Err: Invalid register offset %d\n", reg); | |
19fc2eae SR |
1390 | return -EFAULT; |
1391 | } | |
1392 | ||
1393 | /* wait till the SMI is not busy */ | |
1394 | if (smi_wait_ready(pp) < 0) | |
1395 | return -EFAULT; | |
1396 | ||
1397 | /* fill the phy address and regiser offset and read opcode */ | |
e3b9c98a SR |
1398 | smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS) |
1399 | | (reg << MVNETA_SMI_REG_ADDR_OFFS) | |
19fc2eae SR |
1400 | | MVNETA_SMI_OPCODE_READ; |
1401 | ||
1402 | /* write the smi register */ | |
1403 | mvreg_write(pp, MVNETA_SMI, smi_reg); | |
1404 | ||
e3b9c98a | 1405 | /* wait till read value is ready */ |
19fc2eae SR |
1406 | timeout = MVNETA_SMI_TIMEOUT; |
1407 | ||
1408 | do { | |
1409 | /* read smi register */ | |
1410 | smi_reg = mvreg_read(pp, MVNETA_SMI); | |
1411 | if (timeout-- == 0) { | |
1412 | printf("Err: SMI read ready timeout\n"); | |
1413 | return -EFAULT; | |
1414 | } | |
1415 | } while (!(smi_reg & MVNETA_SMI_READ_VALID)); | |
1416 | ||
1417 | /* Wait for the data to update in the SMI register */ | |
1418 | for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++) | |
1419 | ; | |
1420 | ||
e3b9c98a | 1421 | return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK; |
19fc2eae SR |
1422 | } |
1423 | ||
1424 | /* | |
e3b9c98a | 1425 | * mvneta_mdio_write - miiphy_write callback function. |
19fc2eae SR |
1426 | * |
1427 | * Returns 0 if write succeed, -EINVAL on bad parameters | |
1428 | * -ETIME on timeout | |
1429 | */ | |
e3b9c98a SR |
1430 | static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, |
1431 | u16 value) | |
19fc2eae | 1432 | { |
e3b9c98a | 1433 | struct mvneta_port *pp = bus->priv; |
19fc2eae SR |
1434 | u32 smi_reg; |
1435 | ||
1436 | /* check parameters */ | |
e3b9c98a SR |
1437 | if (addr > MVNETA_PHY_ADDR_MASK) { |
1438 | printf("Error: Invalid PHY address %d\n", addr); | |
19fc2eae SR |
1439 | return -EFAULT; |
1440 | } | |
1441 | ||
e3b9c98a SR |
1442 | if (reg > MVNETA_PHY_REG_MASK) { |
1443 | printf("Err: Invalid register offset %d\n", reg); | |
19fc2eae SR |
1444 | return -EFAULT; |
1445 | } | |
1446 | ||
1447 | /* wait till the SMI is not busy */ | |
1448 | if (smi_wait_ready(pp) < 0) | |
1449 | return -EFAULT; | |
1450 | ||
1451 | /* fill the phy addr and reg offset and write opcode and data */ | |
e3b9c98a SR |
1452 | smi_reg = value << MVNETA_SMI_DATA_OFFS; |
1453 | smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS) | |
1454 | | (reg << MVNETA_SMI_REG_ADDR_OFFS); | |
19fc2eae SR |
1455 | smi_reg &= ~MVNETA_SMI_OPCODE_READ; |
1456 | ||
1457 | /* write the smi register */ | |
1458 | mvreg_write(pp, MVNETA_SMI, smi_reg); | |
1459 | ||
1460 | return 0; | |
1461 | } | |
1462 | ||
e3b9c98a | 1463 | static int mvneta_start(struct udevice *dev) |
19fc2eae | 1464 | { |
e3b9c98a | 1465 | struct mvneta_port *pp = dev_get_priv(dev); |
19fc2eae SR |
1466 | struct phy_device *phydev; |
1467 | ||
1468 | mvneta_port_power_up(pp, pp->phy_interface); | |
1469 | ||
1470 | if (!pp->init || pp->link == 0) { | |
1471 | /* Set phy address of the port */ | |
1472 | mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr); | |
1473 | phydev = phy_connect(pp->bus, pp->phyaddr, dev, | |
1474 | pp->phy_interface); | |
1475 | ||
1476 | pp->phydev = phydev; | |
1477 | phy_config(phydev); | |
1478 | phy_startup(phydev); | |
1479 | if (!phydev->link) { | |
1480 | printf("%s: No link.\n", phydev->dev->name); | |
1481 | return -1; | |
1482 | } | |
1483 | ||
1484 | /* Full init on first call */ | |
e3b9c98a | 1485 | mvneta_init(dev); |
19fc2eae SR |
1486 | pp->init = 1; |
1487 | } else { | |
1488 | /* Upon all following calls, this is enough */ | |
1489 | mvneta_port_up(pp); | |
1490 | mvneta_port_enable(pp); | |
1491 | } | |
1492 | ||
1493 | return 0; | |
1494 | } | |
1495 | ||
e3b9c98a | 1496 | static int mvneta_send(struct udevice *dev, void *packet, int length) |
19fc2eae | 1497 | { |
e3b9c98a | 1498 | struct mvneta_port *pp = dev_get_priv(dev); |
19fc2eae SR |
1499 | struct mvneta_tx_queue *txq = &pp->txqs[0]; |
1500 | struct mvneta_tx_desc *tx_desc; | |
1501 | int sent_desc; | |
1502 | u32 timeout = 0; | |
1503 | ||
1504 | /* Get a descriptor for the first part of the packet */ | |
1505 | tx_desc = mvneta_txq_next_desc_get(txq); | |
1506 | ||
e3b9c98a SR |
1507 | tx_desc->buf_phys_addr = (u32)packet; |
1508 | tx_desc->data_size = length; | |
35e3fca7 SR |
1509 | flush_dcache_range((u32)packet, |
1510 | (u32)packet + ALIGN(length, PKTALIGN)); | |
19fc2eae SR |
1511 | |
1512 | /* First and Last descriptor */ | |
1513 | tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC; | |
1514 | mvneta_txq_pend_desc_add(pp, txq, 1); | |
1515 | ||
1516 | /* Wait for packet to be sent (queue might help with speed here) */ | |
1517 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); | |
1518 | while (!sent_desc) { | |
1519 | if (timeout++ > 10000) { | |
1520 | printf("timeout: packet not sent\n"); | |
1521 | return -1; | |
1522 | } | |
1523 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); | |
1524 | } | |
1525 | ||
1526 | /* txDone has increased - hw sent packet */ | |
1527 | mvneta_txq_sent_desc_dec(pp, txq, sent_desc); | |
19fc2eae SR |
1528 | |
1529 | return 0; | |
1530 | } | |
1531 | ||
e3b9c98a | 1532 | static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp) |
19fc2eae | 1533 | { |
e3b9c98a | 1534 | struct mvneta_port *pp = dev_get_priv(dev); |
19fc2eae | 1535 | int rx_done; |
19fc2eae | 1536 | struct mvneta_rx_queue *rxq; |
e3b9c98a | 1537 | int rx_bytes = 0; |
19fc2eae SR |
1538 | |
1539 | /* get rx queue */ | |
1540 | rxq = mvneta_rxq_handle_get(pp, rxq_def); | |
1541 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
19fc2eae | 1542 | |
e3b9c98a | 1543 | if (rx_done) { |
19fc2eae SR |
1544 | struct mvneta_rx_desc *rx_desc; |
1545 | unsigned char *data; | |
1546 | u32 rx_status; | |
19fc2eae SR |
1547 | |
1548 | /* | |
1549 | * No cache invalidation needed here, since the desc's are | |
1550 | * located in a uncached memory region | |
1551 | */ | |
1552 | rx_desc = mvneta_rxq_next_desc_get(rxq); | |
1553 | ||
1554 | rx_status = rx_desc->status; | |
1555 | if (!mvneta_rxq_desc_is_first_last(rx_status) || | |
1556 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { | |
1557 | mvneta_rx_error(pp, rx_desc); | |
1558 | /* leave the descriptor untouched */ | |
e3b9c98a | 1559 | return -EIO; |
19fc2eae SR |
1560 | } |
1561 | ||
1562 | /* 2 bytes for marvell header. 4 bytes for crc */ | |
1563 | rx_bytes = rx_desc->data_size - 6; | |
1564 | ||
1565 | /* give packet to stack - skip on first 2 bytes */ | |
1566 | data = (u8 *)rx_desc->buf_cookie + 2; | |
1567 | /* | |
1568 | * No cache invalidation needed here, since the rx_buffer's are | |
1569 | * located in a uncached memory region | |
1570 | */ | |
e3b9c98a | 1571 | *packetp = data; |
19fc2eae | 1572 | |
19fc2eae | 1573 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); |
e3b9c98a | 1574 | } |
19fc2eae | 1575 | |
e3b9c98a | 1576 | return rx_bytes; |
19fc2eae SR |
1577 | } |
1578 | ||
e3b9c98a | 1579 | static int mvneta_probe(struct udevice *dev) |
19fc2eae | 1580 | { |
e3b9c98a SR |
1581 | struct eth_pdata *pdata = dev_get_platdata(dev); |
1582 | struct mvneta_port *pp = dev_get_priv(dev); | |
1583 | void *blob = (void *)gd->fdt_blob; | |
1584 | int node = dev->of_offset; | |
1585 | struct mii_dev *bus; | |
1586 | unsigned long addr; | |
19fc2eae SR |
1587 | void *bd_space; |
1588 | ||
19fc2eae SR |
1589 | /* |
1590 | * Allocate buffer area for descs and rx_buffers. This is only | |
1591 | * done once for all interfaces. As only one interface can | |
1592 | * be active. Make this area DMA save by disabling the D-cache | |
1593 | */ | |
1594 | if (!buffer_loc.tx_descs) { | |
1595 | /* Align buffer area for descs and rx_buffers to 1MiB */ | |
1596 | bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); | |
1597 | mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, | |
1598 | DCACHE_OFF); | |
1599 | buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space; | |
1600 | buffer_loc.rx_descs = (struct mvneta_rx_desc *) | |
1601 | ((u32)bd_space + | |
1602 | MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc)); | |
1603 | buffer_loc.rx_buffers = (u32) | |
1604 | (bd_space + | |
1605 | MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) + | |
1606 | MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc)); | |
1607 | } | |
1608 | ||
e3b9c98a | 1609 | pp->base = (void __iomem *)pdata->iobase; |
19fc2eae | 1610 | |
e3b9c98a SR |
1611 | /* Configure MBUS address windows */ |
1612 | mvneta_conf_mbus_windows(pp); | |
19fc2eae | 1613 | |
e3b9c98a SR |
1614 | /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */ |
1615 | pp->phy_interface = pdata->phy_interface; | |
1616 | ||
1617 | /* Now read phyaddr from DT */ | |
1618 | addr = fdtdec_get_int(blob, node, "phy", 0); | |
1619 | addr = fdt_node_offset_by_phandle(blob, addr); | |
1620 | pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0); | |
1621 | ||
1622 | bus = mdio_alloc(); | |
1623 | if (!bus) { | |
1624 | printf("Failed to allocate MDIO bus\n"); | |
1625 | return -ENOMEM; | |
1626 | } | |
1627 | ||
1628 | bus->read = mvneta_mdio_read; | |
1629 | bus->write = mvneta_mdio_write; | |
1630 | snprintf(bus->name, sizeof(bus->name), dev->name); | |
1631 | bus->priv = (void *)pp; | |
1632 | pp->bus = bus; | |
19fc2eae | 1633 | |
e3b9c98a SR |
1634 | return mdio_register(bus); |
1635 | } | |
19fc2eae | 1636 | |
e3b9c98a SR |
1637 | static void mvneta_stop(struct udevice *dev) |
1638 | { | |
1639 | struct mvneta_port *pp = dev_get_priv(dev); | |
19fc2eae | 1640 | |
e3b9c98a SR |
1641 | mvneta_port_down(pp); |
1642 | mvneta_port_disable(pp); | |
19fc2eae | 1643 | } |
e3b9c98a SR |
1644 | |
1645 | static const struct eth_ops mvneta_ops = { | |
1646 | .start = mvneta_start, | |
1647 | .send = mvneta_send, | |
1648 | .recv = mvneta_recv, | |
1649 | .stop = mvneta_stop, | |
1650 | }; | |
1651 | ||
1652 | static int mvneta_ofdata_to_platdata(struct udevice *dev) | |
1653 | { | |
1654 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
1655 | const char *phy_mode; | |
1656 | ||
1657 | pdata->iobase = dev_get_addr(dev); | |
1658 | ||
1659 | /* Get phy-mode / phy_interface from DT */ | |
1660 | pdata->phy_interface = -1; | |
1661 | phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); | |
1662 | if (phy_mode) | |
1663 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); | |
1664 | if (pdata->phy_interface == -1) { | |
1665 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); | |
1666 | return -EINVAL; | |
1667 | } | |
1668 | ||
1669 | return 0; | |
1670 | } | |
1671 | ||
1672 | static const struct udevice_id mvneta_ids[] = { | |
1673 | { .compatible = "marvell,armada-370-neta" }, | |
1674 | { .compatible = "marvell,armada-xp-neta" }, | |
1675 | { } | |
1676 | }; | |
1677 | ||
1678 | U_BOOT_DRIVER(mvneta) = { | |
1679 | .name = "mvneta", | |
1680 | .id = UCLASS_ETH, | |
1681 | .of_match = mvneta_ids, | |
1682 | .ofdata_to_platdata = mvneta_ofdata_to_platdata, | |
1683 | .probe = mvneta_probe, | |
1684 | .ops = &mvneta_ops, | |
1685 | .priv_auto_alloc_size = sizeof(struct mvneta_port), | |
1686 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
1687 | }; |