]>
Commit | Line | Data |
---|---|---|
19fc2eae SR |
1 | /* |
2 | * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. | |
3 | * | |
4 | * U-Boot version: | |
e3b9c98a | 5 | * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> |
19fc2eae SR |
6 | * |
7 | * Based on the Linux version which is: | |
8 | * Copyright (C) 2012 Marvell | |
9 | * | |
10 | * Rami Rosen <rosenr@marvell.com> | |
11 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
12 | * | |
13 | * SPDX-License-Identifier: GPL-2.0 | |
14 | */ | |
15 | ||
16 | #include <common.h> | |
e3b9c98a | 17 | #include <dm.h> |
19fc2eae SR |
18 | #include <net.h> |
19 | #include <netdev.h> | |
20 | #include <config.h> | |
21 | #include <malloc.h> | |
22 | #include <asm/io.h> | |
1221ce45 | 23 | #include <linux/errno.h> |
19fc2eae SR |
24 | #include <phy.h> |
25 | #include <miiphy.h> | |
26 | #include <watchdog.h> | |
27 | #include <asm/arch/cpu.h> | |
28 | #include <asm/arch/soc.h> | |
29 | #include <linux/compat.h> | |
30 | #include <linux/mbus.h> | |
31 | ||
e3b9c98a SR |
32 | DECLARE_GLOBAL_DATA_PTR; |
33 | ||
19fc2eae SR |
34 | #if !defined(CONFIG_PHYLIB) |
35 | # error Marvell mvneta requires PHYLIB | |
36 | #endif | |
37 | ||
38 | /* Some linux -> U-Boot compatibility stuff */ | |
39 | #define netdev_err(dev, fmt, args...) \ | |
40 | printf(fmt, ##args) | |
41 | #define netdev_warn(dev, fmt, args...) \ | |
42 | printf(fmt, ##args) | |
43 | #define netdev_info(dev, fmt, args...) \ | |
44 | printf(fmt, ##args) | |
45 | ||
46 | #define CONFIG_NR_CPUS 1 | |
19fc2eae SR |
47 | #define ETH_HLEN 14 /* Total octets in header */ |
48 | ||
49 | /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */ | |
50 | #define WRAP (2 + ETH_HLEN + 4 + 32) | |
51 | #define MTU 1500 | |
52 | #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN)) | |
53 | ||
54 | #define MVNETA_SMI_TIMEOUT 10000 | |
55 | ||
56 | /* Registers */ | |
57 | #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) | |
58 | #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) | |
59 | #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) | |
60 | #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) | |
61 | #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) | |
62 | #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) | |
63 | #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) | |
64 | #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) | |
65 | #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 | |
66 | #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) | |
67 | #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) | |
68 | #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff | |
69 | #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) | |
70 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 | |
71 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 | |
72 | #define MVNETA_PORT_RX_RESET 0x1cc0 | |
73 | #define MVNETA_PORT_RX_DMA_RESET BIT(0) | |
74 | #define MVNETA_PHY_ADDR 0x2000 | |
75 | #define MVNETA_PHY_ADDR_MASK 0x1f | |
76 | #define MVNETA_SMI 0x2004 | |
77 | #define MVNETA_PHY_REG_MASK 0x1f | |
78 | /* SMI register fields */ | |
79 | #define MVNETA_SMI_DATA_OFFS 0 /* Data */ | |
80 | #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS) | |
81 | #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ | |
82 | #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/ | |
83 | #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ | |
84 | #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS) | |
85 | #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */ | |
86 | #define MVNETA_SMI_BUSY (1 << 28) /* Busy */ | |
87 | #define MVNETA_MBUS_RETRY 0x2010 | |
88 | #define MVNETA_UNIT_INTR_CAUSE 0x2080 | |
89 | #define MVNETA_UNIT_CONTROL 0x20B0 | |
90 | #define MVNETA_PHY_POLLING_ENABLE BIT(1) | |
91 | #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) | |
92 | #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) | |
93 | #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) | |
544eefe0 | 94 | #define MVNETA_WIN_SIZE_MASK (0xffff0000) |
19fc2eae | 95 | #define MVNETA_BASE_ADDR_ENABLE 0x2290 |
544eefe0 SR |
96 | #define MVNETA_BASE_ADDR_ENABLE_BIT 0x1 |
97 | #define MVNETA_PORT_ACCESS_PROTECT 0x2294 | |
98 | #define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3 | |
19fc2eae SR |
99 | #define MVNETA_PORT_CONFIG 0x2400 |
100 | #define MVNETA_UNI_PROMISC_MODE BIT(0) | |
101 | #define MVNETA_DEF_RXQ(q) ((q) << 1) | |
102 | #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) | |
103 | #define MVNETA_TX_UNSET_ERR_SUM BIT(12) | |
104 | #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) | |
105 | #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) | |
106 | #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) | |
107 | #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) | |
108 | #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ | |
109 | MVNETA_DEF_RXQ_ARP(q) | \ | |
110 | MVNETA_DEF_RXQ_TCP(q) | \ | |
111 | MVNETA_DEF_RXQ_UDP(q) | \ | |
112 | MVNETA_DEF_RXQ_BPDU(q) | \ | |
113 | MVNETA_TX_UNSET_ERR_SUM | \ | |
114 | MVNETA_RX_CSUM_WITH_PSEUDO_HDR) | |
115 | #define MVNETA_PORT_CONFIG_EXTEND 0x2404 | |
116 | #define MVNETA_MAC_ADDR_LOW 0x2414 | |
117 | #define MVNETA_MAC_ADDR_HIGH 0x2418 | |
118 | #define MVNETA_SDMA_CONFIG 0x241c | |
119 | #define MVNETA_SDMA_BRST_SIZE_16 4 | |
120 | #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) | |
121 | #define MVNETA_RX_NO_DATA_SWAP BIT(4) | |
122 | #define MVNETA_TX_NO_DATA_SWAP BIT(5) | |
123 | #define MVNETA_DESC_SWAP BIT(6) | |
124 | #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) | |
125 | #define MVNETA_PORT_STATUS 0x2444 | |
126 | #define MVNETA_TX_IN_PRGRS BIT(1) | |
127 | #define MVNETA_TX_FIFO_EMPTY BIT(8) | |
128 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c | |
129 | #define MVNETA_SERDES_CFG 0x24A0 | |
130 | #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 | |
131 | #define MVNETA_QSGMII_SERDES_PROTO 0x0667 | |
132 | #define MVNETA_TYPE_PRIO 0x24bc | |
133 | #define MVNETA_FORCE_UNI BIT(21) | |
134 | #define MVNETA_TXQ_CMD_1 0x24e4 | |
135 | #define MVNETA_TXQ_CMD 0x2448 | |
136 | #define MVNETA_TXQ_DISABLE_SHIFT 8 | |
137 | #define MVNETA_TXQ_ENABLE_MASK 0x000000ff | |
138 | #define MVNETA_ACC_MODE 0x2500 | |
139 | #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) | |
140 | #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff | |
141 | #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 | |
142 | #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) | |
143 | ||
144 | /* Exception Interrupt Port/Queue Cause register */ | |
145 | ||
146 | #define MVNETA_INTR_NEW_CAUSE 0x25a0 | |
147 | #define MVNETA_INTR_NEW_MASK 0x25a4 | |
148 | ||
149 | /* bits 0..7 = TXQ SENT, one bit per queue. | |
150 | * bits 8..15 = RXQ OCCUP, one bit per queue. | |
151 | * bits 16..23 = RXQ FREE, one bit per queue. | |
152 | * bit 29 = OLD_REG_SUM, see old reg ? | |
153 | * bit 30 = TX_ERR_SUM, one bit for 4 ports | |
154 | * bit 31 = MISC_SUM, one bit for 4 ports | |
155 | */ | |
156 | #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) | |
157 | #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) | |
158 | #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) | |
159 | #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) | |
160 | ||
161 | #define MVNETA_INTR_OLD_CAUSE 0x25a8 | |
162 | #define MVNETA_INTR_OLD_MASK 0x25ac | |
163 | ||
164 | /* Data Path Port/Queue Cause Register */ | |
165 | #define MVNETA_INTR_MISC_CAUSE 0x25b0 | |
166 | #define MVNETA_INTR_MISC_MASK 0x25b4 | |
167 | #define MVNETA_INTR_ENABLE 0x25b8 | |
168 | ||
169 | #define MVNETA_RXQ_CMD 0x2680 | |
170 | #define MVNETA_RXQ_DISABLE_SHIFT 8 | |
171 | #define MVNETA_RXQ_ENABLE_MASK 0x000000ff | |
172 | #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) | |
173 | #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) | |
174 | #define MVNETA_GMAC_CTRL_0 0x2c00 | |
175 | #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 | |
176 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
177 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) | |
178 | #define MVNETA_GMAC_CTRL_2 0x2c08 | |
179 | #define MVNETA_GMAC2_PCS_ENABLE BIT(3) | |
180 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) | |
181 | #define MVNETA_GMAC2_PORT_RESET BIT(6) | |
182 | #define MVNETA_GMAC_STATUS 0x2c10 | |
183 | #define MVNETA_GMAC_LINK_UP BIT(0) | |
184 | #define MVNETA_GMAC_SPEED_1000 BIT(1) | |
185 | #define MVNETA_GMAC_SPEED_100 BIT(2) | |
186 | #define MVNETA_GMAC_FULL_DUPLEX BIT(3) | |
187 | #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) | |
188 | #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) | |
189 | #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) | |
190 | #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) | |
191 | #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c | |
192 | #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) | |
193 | #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) | |
194 | #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) | |
195 | #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) | |
196 | #define MVNETA_GMAC_AN_SPEED_EN BIT(7) | |
197 | #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) | |
198 | #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) | |
199 | #define MVNETA_MIB_COUNTERS_BASE 0x3080 | |
200 | #define MVNETA_MIB_LATE_COLLISION 0x7c | |
201 | #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 | |
202 | #define MVNETA_DA_FILT_OTH_MCAST 0x3500 | |
203 | #define MVNETA_DA_FILT_UCAST_BASE 0x3600 | |
204 | #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) | |
205 | #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) | |
206 | #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 | |
207 | #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) | |
208 | #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) | |
209 | #define MVNETA_TXQ_DEC_SENT_SHIFT 16 | |
210 | #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) | |
211 | #define MVNETA_TXQ_SENT_DESC_SHIFT 16 | |
212 | #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 | |
213 | #define MVNETA_PORT_TX_RESET 0x3cf0 | |
214 | #define MVNETA_PORT_TX_DMA_RESET BIT(0) | |
215 | #define MVNETA_TX_MTU 0x3e0c | |
216 | #define MVNETA_TX_TOKEN_SIZE 0x3e14 | |
217 | #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff | |
218 | #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) | |
219 | #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
220 | ||
221 | /* Descriptor ring Macros */ | |
222 | #define MVNETA_QUEUE_NEXT_DESC(q, index) \ | |
223 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
224 | ||
225 | /* Various constants */ | |
226 | ||
227 | /* Coalescing */ | |
228 | #define MVNETA_TXDONE_COAL_PKTS 16 | |
229 | #define MVNETA_RX_COAL_PKTS 32 | |
230 | #define MVNETA_RX_COAL_USEC 100 | |
231 | ||
232 | /* The two bytes Marvell header. Either contains a special value used | |
233 | * by Marvell switches when a specific hardware mode is enabled (not | |
234 | * supported by this driver) or is filled automatically by zeroes on | |
235 | * the RX side. Those two bytes being at the front of the Ethernet | |
236 | * header, they allow to have the IP header aligned on a 4 bytes | |
237 | * boundary automatically: the hardware skips those two bytes on its | |
238 | * own. | |
239 | */ | |
240 | #define MVNETA_MH_SIZE 2 | |
241 | ||
242 | #define MVNETA_VLAN_TAG_LEN 4 | |
243 | ||
244 | #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 | |
245 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 | |
246 | #define MVNETA_ACC_MODE_EXT 1 | |
247 | ||
248 | /* Timeout constants */ | |
249 | #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 | |
250 | #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 | |
251 | #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 | |
252 | ||
253 | #define MVNETA_TX_MTU_MAX 0x3ffff | |
254 | ||
255 | /* Max number of Rx descriptors */ | |
256 | #define MVNETA_MAX_RXD 16 | |
257 | ||
258 | /* Max number of Tx descriptors */ | |
259 | #define MVNETA_MAX_TXD 16 | |
260 | ||
261 | /* descriptor aligned size */ | |
262 | #define MVNETA_DESC_ALIGNED_SIZE 32 | |
263 | ||
264 | struct mvneta_port { | |
265 | void __iomem *base; | |
266 | struct mvneta_rx_queue *rxqs; | |
267 | struct mvneta_tx_queue *txqs; | |
268 | ||
269 | u8 mcast_count[256]; | |
270 | u16 tx_ring_size; | |
271 | u16 rx_ring_size; | |
272 | ||
273 | phy_interface_t phy_interface; | |
274 | unsigned int link; | |
275 | unsigned int duplex; | |
276 | unsigned int speed; | |
277 | ||
278 | int init; | |
279 | int phyaddr; | |
280 | struct phy_device *phydev; | |
281 | struct mii_dev *bus; | |
282 | }; | |
283 | ||
284 | /* The mvneta_tx_desc and mvneta_rx_desc structures describe the | |
285 | * layout of the transmit and reception DMA descriptors, and their | |
286 | * layout is therefore defined by the hardware design | |
287 | */ | |
288 | ||
289 | #define MVNETA_TX_L3_OFF_SHIFT 0 | |
290 | #define MVNETA_TX_IP_HLEN_SHIFT 8 | |
291 | #define MVNETA_TX_L4_UDP BIT(16) | |
292 | #define MVNETA_TX_L3_IP6 BIT(17) | |
293 | #define MVNETA_TXD_IP_CSUM BIT(18) | |
294 | #define MVNETA_TXD_Z_PAD BIT(19) | |
295 | #define MVNETA_TXD_L_DESC BIT(20) | |
296 | #define MVNETA_TXD_F_DESC BIT(21) | |
297 | #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ | |
298 | MVNETA_TXD_L_DESC | \ | |
299 | MVNETA_TXD_F_DESC) | |
300 | #define MVNETA_TX_L4_CSUM_FULL BIT(30) | |
301 | #define MVNETA_TX_L4_CSUM_NOT BIT(31) | |
302 | ||
303 | #define MVNETA_RXD_ERR_CRC 0x0 | |
304 | #define MVNETA_RXD_ERR_SUMMARY BIT(16) | |
305 | #define MVNETA_RXD_ERR_OVERRUN BIT(17) | |
306 | #define MVNETA_RXD_ERR_LEN BIT(18) | |
307 | #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) | |
308 | #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) | |
309 | #define MVNETA_RXD_L3_IP4 BIT(25) | |
310 | #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) | |
311 | #define MVNETA_RXD_L4_CSUM_OK BIT(30) | |
312 | ||
313 | struct mvneta_tx_desc { | |
314 | u32 command; /* Options used by HW for packet transmitting.*/ | |
315 | u16 reserverd1; /* csum_l4 (for future use) */ | |
316 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
317 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
318 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
319 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
320 | }; | |
321 | ||
322 | struct mvneta_rx_desc { | |
323 | u32 status; /* Info about received packet */ | |
324 | u16 reserved1; /* pnc_info - (for future use, PnC) */ | |
325 | u16 data_size; /* Size of received packet in bytes */ | |
326 | ||
327 | u32 buf_phys_addr; /* Physical address of the buffer */ | |
328 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
329 | ||
330 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ | |
331 | u16 reserved3; /* prefetch_cmd, for future use */ | |
332 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
333 | ||
334 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ | |
335 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
336 | }; | |
337 | ||
338 | struct mvneta_tx_queue { | |
339 | /* Number of this TX queue, in the range 0-7 */ | |
340 | u8 id; | |
341 | ||
342 | /* Number of TX DMA descriptors in the descriptor ring */ | |
343 | int size; | |
344 | ||
345 | /* Index of last TX DMA descriptor that was inserted */ | |
346 | int txq_put_index; | |
347 | ||
348 | /* Index of the TX DMA descriptor to be cleaned up */ | |
349 | int txq_get_index; | |
350 | ||
351 | /* Virtual address of the TX DMA descriptors array */ | |
352 | struct mvneta_tx_desc *descs; | |
353 | ||
354 | /* DMA address of the TX DMA descriptors array */ | |
355 | dma_addr_t descs_phys; | |
356 | ||
357 | /* Index of the last TX DMA descriptor */ | |
358 | int last_desc; | |
359 | ||
360 | /* Index of the next TX DMA descriptor to process */ | |
361 | int next_desc_to_proc; | |
362 | }; | |
363 | ||
364 | struct mvneta_rx_queue { | |
365 | /* rx queue number, in the range 0-7 */ | |
366 | u8 id; | |
367 | ||
368 | /* num of rx descriptors in the rx descriptor ring */ | |
369 | int size; | |
370 | ||
371 | /* Virtual address of the RX DMA descriptors array */ | |
372 | struct mvneta_rx_desc *descs; | |
373 | ||
374 | /* DMA address of the RX DMA descriptors array */ | |
375 | dma_addr_t descs_phys; | |
376 | ||
377 | /* Index of the last RX DMA descriptor */ | |
378 | int last_desc; | |
379 | ||
380 | /* Index of the next RX DMA descriptor to process */ | |
381 | int next_desc_to_proc; | |
382 | }; | |
383 | ||
384 | /* U-Boot doesn't use the queues, so set the number to 1 */ | |
385 | static int rxq_number = 1; | |
386 | static int txq_number = 1; | |
387 | static int rxq_def; | |
388 | ||
389 | struct buffer_location { | |
390 | struct mvneta_tx_desc *tx_descs; | |
391 | struct mvneta_rx_desc *rx_descs; | |
392 | u32 rx_buffers; | |
393 | }; | |
394 | ||
395 | /* | |
396 | * All 4 interfaces use the same global buffer, since only one interface | |
397 | * can be enabled at once | |
398 | */ | |
399 | static struct buffer_location buffer_loc; | |
400 | ||
401 | /* | |
402 | * Page table entries are set to 1MB, or multiples of 1MB | |
403 | * (not < 1MB). driver uses less bd's so use 1MB bdspace. | |
404 | */ | |
405 | #define BD_SPACE (1 << 20) | |
406 | ||
976feda2 KP |
407 | /* |
408 | * Dummy implementation that can be overwritten by a board | |
409 | * specific function | |
410 | */ | |
411 | __weak int board_network_enable(struct mii_dev *bus) | |
412 | { | |
413 | return 0; | |
414 | } | |
415 | ||
19fc2eae SR |
416 | /* Utility/helper methods */ |
417 | ||
418 | /* Write helper method */ | |
419 | static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) | |
420 | { | |
421 | writel(data, pp->base + offset); | |
422 | } | |
423 | ||
424 | /* Read helper method */ | |
425 | static u32 mvreg_read(struct mvneta_port *pp, u32 offset) | |
426 | { | |
427 | return readl(pp->base + offset); | |
428 | } | |
429 | ||
430 | /* Clear all MIB counters */ | |
431 | static void mvneta_mib_counters_clear(struct mvneta_port *pp) | |
432 | { | |
433 | int i; | |
434 | ||
435 | /* Perform dummy reads from MIB counters */ | |
436 | for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) | |
437 | mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); | |
438 | } | |
439 | ||
440 | /* Rx descriptors helper methods */ | |
441 | ||
442 | /* Checks whether the RX descriptor having this status is both the first | |
443 | * and the last descriptor for the RX packet. Each RX packet is currently | |
444 | * received through a single RX descriptor, so not having each RX | |
445 | * descriptor with its first and last bits set is an error | |
446 | */ | |
447 | static int mvneta_rxq_desc_is_first_last(u32 status) | |
448 | { | |
449 | return (status & MVNETA_RXD_FIRST_LAST_DESC) == | |
450 | MVNETA_RXD_FIRST_LAST_DESC; | |
451 | } | |
452 | ||
453 | /* Add number of descriptors ready to receive new packets */ | |
454 | static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, | |
455 | struct mvneta_rx_queue *rxq, | |
456 | int ndescs) | |
457 | { | |
458 | /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can | |
459 | * be added at once | |
460 | */ | |
461 | while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { | |
462 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
463 | (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << | |
464 | MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
465 | ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; | |
466 | } | |
467 | ||
468 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
469 | (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
470 | } | |
471 | ||
472 | /* Get number of RX descriptors occupied by received packets */ | |
473 | static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, | |
474 | struct mvneta_rx_queue *rxq) | |
475 | { | |
476 | u32 val; | |
477 | ||
478 | val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); | |
479 | return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; | |
480 | } | |
481 | ||
482 | /* Update num of rx desc called upon return from rx path or | |
483 | * from mvneta_rxq_drop_pkts(). | |
484 | */ | |
485 | static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, | |
486 | struct mvneta_rx_queue *rxq, | |
487 | int rx_done, int rx_filled) | |
488 | { | |
489 | u32 val; | |
490 | ||
491 | if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { | |
492 | val = rx_done | | |
493 | (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); | |
494 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
495 | return; | |
496 | } | |
497 | ||
498 | /* Only 255 descriptors can be added at once */ | |
499 | while ((rx_done > 0) || (rx_filled > 0)) { | |
500 | if (rx_done <= 0xff) { | |
501 | val = rx_done; | |
502 | rx_done = 0; | |
503 | } else { | |
504 | val = 0xff; | |
505 | rx_done -= 0xff; | |
506 | } | |
507 | if (rx_filled <= 0xff) { | |
508 | val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
509 | rx_filled = 0; | |
510 | } else { | |
511 | val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
512 | rx_filled -= 0xff; | |
513 | } | |
514 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
515 | } | |
516 | } | |
517 | ||
518 | /* Get pointer to next RX descriptor to be processed by SW */ | |
519 | static struct mvneta_rx_desc * | |
520 | mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) | |
521 | { | |
522 | int rx_desc = rxq->next_desc_to_proc; | |
523 | ||
524 | rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); | |
525 | return rxq->descs + rx_desc; | |
526 | } | |
527 | ||
528 | /* Tx descriptors helper methods */ | |
529 | ||
530 | /* Update HW with number of TX descriptors to be sent */ | |
531 | static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, | |
532 | struct mvneta_tx_queue *txq, | |
533 | int pend_desc) | |
534 | { | |
535 | u32 val; | |
536 | ||
537 | /* Only 255 descriptors can be added at once ; Assume caller | |
538 | * process TX desriptors in quanta less than 256 | |
539 | */ | |
540 | val = pend_desc; | |
541 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
542 | } | |
543 | ||
544 | /* Get pointer to next TX descriptor to be processed (send) by HW */ | |
545 | static struct mvneta_tx_desc * | |
546 | mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) | |
547 | { | |
548 | int tx_desc = txq->next_desc_to_proc; | |
549 | ||
550 | txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); | |
551 | return txq->descs + tx_desc; | |
552 | } | |
553 | ||
554 | /* Set rxq buf size */ | |
555 | static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, | |
556 | struct mvneta_rx_queue *rxq, | |
557 | int buf_size) | |
558 | { | |
559 | u32 val; | |
560 | ||
561 | val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); | |
562 | ||
563 | val &= ~MVNETA_RXQ_BUF_SIZE_MASK; | |
564 | val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); | |
565 | ||
566 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); | |
567 | } | |
568 | ||
569 | /* Start the Ethernet port RX and TX activity */ | |
570 | static void mvneta_port_up(struct mvneta_port *pp) | |
571 | { | |
572 | int queue; | |
573 | u32 q_map; | |
574 | ||
575 | /* Enable all initialized TXs. */ | |
576 | mvneta_mib_counters_clear(pp); | |
577 | q_map = 0; | |
578 | for (queue = 0; queue < txq_number; queue++) { | |
579 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
580 | if (txq->descs != NULL) | |
581 | q_map |= (1 << queue); | |
582 | } | |
583 | mvreg_write(pp, MVNETA_TXQ_CMD, q_map); | |
584 | ||
585 | /* Enable all initialized RXQs. */ | |
586 | q_map = 0; | |
587 | for (queue = 0; queue < rxq_number; queue++) { | |
588 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
589 | if (rxq->descs != NULL) | |
590 | q_map |= (1 << queue); | |
591 | } | |
592 | mvreg_write(pp, MVNETA_RXQ_CMD, q_map); | |
593 | } | |
594 | ||
595 | /* Stop the Ethernet port activity */ | |
596 | static void mvneta_port_down(struct mvneta_port *pp) | |
597 | { | |
598 | u32 val; | |
599 | int count; | |
600 | ||
601 | /* Stop Rx port activity. Check port Rx activity. */ | |
602 | val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; | |
603 | ||
604 | /* Issue stop command for active channels only */ | |
605 | if (val != 0) | |
606 | mvreg_write(pp, MVNETA_RXQ_CMD, | |
607 | val << MVNETA_RXQ_DISABLE_SHIFT); | |
608 | ||
609 | /* Wait for all Rx activity to terminate. */ | |
610 | count = 0; | |
611 | do { | |
612 | if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { | |
613 | netdev_warn(pp->dev, | |
614 | "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", | |
615 | val); | |
616 | break; | |
617 | } | |
618 | mdelay(1); | |
619 | ||
620 | val = mvreg_read(pp, MVNETA_RXQ_CMD); | |
621 | } while (val & 0xff); | |
622 | ||
623 | /* Stop Tx port activity. Check port Tx activity. Issue stop | |
624 | * command for active channels only | |
625 | */ | |
626 | val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; | |
627 | ||
628 | if (val != 0) | |
629 | mvreg_write(pp, MVNETA_TXQ_CMD, | |
630 | (val << MVNETA_TXQ_DISABLE_SHIFT)); | |
631 | ||
632 | /* Wait for all Tx activity to terminate. */ | |
633 | count = 0; | |
634 | do { | |
635 | if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { | |
636 | netdev_warn(pp->dev, | |
637 | "TIMEOUT for TX stopped status=0x%08x\n", | |
638 | val); | |
639 | break; | |
640 | } | |
641 | mdelay(1); | |
642 | ||
643 | /* Check TX Command reg that all Txqs are stopped */ | |
644 | val = mvreg_read(pp, MVNETA_TXQ_CMD); | |
645 | ||
646 | } while (val & 0xff); | |
647 | ||
648 | /* Double check to verify that TX FIFO is empty */ | |
649 | count = 0; | |
650 | do { | |
651 | if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { | |
652 | netdev_warn(pp->dev, | |
653 | "TX FIFO empty timeout status=0x08%x\n", | |
654 | val); | |
655 | break; | |
656 | } | |
657 | mdelay(1); | |
658 | ||
659 | val = mvreg_read(pp, MVNETA_PORT_STATUS); | |
660 | } while (!(val & MVNETA_TX_FIFO_EMPTY) && | |
661 | (val & MVNETA_TX_IN_PRGRS)); | |
662 | ||
663 | udelay(200); | |
664 | } | |
665 | ||
666 | /* Enable the port by setting the port enable bit of the MAC control register */ | |
667 | static void mvneta_port_enable(struct mvneta_port *pp) | |
668 | { | |
669 | u32 val; | |
670 | ||
671 | /* Enable port */ | |
672 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
673 | val |= MVNETA_GMAC0_PORT_ENABLE; | |
674 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
675 | } | |
676 | ||
677 | /* Disable the port and wait for about 200 usec before retuning */ | |
678 | static void mvneta_port_disable(struct mvneta_port *pp) | |
679 | { | |
680 | u32 val; | |
681 | ||
682 | /* Reset the Enable bit in the Serial Control Register */ | |
683 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
684 | val &= ~MVNETA_GMAC0_PORT_ENABLE; | |
685 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
686 | ||
687 | udelay(200); | |
688 | } | |
689 | ||
690 | /* Multicast tables methods */ | |
691 | ||
692 | /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ | |
693 | static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) | |
694 | { | |
695 | int offset; | |
696 | u32 val; | |
697 | ||
698 | if (queue == -1) { | |
699 | val = 0; | |
700 | } else { | |
701 | val = 0x1 | (queue << 1); | |
702 | val |= (val << 24) | (val << 16) | (val << 8); | |
703 | } | |
704 | ||
705 | for (offset = 0; offset <= 0xc; offset += 4) | |
706 | mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); | |
707 | } | |
708 | ||
709 | /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ | |
710 | static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) | |
711 | { | |
712 | int offset; | |
713 | u32 val; | |
714 | ||
715 | if (queue == -1) { | |
716 | val = 0; | |
717 | } else { | |
718 | val = 0x1 | (queue << 1); | |
719 | val |= (val << 24) | (val << 16) | (val << 8); | |
720 | } | |
721 | ||
722 | for (offset = 0; offset <= 0xfc; offset += 4) | |
723 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); | |
724 | } | |
725 | ||
726 | /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ | |
727 | static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) | |
728 | { | |
729 | int offset; | |
730 | u32 val; | |
731 | ||
732 | if (queue == -1) { | |
733 | memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); | |
734 | val = 0; | |
735 | } else { | |
736 | memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); | |
737 | val = 0x1 | (queue << 1); | |
738 | val |= (val << 24) | (val << 16) | (val << 8); | |
739 | } | |
740 | ||
741 | for (offset = 0; offset <= 0xfc; offset += 4) | |
742 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); | |
743 | } | |
744 | ||
745 | /* This method sets defaults to the NETA port: | |
746 | * Clears interrupt Cause and Mask registers. | |
747 | * Clears all MAC tables. | |
748 | * Sets defaults to all registers. | |
749 | * Resets RX and TX descriptor rings. | |
750 | * Resets PHY. | |
751 | * This method can be called after mvneta_port_down() to return the port | |
752 | * settings to defaults. | |
753 | */ | |
754 | static void mvneta_defaults_set(struct mvneta_port *pp) | |
755 | { | |
756 | int cpu; | |
757 | int queue; | |
758 | u32 val; | |
759 | ||
760 | /* Clear all Cause registers */ | |
761 | mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); | |
762 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); | |
763 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
764 | ||
765 | /* Mask all interrupts */ | |
766 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
767 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
768 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
769 | mvreg_write(pp, MVNETA_INTR_ENABLE, 0); | |
770 | ||
771 | /* Enable MBUS Retry bit16 */ | |
772 | mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); | |
773 | ||
774 | /* Set CPU queue access map - all CPUs have access to all RX | |
775 | * queues and to all TX queues | |
776 | */ | |
777 | for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) | |
778 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), | |
779 | (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | | |
780 | MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); | |
781 | ||
782 | /* Reset RX and TX DMAs */ | |
783 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
784 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
785 | ||
786 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
787 | mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); | |
788 | for (queue = 0; queue < txq_number; queue++) { | |
789 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); | |
790 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); | |
791 | } | |
792 | ||
793 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
794 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
795 | ||
796 | /* Set Port Acceleration Mode */ | |
797 | val = MVNETA_ACC_MODE_EXT; | |
798 | mvreg_write(pp, MVNETA_ACC_MODE, val); | |
799 | ||
800 | /* Update val of portCfg register accordingly with all RxQueue types */ | |
801 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); | |
802 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); | |
803 | ||
804 | val = 0; | |
805 | mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); | |
806 | mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); | |
807 | ||
808 | /* Build PORT_SDMA_CONFIG_REG */ | |
809 | val = 0; | |
810 | ||
811 | /* Default burst size */ | |
812 | val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
813 | val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
814 | val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; | |
815 | ||
816 | /* Assign port SDMA configuration */ | |
817 | mvreg_write(pp, MVNETA_SDMA_CONFIG, val); | |
818 | ||
819 | /* Enable PHY polling in hardware for U-Boot */ | |
820 | val = mvreg_read(pp, MVNETA_UNIT_CONTROL); | |
821 | val |= MVNETA_PHY_POLLING_ENABLE; | |
822 | mvreg_write(pp, MVNETA_UNIT_CONTROL, val); | |
823 | ||
824 | mvneta_set_ucast_table(pp, -1); | |
825 | mvneta_set_special_mcast_table(pp, -1); | |
826 | mvneta_set_other_mcast_table(pp, -1); | |
827 | } | |
828 | ||
829 | /* Set unicast address */ | |
830 | static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, | |
831 | int queue) | |
832 | { | |
833 | unsigned int unicast_reg; | |
834 | unsigned int tbl_offset; | |
835 | unsigned int reg_offset; | |
836 | ||
837 | /* Locate the Unicast table entry */ | |
838 | last_nibble = (0xf & last_nibble); | |
839 | ||
840 | /* offset from unicast tbl base */ | |
841 | tbl_offset = (last_nibble / 4) * 4; | |
842 | ||
843 | /* offset within the above reg */ | |
844 | reg_offset = last_nibble % 4; | |
845 | ||
846 | unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); | |
847 | ||
848 | if (queue == -1) { | |
849 | /* Clear accepts frame bit at specified unicast DA tbl entry */ | |
850 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
851 | } else { | |
852 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
853 | unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
854 | } | |
855 | ||
856 | mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); | |
857 | } | |
858 | ||
859 | /* Set mac address */ | |
860 | static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, | |
861 | int queue) | |
862 | { | |
863 | unsigned int mac_h; | |
864 | unsigned int mac_l; | |
865 | ||
866 | if (queue != -1) { | |
867 | mac_l = (addr[4] << 8) | (addr[5]); | |
868 | mac_h = (addr[0] << 24) | (addr[1] << 16) | | |
869 | (addr[2] << 8) | (addr[3] << 0); | |
870 | ||
871 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); | |
872 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); | |
873 | } | |
874 | ||
875 | /* Accept frames of this address */ | |
876 | mvneta_set_ucast_addr(pp, addr[5], queue); | |
877 | } | |
878 | ||
879 | /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ | |
880 | static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, | |
881 | u32 phys_addr, u32 cookie) | |
882 | { | |
883 | rx_desc->buf_cookie = cookie; | |
884 | rx_desc->buf_phys_addr = phys_addr; | |
885 | } | |
886 | ||
887 | /* Decrement sent descriptors counter */ | |
888 | static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, | |
889 | struct mvneta_tx_queue *txq, | |
890 | int sent_desc) | |
891 | { | |
892 | u32 val; | |
893 | ||
894 | /* Only 255 TX descriptors can be updated at once */ | |
895 | while (sent_desc > 0xff) { | |
896 | val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; | |
897 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
898 | sent_desc = sent_desc - 0xff; | |
899 | } | |
900 | ||
901 | val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; | |
902 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
903 | } | |
904 | ||
905 | /* Get number of TX descriptors already sent by HW */ | |
906 | static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, | |
907 | struct mvneta_tx_queue *txq) | |
908 | { | |
909 | u32 val; | |
910 | int sent_desc; | |
911 | ||
912 | val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); | |
913 | sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> | |
914 | MVNETA_TXQ_SENT_DESC_SHIFT; | |
915 | ||
916 | return sent_desc; | |
917 | } | |
918 | ||
919 | /* Display more error info */ | |
920 | static void mvneta_rx_error(struct mvneta_port *pp, | |
921 | struct mvneta_rx_desc *rx_desc) | |
922 | { | |
923 | u32 status = rx_desc->status; | |
924 | ||
925 | if (!mvneta_rxq_desc_is_first_last(status)) { | |
926 | netdev_err(pp->dev, | |
927 | "bad rx status %08x (buffer oversize), size=%d\n", | |
928 | status, rx_desc->data_size); | |
929 | return; | |
930 | } | |
931 | ||
932 | switch (status & MVNETA_RXD_ERR_CODE_MASK) { | |
933 | case MVNETA_RXD_ERR_CRC: | |
934 | netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", | |
935 | status, rx_desc->data_size); | |
936 | break; | |
937 | case MVNETA_RXD_ERR_OVERRUN: | |
938 | netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", | |
939 | status, rx_desc->data_size); | |
940 | break; | |
941 | case MVNETA_RXD_ERR_LEN: | |
942 | netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", | |
943 | status, rx_desc->data_size); | |
944 | break; | |
945 | case MVNETA_RXD_ERR_RESOURCE: | |
946 | netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", | |
947 | status, rx_desc->data_size); | |
948 | break; | |
949 | } | |
950 | } | |
951 | ||
952 | static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp, | |
953 | int rxq) | |
954 | { | |
955 | return &pp->rxqs[rxq]; | |
956 | } | |
957 | ||
958 | ||
959 | /* Drop packets received by the RXQ and free buffers */ | |
960 | static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, | |
961 | struct mvneta_rx_queue *rxq) | |
962 | { | |
963 | int rx_done; | |
964 | ||
965 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
966 | if (rx_done) | |
967 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); | |
968 | } | |
969 | ||
970 | /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ | |
971 | static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
972 | int num) | |
973 | { | |
974 | int i; | |
975 | ||
976 | for (i = 0; i < num; i++) { | |
977 | u32 addr; | |
978 | ||
979 | /* U-Boot special: Fill in the rx buffer addresses */ | |
980 | addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE); | |
981 | mvneta_rx_desc_fill(rxq->descs + i, addr, addr); | |
982 | } | |
983 | ||
984 | /* Add this number of RX descriptors as non occupied (ready to | |
985 | * get packets) | |
986 | */ | |
987 | mvneta_rxq_non_occup_desc_add(pp, rxq, i); | |
988 | ||
989 | return 0; | |
990 | } | |
991 | ||
992 | /* Rx/Tx queue initialization/cleanup methods */ | |
993 | ||
994 | /* Create a specified RX queue */ | |
995 | static int mvneta_rxq_init(struct mvneta_port *pp, | |
996 | struct mvneta_rx_queue *rxq) | |
997 | ||
998 | { | |
999 | rxq->size = pp->rx_ring_size; | |
1000 | ||
1001 | /* Allocate memory for RX descriptors */ | |
1002 | rxq->descs_phys = (dma_addr_t)rxq->descs; | |
1003 | if (rxq->descs == NULL) | |
1004 | return -ENOMEM; | |
1005 | ||
1006 | rxq->last_desc = rxq->size - 1; | |
1007 | ||
1008 | /* Set Rx descriptors queue starting address */ | |
1009 | mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); | |
1010 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); | |
1011 | ||
1012 | /* Fill RXQ with buffers from RX pool */ | |
1013 | mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE); | |
1014 | mvneta_rxq_fill(pp, rxq, rxq->size); | |
1015 | ||
1016 | return 0; | |
1017 | } | |
1018 | ||
1019 | /* Cleanup Rx queue */ | |
1020 | static void mvneta_rxq_deinit(struct mvneta_port *pp, | |
1021 | struct mvneta_rx_queue *rxq) | |
1022 | { | |
1023 | mvneta_rxq_drop_pkts(pp, rxq); | |
1024 | ||
1025 | rxq->descs = NULL; | |
1026 | rxq->last_desc = 0; | |
1027 | rxq->next_desc_to_proc = 0; | |
1028 | rxq->descs_phys = 0; | |
1029 | } | |
1030 | ||
1031 | /* Create and initialize a tx queue */ | |
1032 | static int mvneta_txq_init(struct mvneta_port *pp, | |
1033 | struct mvneta_tx_queue *txq) | |
1034 | { | |
1035 | txq->size = pp->tx_ring_size; | |
1036 | ||
1037 | /* Allocate memory for TX descriptors */ | |
3cbc11da | 1038 | txq->descs_phys = (dma_addr_t)txq->descs; |
19fc2eae SR |
1039 | if (txq->descs == NULL) |
1040 | return -ENOMEM; | |
1041 | ||
1042 | txq->last_desc = txq->size - 1; | |
1043 | ||
1044 | /* Set maximum bandwidth for enabled TXQs */ | |
1045 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); | |
1046 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); | |
1047 | ||
1048 | /* Set Tx descriptors queue starting address */ | |
1049 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); | |
1050 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); | |
1051 | ||
1052 | return 0; | |
1053 | } | |
1054 | ||
1055 | /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ | |
1056 | static void mvneta_txq_deinit(struct mvneta_port *pp, | |
1057 | struct mvneta_tx_queue *txq) | |
1058 | { | |
1059 | txq->descs = NULL; | |
1060 | txq->last_desc = 0; | |
1061 | txq->next_desc_to_proc = 0; | |
1062 | txq->descs_phys = 0; | |
1063 | ||
1064 | /* Set minimum bandwidth for disabled TXQs */ | |
1065 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); | |
1066 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); | |
1067 | ||
1068 | /* Set Tx descriptors queue starting address and size */ | |
1069 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); | |
1070 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); | |
1071 | } | |
1072 | ||
1073 | /* Cleanup all Tx queues */ | |
1074 | static void mvneta_cleanup_txqs(struct mvneta_port *pp) | |
1075 | { | |
1076 | int queue; | |
1077 | ||
1078 | for (queue = 0; queue < txq_number; queue++) | |
1079 | mvneta_txq_deinit(pp, &pp->txqs[queue]); | |
1080 | } | |
1081 | ||
1082 | /* Cleanup all Rx queues */ | |
1083 | static void mvneta_cleanup_rxqs(struct mvneta_port *pp) | |
1084 | { | |
1085 | int queue; | |
1086 | ||
1087 | for (queue = 0; queue < rxq_number; queue++) | |
1088 | mvneta_rxq_deinit(pp, &pp->rxqs[queue]); | |
1089 | } | |
1090 | ||
1091 | ||
1092 | /* Init all Rx queues */ | |
1093 | static int mvneta_setup_rxqs(struct mvneta_port *pp) | |
1094 | { | |
1095 | int queue; | |
1096 | ||
1097 | for (queue = 0; queue < rxq_number; queue++) { | |
1098 | int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); | |
1099 | if (err) { | |
1100 | netdev_err(pp->dev, "%s: can't create rxq=%d\n", | |
1101 | __func__, queue); | |
1102 | mvneta_cleanup_rxqs(pp); | |
1103 | return err; | |
1104 | } | |
1105 | } | |
1106 | ||
1107 | return 0; | |
1108 | } | |
1109 | ||
1110 | /* Init all tx queues */ | |
1111 | static int mvneta_setup_txqs(struct mvneta_port *pp) | |
1112 | { | |
1113 | int queue; | |
1114 | ||
1115 | for (queue = 0; queue < txq_number; queue++) { | |
1116 | int err = mvneta_txq_init(pp, &pp->txqs[queue]); | |
1117 | if (err) { | |
1118 | netdev_err(pp->dev, "%s: can't create txq=%d\n", | |
1119 | __func__, queue); | |
1120 | mvneta_cleanup_txqs(pp); | |
1121 | return err; | |
1122 | } | |
1123 | } | |
1124 | ||
1125 | return 0; | |
1126 | } | |
1127 | ||
1128 | static void mvneta_start_dev(struct mvneta_port *pp) | |
1129 | { | |
1130 | /* start the Rx/Tx activity */ | |
1131 | mvneta_port_enable(pp); | |
1132 | } | |
1133 | ||
e3b9c98a | 1134 | static void mvneta_adjust_link(struct udevice *dev) |
19fc2eae | 1135 | { |
e3b9c98a | 1136 | struct mvneta_port *pp = dev_get_priv(dev); |
19fc2eae SR |
1137 | struct phy_device *phydev = pp->phydev; |
1138 | int status_change = 0; | |
1139 | ||
1140 | if (phydev->link) { | |
1141 | if ((pp->speed != phydev->speed) || | |
1142 | (pp->duplex != phydev->duplex)) { | |
1143 | u32 val; | |
1144 | ||
1145 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
1146 | val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | | |
1147 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
1148 | MVNETA_GMAC_CONFIG_FULL_DUPLEX | | |
1149 | MVNETA_GMAC_AN_SPEED_EN | | |
1150 | MVNETA_GMAC_AN_DUPLEX_EN); | |
1151 | ||
1152 | if (phydev->duplex) | |
1153 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
1154 | ||
1155 | if (phydev->speed == SPEED_1000) | |
1156 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; | |
1157 | else | |
1158 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; | |
1159 | ||
1160 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
1161 | ||
1162 | pp->duplex = phydev->duplex; | |
1163 | pp->speed = phydev->speed; | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | if (phydev->link != pp->link) { | |
1168 | if (!phydev->link) { | |
1169 | pp->duplex = -1; | |
1170 | pp->speed = 0; | |
1171 | } | |
1172 | ||
1173 | pp->link = phydev->link; | |
1174 | status_change = 1; | |
1175 | } | |
1176 | ||
1177 | if (status_change) { | |
1178 | if (phydev->link) { | |
1179 | u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
1180 | val |= (MVNETA_GMAC_FORCE_LINK_PASS | | |
1181 | MVNETA_GMAC_FORCE_LINK_DOWN); | |
1182 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
1183 | mvneta_port_up(pp); | |
1184 | } else { | |
1185 | mvneta_port_down(pp); | |
1186 | } | |
1187 | } | |
1188 | } | |
1189 | ||
e3b9c98a | 1190 | static int mvneta_open(struct udevice *dev) |
19fc2eae | 1191 | { |
e3b9c98a | 1192 | struct mvneta_port *pp = dev_get_priv(dev); |
19fc2eae SR |
1193 | int ret; |
1194 | ||
1195 | ret = mvneta_setup_rxqs(pp); | |
1196 | if (ret) | |
1197 | return ret; | |
1198 | ||
1199 | ret = mvneta_setup_txqs(pp); | |
1200 | if (ret) | |
1201 | return ret; | |
1202 | ||
1203 | mvneta_adjust_link(dev); | |
1204 | ||
1205 | mvneta_start_dev(pp); | |
1206 | ||
1207 | return 0; | |
1208 | } | |
1209 | ||
1210 | /* Initialize hw */ | |
e3b9c98a | 1211 | static int mvneta_init2(struct mvneta_port *pp) |
19fc2eae SR |
1212 | { |
1213 | int queue; | |
1214 | ||
1215 | /* Disable port */ | |
1216 | mvneta_port_disable(pp); | |
1217 | ||
1218 | /* Set port default values */ | |
1219 | mvneta_defaults_set(pp); | |
1220 | ||
1221 | pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue), | |
1222 | GFP_KERNEL); | |
1223 | if (!pp->txqs) | |
1224 | return -ENOMEM; | |
1225 | ||
1226 | /* U-Boot special: use preallocated area */ | |
1227 | pp->txqs[0].descs = buffer_loc.tx_descs; | |
1228 | ||
1229 | /* Initialize TX descriptor rings */ | |
1230 | for (queue = 0; queue < txq_number; queue++) { | |
1231 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
1232 | txq->id = queue; | |
1233 | txq->size = pp->tx_ring_size; | |
1234 | } | |
1235 | ||
1236 | pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue), | |
1237 | GFP_KERNEL); | |
1238 | if (!pp->rxqs) { | |
1239 | kfree(pp->txqs); | |
1240 | return -ENOMEM; | |
1241 | } | |
1242 | ||
1243 | /* U-Boot special: use preallocated area */ | |
1244 | pp->rxqs[0].descs = buffer_loc.rx_descs; | |
1245 | ||
1246 | /* Create Rx descriptor rings */ | |
1247 | for (queue = 0; queue < rxq_number; queue++) { | |
1248 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
1249 | rxq->id = queue; | |
1250 | rxq->size = pp->rx_ring_size; | |
1251 | } | |
1252 | ||
1253 | return 0; | |
1254 | } | |
1255 | ||
1256 | /* platform glue : initialize decoding windows */ | |
544eefe0 SR |
1257 | |
1258 | /* | |
1259 | * Not like A380, in Armada3700, there are two layers of decode windows for GBE: | |
1260 | * First layer is: GbE Address window that resides inside the GBE unit, | |
1261 | * Second layer is: Fabric address window which is located in the NIC400 | |
1262 | * (South Fabric). | |
1263 | * To simplify the address decode configuration for Armada3700, we bypass the | |
1264 | * first layer of GBE decode window by setting the first window to 4GB. | |
1265 | */ | |
1266 | static void mvneta_bypass_mbus_windows(struct mvneta_port *pp) | |
1267 | { | |
1268 | /* | |
1269 | * Set window size to 4GB, to bypass GBE address decode, leave the | |
1270 | * work to MBUS decode window | |
1271 | */ | |
1272 | mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK); | |
1273 | ||
1274 | /* Enable GBE address decode window 0 by set bit 0 to 0 */ | |
1275 | clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE, | |
1276 | MVNETA_BASE_ADDR_ENABLE_BIT); | |
1277 | ||
1278 | /* Set GBE address decode window 0 to full Access (read or write) */ | |
1279 | setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT, | |
1280 | MVNETA_PORT_ACCESS_PROTECT_WIN0_RW); | |
1281 | } | |
1282 | ||
19fc2eae SR |
1283 | static void mvneta_conf_mbus_windows(struct mvneta_port *pp) |
1284 | { | |
1285 | const struct mbus_dram_target_info *dram; | |
1286 | u32 win_enable; | |
1287 | u32 win_protect; | |
1288 | int i; | |
1289 | ||
1290 | dram = mvebu_mbus_dram_info(); | |
1291 | for (i = 0; i < 6; i++) { | |
1292 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
1293 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
1294 | ||
1295 | if (i < 4) | |
1296 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
1297 | } | |
1298 | ||
1299 | win_enable = 0x3f; | |
1300 | win_protect = 0; | |
1301 | ||
1302 | for (i = 0; i < dram->num_cs; i++) { | |
1303 | const struct mbus_dram_window *cs = dram->cs + i; | |
1304 | mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | | |
1305 | (cs->mbus_attr << 8) | dram->mbus_dram_target_id); | |
1306 | ||
1307 | mvreg_write(pp, MVNETA_WIN_SIZE(i), | |
1308 | (cs->size - 1) & 0xffff0000); | |
1309 | ||
1310 | win_enable &= ~(1 << i); | |
1311 | win_protect |= 3 << (2 * i); | |
1312 | } | |
1313 | ||
1314 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
1315 | } | |
1316 | ||
1317 | /* Power up the port */ | |
1318 | static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) | |
1319 | { | |
1320 | u32 ctrl; | |
1321 | ||
1322 | /* MAC Cause register should be cleared */ | |
1323 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); | |
1324 | ||
1325 | ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | |
1326 | ||
1327 | /* Even though it might look weird, when we're configured in | |
1328 | * SGMII or QSGMII mode, the RGMII bit needs to be set. | |
1329 | */ | |
1330 | switch (phy_mode) { | |
1331 | case PHY_INTERFACE_MODE_QSGMII: | |
1332 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); | |
1333 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; | |
1334 | break; | |
1335 | case PHY_INTERFACE_MODE_SGMII: | |
1336 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); | |
1337 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; | |
1338 | break; | |
1339 | case PHY_INTERFACE_MODE_RGMII: | |
1340 | case PHY_INTERFACE_MODE_RGMII_ID: | |
1341 | ctrl |= MVNETA_GMAC2_PORT_RGMII; | |
1342 | break; | |
1343 | default: | |
1344 | return -EINVAL; | |
1345 | } | |
1346 | ||
1347 | /* Cancel Port Reset */ | |
1348 | ctrl &= ~MVNETA_GMAC2_PORT_RESET; | |
1349 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); | |
1350 | ||
1351 | while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & | |
1352 | MVNETA_GMAC2_PORT_RESET) != 0) | |
1353 | continue; | |
1354 | ||
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | /* Device initialization routine */ | |
e3b9c98a | 1359 | static int mvneta_init(struct udevice *dev) |
19fc2eae | 1360 | { |
e3b9c98a SR |
1361 | struct eth_pdata *pdata = dev_get_platdata(dev); |
1362 | struct mvneta_port *pp = dev_get_priv(dev); | |
19fc2eae SR |
1363 | int err; |
1364 | ||
1365 | pp->tx_ring_size = MVNETA_MAX_TXD; | |
1366 | pp->rx_ring_size = MVNETA_MAX_RXD; | |
1367 | ||
e3b9c98a | 1368 | err = mvneta_init2(pp); |
19fc2eae SR |
1369 | if (err < 0) { |
1370 | dev_err(&pdev->dev, "can't init eth hal\n"); | |
1371 | return err; | |
1372 | } | |
1373 | ||
e3b9c98a | 1374 | mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def); |
19fc2eae SR |
1375 | |
1376 | err = mvneta_port_power_up(pp, pp->phy_interface); | |
1377 | if (err < 0) { | |
1378 | dev_err(&pdev->dev, "can't power up port\n"); | |
1379 | return err; | |
1380 | } | |
1381 | ||
1382 | /* Call open() now as it needs to be done before runing send() */ | |
1383 | mvneta_open(dev); | |
1384 | ||
1385 | return 0; | |
1386 | } | |
1387 | ||
1388 | /* U-Boot only functions follow here */ | |
1389 | ||
1390 | /* SMI / MDIO functions */ | |
1391 | ||
1392 | static int smi_wait_ready(struct mvneta_port *pp) | |
1393 | { | |
1394 | u32 timeout = MVNETA_SMI_TIMEOUT; | |
1395 | u32 smi_reg; | |
1396 | ||
1397 | /* wait till the SMI is not busy */ | |
1398 | do { | |
1399 | /* read smi register */ | |
1400 | smi_reg = mvreg_read(pp, MVNETA_SMI); | |
1401 | if (timeout-- == 0) { | |
1402 | printf("Error: SMI busy timeout\n"); | |
1403 | return -EFAULT; | |
1404 | } | |
1405 | } while (smi_reg & MVNETA_SMI_BUSY); | |
1406 | ||
1407 | return 0; | |
1408 | } | |
1409 | ||
1410 | /* | |
e3b9c98a | 1411 | * mvneta_mdio_read - miiphy_read callback function. |
19fc2eae SR |
1412 | * |
1413 | * Returns 16bit phy register value, or 0xffff on error | |
1414 | */ | |
e3b9c98a | 1415 | static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) |
19fc2eae | 1416 | { |
e3b9c98a | 1417 | struct mvneta_port *pp = bus->priv; |
19fc2eae SR |
1418 | u32 smi_reg; |
1419 | u32 timeout; | |
1420 | ||
1421 | /* check parameters */ | |
e3b9c98a SR |
1422 | if (addr > MVNETA_PHY_ADDR_MASK) { |
1423 | printf("Error: Invalid PHY address %d\n", addr); | |
19fc2eae SR |
1424 | return -EFAULT; |
1425 | } | |
1426 | ||
e3b9c98a SR |
1427 | if (reg > MVNETA_PHY_REG_MASK) { |
1428 | printf("Err: Invalid register offset %d\n", reg); | |
19fc2eae SR |
1429 | return -EFAULT; |
1430 | } | |
1431 | ||
1432 | /* wait till the SMI is not busy */ | |
1433 | if (smi_wait_ready(pp) < 0) | |
1434 | return -EFAULT; | |
1435 | ||
1436 | /* fill the phy address and regiser offset and read opcode */ | |
e3b9c98a SR |
1437 | smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS) |
1438 | | (reg << MVNETA_SMI_REG_ADDR_OFFS) | |
19fc2eae SR |
1439 | | MVNETA_SMI_OPCODE_READ; |
1440 | ||
1441 | /* write the smi register */ | |
1442 | mvreg_write(pp, MVNETA_SMI, smi_reg); | |
1443 | ||
e3b9c98a | 1444 | /* wait till read value is ready */ |
19fc2eae SR |
1445 | timeout = MVNETA_SMI_TIMEOUT; |
1446 | ||
1447 | do { | |
1448 | /* read smi register */ | |
1449 | smi_reg = mvreg_read(pp, MVNETA_SMI); | |
1450 | if (timeout-- == 0) { | |
1451 | printf("Err: SMI read ready timeout\n"); | |
1452 | return -EFAULT; | |
1453 | } | |
1454 | } while (!(smi_reg & MVNETA_SMI_READ_VALID)); | |
1455 | ||
1456 | /* Wait for the data to update in the SMI register */ | |
1457 | for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++) | |
1458 | ; | |
1459 | ||
e3b9c98a | 1460 | return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK; |
19fc2eae SR |
1461 | } |
1462 | ||
1463 | /* | |
e3b9c98a | 1464 | * mvneta_mdio_write - miiphy_write callback function. |
19fc2eae SR |
1465 | * |
1466 | * Returns 0 if write succeed, -EINVAL on bad parameters | |
1467 | * -ETIME on timeout | |
1468 | */ | |
e3b9c98a SR |
1469 | static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, |
1470 | u16 value) | |
19fc2eae | 1471 | { |
e3b9c98a | 1472 | struct mvneta_port *pp = bus->priv; |
19fc2eae SR |
1473 | u32 smi_reg; |
1474 | ||
1475 | /* check parameters */ | |
e3b9c98a SR |
1476 | if (addr > MVNETA_PHY_ADDR_MASK) { |
1477 | printf("Error: Invalid PHY address %d\n", addr); | |
19fc2eae SR |
1478 | return -EFAULT; |
1479 | } | |
1480 | ||
e3b9c98a SR |
1481 | if (reg > MVNETA_PHY_REG_MASK) { |
1482 | printf("Err: Invalid register offset %d\n", reg); | |
19fc2eae SR |
1483 | return -EFAULT; |
1484 | } | |
1485 | ||
1486 | /* wait till the SMI is not busy */ | |
1487 | if (smi_wait_ready(pp) < 0) | |
1488 | return -EFAULT; | |
1489 | ||
1490 | /* fill the phy addr and reg offset and write opcode and data */ | |
e3b9c98a SR |
1491 | smi_reg = value << MVNETA_SMI_DATA_OFFS; |
1492 | smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS) | |
1493 | | (reg << MVNETA_SMI_REG_ADDR_OFFS); | |
19fc2eae SR |
1494 | smi_reg &= ~MVNETA_SMI_OPCODE_READ; |
1495 | ||
1496 | /* write the smi register */ | |
1497 | mvreg_write(pp, MVNETA_SMI, smi_reg); | |
1498 | ||
1499 | return 0; | |
1500 | } | |
1501 | ||
e3b9c98a | 1502 | static int mvneta_start(struct udevice *dev) |
19fc2eae | 1503 | { |
e3b9c98a | 1504 | struct mvneta_port *pp = dev_get_priv(dev); |
19fc2eae SR |
1505 | struct phy_device *phydev; |
1506 | ||
1507 | mvneta_port_power_up(pp, pp->phy_interface); | |
1508 | ||
1509 | if (!pp->init || pp->link == 0) { | |
1510 | /* Set phy address of the port */ | |
1511 | mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr); | |
1512 | phydev = phy_connect(pp->bus, pp->phyaddr, dev, | |
1513 | pp->phy_interface); | |
1514 | ||
1515 | pp->phydev = phydev; | |
1516 | phy_config(phydev); | |
1517 | phy_startup(phydev); | |
1518 | if (!phydev->link) { | |
1519 | printf("%s: No link.\n", phydev->dev->name); | |
1520 | return -1; | |
1521 | } | |
1522 | ||
1523 | /* Full init on first call */ | |
e3b9c98a | 1524 | mvneta_init(dev); |
19fc2eae SR |
1525 | pp->init = 1; |
1526 | } else { | |
1527 | /* Upon all following calls, this is enough */ | |
1528 | mvneta_port_up(pp); | |
1529 | mvneta_port_enable(pp); | |
1530 | } | |
1531 | ||
1532 | return 0; | |
1533 | } | |
1534 | ||
e3b9c98a | 1535 | static int mvneta_send(struct udevice *dev, void *packet, int length) |
19fc2eae | 1536 | { |
e3b9c98a | 1537 | struct mvneta_port *pp = dev_get_priv(dev); |
19fc2eae SR |
1538 | struct mvneta_tx_queue *txq = &pp->txqs[0]; |
1539 | struct mvneta_tx_desc *tx_desc; | |
1540 | int sent_desc; | |
1541 | u32 timeout = 0; | |
1542 | ||
1543 | /* Get a descriptor for the first part of the packet */ | |
1544 | tx_desc = mvneta_txq_next_desc_get(txq); | |
1545 | ||
3cbc11da | 1546 | tx_desc->buf_phys_addr = (u32)(uintptr_t)packet; |
e3b9c98a | 1547 | tx_desc->data_size = length; |
3cbc11da SR |
1548 | flush_dcache_range((ulong)packet, |
1549 | (ulong)packet + ALIGN(length, PKTALIGN)); | |
19fc2eae SR |
1550 | |
1551 | /* First and Last descriptor */ | |
1552 | tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC; | |
1553 | mvneta_txq_pend_desc_add(pp, txq, 1); | |
1554 | ||
1555 | /* Wait for packet to be sent (queue might help with speed here) */ | |
1556 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); | |
1557 | while (!sent_desc) { | |
1558 | if (timeout++ > 10000) { | |
1559 | printf("timeout: packet not sent\n"); | |
1560 | return -1; | |
1561 | } | |
1562 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); | |
1563 | } | |
1564 | ||
1565 | /* txDone has increased - hw sent packet */ | |
1566 | mvneta_txq_sent_desc_dec(pp, txq, sent_desc); | |
19fc2eae SR |
1567 | |
1568 | return 0; | |
1569 | } | |
1570 | ||
e3b9c98a | 1571 | static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp) |
19fc2eae | 1572 | { |
e3b9c98a | 1573 | struct mvneta_port *pp = dev_get_priv(dev); |
19fc2eae | 1574 | int rx_done; |
19fc2eae | 1575 | struct mvneta_rx_queue *rxq; |
e3b9c98a | 1576 | int rx_bytes = 0; |
19fc2eae SR |
1577 | |
1578 | /* get rx queue */ | |
1579 | rxq = mvneta_rxq_handle_get(pp, rxq_def); | |
1580 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
19fc2eae | 1581 | |
e3b9c98a | 1582 | if (rx_done) { |
19fc2eae SR |
1583 | struct mvneta_rx_desc *rx_desc; |
1584 | unsigned char *data; | |
1585 | u32 rx_status; | |
19fc2eae SR |
1586 | |
1587 | /* | |
1588 | * No cache invalidation needed here, since the desc's are | |
1589 | * located in a uncached memory region | |
1590 | */ | |
1591 | rx_desc = mvneta_rxq_next_desc_get(rxq); | |
1592 | ||
1593 | rx_status = rx_desc->status; | |
1594 | if (!mvneta_rxq_desc_is_first_last(rx_status) || | |
1595 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { | |
1596 | mvneta_rx_error(pp, rx_desc); | |
1597 | /* leave the descriptor untouched */ | |
e3b9c98a | 1598 | return -EIO; |
19fc2eae SR |
1599 | } |
1600 | ||
1601 | /* 2 bytes for marvell header. 4 bytes for crc */ | |
1602 | rx_bytes = rx_desc->data_size - 6; | |
1603 | ||
1604 | /* give packet to stack - skip on first 2 bytes */ | |
3cbc11da | 1605 | data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2; |
19fc2eae SR |
1606 | /* |
1607 | * No cache invalidation needed here, since the rx_buffer's are | |
1608 | * located in a uncached memory region | |
1609 | */ | |
e3b9c98a | 1610 | *packetp = data; |
19fc2eae | 1611 | |
19fc2eae | 1612 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); |
e3b9c98a | 1613 | } |
19fc2eae | 1614 | |
e3b9c98a | 1615 | return rx_bytes; |
19fc2eae SR |
1616 | } |
1617 | ||
e3b9c98a | 1618 | static int mvneta_probe(struct udevice *dev) |
19fc2eae | 1619 | { |
e3b9c98a SR |
1620 | struct eth_pdata *pdata = dev_get_platdata(dev); |
1621 | struct mvneta_port *pp = dev_get_priv(dev); | |
1622 | void *blob = (void *)gd->fdt_blob; | |
e160f7d4 | 1623 | int node = dev_of_offset(dev); |
e3b9c98a SR |
1624 | struct mii_dev *bus; |
1625 | unsigned long addr; | |
19fc2eae | 1626 | void *bd_space; |
976feda2 | 1627 | int ret; |
19fc2eae | 1628 | |
19fc2eae SR |
1629 | /* |
1630 | * Allocate buffer area for descs and rx_buffers. This is only | |
1631 | * done once for all interfaces. As only one interface can | |
6723b235 | 1632 | * be active. Make this area DMA safe by disabling the D-cache |
19fc2eae SR |
1633 | */ |
1634 | if (!buffer_loc.tx_descs) { | |
1635 | /* Align buffer area for descs and rx_buffers to 1MiB */ | |
1636 | bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); | |
3cbc11da | 1637 | mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE, |
19fc2eae SR |
1638 | DCACHE_OFF); |
1639 | buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space; | |
1640 | buffer_loc.rx_descs = (struct mvneta_rx_desc *) | |
3cbc11da | 1641 | ((phys_addr_t)bd_space + |
19fc2eae | 1642 | MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc)); |
3cbc11da | 1643 | buffer_loc.rx_buffers = (phys_addr_t) |
19fc2eae SR |
1644 | (bd_space + |
1645 | MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) + | |
1646 | MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc)); | |
1647 | } | |
1648 | ||
e3b9c98a | 1649 | pp->base = (void __iomem *)pdata->iobase; |
19fc2eae | 1650 | |
e3b9c98a | 1651 | /* Configure MBUS address windows */ |
544eefe0 SR |
1652 | if (of_device_is_compatible(dev, "marvell,armada-3700-neta")) |
1653 | mvneta_bypass_mbus_windows(pp); | |
1654 | else | |
1655 | mvneta_conf_mbus_windows(pp); | |
19fc2eae | 1656 | |
e3b9c98a SR |
1657 | /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */ |
1658 | pp->phy_interface = pdata->phy_interface; | |
1659 | ||
1660 | /* Now read phyaddr from DT */ | |
1661 | addr = fdtdec_get_int(blob, node, "phy", 0); | |
1662 | addr = fdt_node_offset_by_phandle(blob, addr); | |
1663 | pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0); | |
1664 | ||
1665 | bus = mdio_alloc(); | |
1666 | if (!bus) { | |
1667 | printf("Failed to allocate MDIO bus\n"); | |
1668 | return -ENOMEM; | |
1669 | } | |
1670 | ||
1671 | bus->read = mvneta_mdio_read; | |
1672 | bus->write = mvneta_mdio_write; | |
1673 | snprintf(bus->name, sizeof(bus->name), dev->name); | |
1674 | bus->priv = (void *)pp; | |
1675 | pp->bus = bus; | |
19fc2eae | 1676 | |
976feda2 KP |
1677 | ret = mdio_register(bus); |
1678 | if (ret) | |
1679 | return ret; | |
1680 | ||
1681 | return board_network_enable(bus); | |
e3b9c98a | 1682 | } |
19fc2eae | 1683 | |
e3b9c98a SR |
1684 | static void mvneta_stop(struct udevice *dev) |
1685 | { | |
1686 | struct mvneta_port *pp = dev_get_priv(dev); | |
19fc2eae | 1687 | |
e3b9c98a SR |
1688 | mvneta_port_down(pp); |
1689 | mvneta_port_disable(pp); | |
19fc2eae | 1690 | } |
e3b9c98a SR |
1691 | |
1692 | static const struct eth_ops mvneta_ops = { | |
1693 | .start = mvneta_start, | |
1694 | .send = mvneta_send, | |
1695 | .recv = mvneta_recv, | |
1696 | .stop = mvneta_stop, | |
1697 | }; | |
1698 | ||
1699 | static int mvneta_ofdata_to_platdata(struct udevice *dev) | |
1700 | { | |
1701 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
1702 | const char *phy_mode; | |
1703 | ||
1704 | pdata->iobase = dev_get_addr(dev); | |
1705 | ||
1706 | /* Get phy-mode / phy_interface from DT */ | |
1707 | pdata->phy_interface = -1; | |
e160f7d4 SG |
1708 | phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", |
1709 | NULL); | |
e3b9c98a SR |
1710 | if (phy_mode) |
1711 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); | |
1712 | if (pdata->phy_interface == -1) { | |
1713 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); | |
1714 | return -EINVAL; | |
1715 | } | |
1716 | ||
1717 | return 0; | |
1718 | } | |
1719 | ||
1720 | static const struct udevice_id mvneta_ids[] = { | |
1721 | { .compatible = "marvell,armada-370-neta" }, | |
1722 | { .compatible = "marvell,armada-xp-neta" }, | |
544eefe0 | 1723 | { .compatible = "marvell,armada-3700-neta" }, |
e3b9c98a SR |
1724 | { } |
1725 | }; | |
1726 | ||
1727 | U_BOOT_DRIVER(mvneta) = { | |
1728 | .name = "mvneta", | |
1729 | .id = UCLASS_ETH, | |
1730 | .of_match = mvneta_ids, | |
1731 | .ofdata_to_platdata = mvneta_ofdata_to_platdata, | |
1732 | .probe = mvneta_probe, | |
1733 | .ops = &mvneta_ops, | |
1734 | .priv_auto_alloc_size = sizeof(struct mvneta_port), | |
1735 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
1736 | }; |