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ba94a1bb
WD		 1/**
2 * @file IxQMgrAqmIf_p.h
3 *
4 * @author Intel Corporation
5 * @date 30-Oct-2001
6 *
7 * @brief The IxQMgrAqmIf sub-component provides a number of inline
8 * functions for performing I/O on the AQM.
9 *
10 * Because some functions contained in this module are inline and are
11 * used in other modules (within the QMgr component) the definitions are
12 * contained in this header file. The "normal" use of inline functions
13 * is to use the inline functions in the module in which they are
14 * defined. In this case these inline functions are used in external
15 * modules and therefore the use of "inline extern". What this means
16 * is as follows: if a function foo is declared as "inline extern"this
17 * definition is only used for inlining, in no case is the function
18 * compiled on its own. If the compiler cannot inline the function it
19 * becomes an external reference. Therefore in IxQMgrAqmIf.c all
20 * inline functions are defined without the "inline extern" specifier
21 * and so define the external references. In all other modules these
22 * funtions are defined as "inline extern".
23 *
24 *
25 * @par
26 * IXP400 SW Release version 2.0
27 *
28 * -- Copyright Notice --
29 *
30 * @par
31 * Copyright 2001-2005, Intel Corporation.
32 * All rights reserved.
33 *
34 * @par
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
37 * are met:
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
43 * 3. Neither the name of the Intel Corporation nor the names of its contributors
44 * may be used to endorse or promote products derived from this software
45 * without specific prior written permission.
46 *
47 * @par
48 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
49 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
58 * SUCH DAMAGE.
59 *
60 * @par
61 * -- End of Copyright Notice --
62*/
63
64#ifndef IXQMGRAQMIF_P_H
65#define IXQMGRAQMIF_P_H
66
67#include "IxOsalTypes.h"
68
69/*
70 * inline definition
71 */
72
73#ifdef IX_OSAL_INLINE_ALL
74/* If IX_OSAL_INLINE_ALL is set then each inlineable API functions will be defined as
75 inline functions */
76#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
77#else
78#ifdef IXQMGRAQMIF_C
79#ifndef IX_QMGR_AQMIF_INLINE
80#define IX_QMGR_AQMIF_INLINE
81#endif
82#else
83#ifndef IX_QMGR_AQMIF_INLINE
84#define IX_QMGR_AQMIF_INLINE IX_OSAL_INLINE_EXTERN
85#endif
86#endif /* IXQMGRAQMIF_C */
87#endif /* IX_OSAL_INLINE */
88
89
90/*
91 * User defined include files.
92 */
93#include "IxQMgr.h"
94#include "IxQMgrLog_p.h"
95#include "IxQMgrQCfg_p.h"
96
97/* Because this file contains inline functions which will be compiled into
98 * other components, we need to ensure that the IX_COMPONENT_NAME define
99 * is set to ix_qmgr while this code is being compiled. This will ensure
100 * that the correct implementation is provided for the memory access macros
101 * IX_OSAL_READ_LONG and IX_OSAL_WRITE_LONG which are used in this file.
102 * This must be done before including "IxOsalMemAccess.h"
103 */
104#define IX_QMGR_AQMIF_SAVED_COMPONENT_NAME IX_COMPONENT_NAME
105#undef IX_COMPONENT_NAME
106#define IX_COMPONENT_NAME ix_qmgr
107#include "IxOsal.h"
108
109/*
110 * #defines and macros used in this file.
111 */
112
113/* Number of bytes per word */
114#define IX_QMGR_NUM_BYTES_PER_WORD 4
115
116/* Underflow bit mask */
117#define IX_QMGR_UNDERFLOW_BIT_OFFSET 0x0
118
119/* Overflow bit mask */
120#define IX_QMGR_OVERFLOW_BIT_OFFSET 0x1
121
122/* Queue access register, queue 0 */
123#define IX_QMGR_QUEACC0_OFFSET 0x0000
124
125/* Size of queue access register in words */
126#define IX_QMGR_QUEACC_SIZE 0x4/*words*/
127
128/* Queue status register, queues 0-7 */
129#define IX_QMGR_QUELOWSTAT0_OFFSET (IX_QMGR_QUEACC0_OFFSET +\
130(IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))
131
132/* Queue status register, queues 8-15 */
133#define IX_QMGR_QUELOWSTAT1_OFFSET (IX_QMGR_QUELOWSTAT0_OFFSET +\
134 IX_QMGR_NUM_BYTES_PER_WORD)
135
136/* Queue status register, queues 16-23 */
137#define IX_QMGR_QUELOWSTAT2_OFFSET (IX_QMGR_QUELOWSTAT1_OFFSET +\
138 IX_QMGR_NUM_BYTES_PER_WORD)
139
140/* Queue status register, queues 24-31 */
141#define IX_QMGR_QUELOWSTAT3_OFFSET (IX_QMGR_QUELOWSTAT2_OFFSET +\
142 IX_QMGR_NUM_BYTES_PER_WORD)
143
144/* Queue status register Q status bits mask */
145#define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF
146
147/* Size of queue 0-31 status register */
148#define IX_QMGR_QUELOWSTAT_SIZE 0x4 /*words*/
149
150/* The number of queues' status specified per word */
151#define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 0x8
152
153/* Queue UF/OF status register queues 0-15 */
154#define IX_QMGR_QUEUOSTAT0_OFFSET (IX_QMGR_QUELOWSTAT3_OFFSET +\
155 IX_QMGR_NUM_BYTES_PER_WORD)
156/* Queue UF/OF status register queues 16-31 */
157#define IX_QMGR_QUEUOSTAT1_OFFSET (IX_QMGR_QUEUOSTAT0_OFFSET +\
158 IX_QMGR_NUM_BYTES_PER_WORD)
159
160/* The number of queues' underflow/overflow status specified per word */
161#define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 0x10
162
163/* Queue NE status register, queues 32-63 */
164#define IX_QMGR_QUEUPPSTAT0_OFFSET (IX_QMGR_QUEUOSTAT1_OFFSET +\
165 IX_QMGR_NUM_BYTES_PER_WORD)
166
167/* Queue F status register, queues 32-63 */
168#define IX_QMGR_QUEUPPSTAT1_OFFSET (IX_QMGR_QUEUPPSTAT0_OFFSET +\
169 IX_QMGR_NUM_BYTES_PER_WORD)
170
171/* Size of queue 32-63 status register */
172#define IX_QMGR_QUEUPPSTAT_SIZE 0x2 /*words*/
173
174/* The number of queues' status specified per word */
175#define IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD 0x20
176
177/* Queue INT source select register, queues 0-7 */
178#define IX_QMGR_INT0SRCSELREG0_OFFSET (IX_QMGR_QUEUPPSTAT1_OFFSET +\
179 IX_QMGR_NUM_BYTES_PER_WORD)
180
181/* Queue INT source select register, queues 8-15 */
182#define IX_QMGR_INT0SRCSELREG1_OFFSET (IX_QMGR_INT0SRCSELREG0_OFFSET+\
183 IX_QMGR_NUM_BYTES_PER_WORD)
184
185/* Queue INT source select register, queues 16-23 */
186#define IX_QMGR_INT0SRCSELREG2_OFFSET (IX_QMGR_INT0SRCSELREG1_OFFSET+\
187 IX_QMGR_NUM_BYTES_PER_WORD)
188
189/* Queue INT source select register, queues 24-31 */
190#define IX_QMGR_INT0SRCSELREG3_OFFSET (IX_QMGR_INT0SRCSELREG2_OFFSET+\
191 IX_QMGR_NUM_BYTES_PER_WORD)
192
193/* Size of interrupt source select reegister */
194#define IX_QMGR_INT0SRCSELREG_SIZE 0x4 /*words*/
195
196/* The number of queues' interrupt source select specified per word*/
197#define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 0x8
198
199/* Queue INT enable register, queues 0-31 */
200#define IX_QMGR_QUEIEREG0_OFFSET (IX_QMGR_INT0SRCSELREG3_OFFSET +\
201 IX_QMGR_NUM_BYTES_PER_WORD)
202
203/* Queue INT enable register, queues 32-63 */
204#define IX_QMGR_QUEIEREG1_OFFSET (IX_QMGR_QUEIEREG0_OFFSET +\
205 IX_QMGR_NUM_BYTES_PER_WORD)
206
207/* Queue INT register, queues 0-31 */
208#define IX_QMGR_QINTREG0_OFFSET (IX_QMGR_QUEIEREG1_OFFSET +\
209 IX_QMGR_NUM_BYTES_PER_WORD)
210
211/* Queue INT register, queues 32-63 */
212#define IX_QMGR_QINTREG1_OFFSET (IX_QMGR_QINTREG0_OFFSET +\
213 IX_QMGR_NUM_BYTES_PER_WORD)
214
215/* Size of interrupt register */
216#define IX_QMGR_QINTREG_SIZE 0x2 /*words*/
217
218/* Number of queues' status specified per word */
219#define IX_QMGR_QINTREG_NUM_QUE_PER_WORD 0x20
220
221/* Number of bits per queue interrupt status */
222#define IX_QMGR_QINTREG_BITS_PER_QUEUE 0x1
223#define IX_QMGR_QINTREG_BIT_OFFSET 0x1
224
225/* Size of address space not used by AQM */
226#define IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES 0x1bC0
227
228/* Queue config register, queue 0 */
229#define IX_QMGR_QUECONFIG_BASE_OFFSET (IX_QMGR_QINTREG1_OFFSET +\
230 IX_QMGR_NUM_BYTES_PER_WORD +\
231 IX_QMGR_AQM_UNUSED_ADDRESS_SPACE_SIZE_IN_BYTES)
232
233/* Total size of configuration words */
234#define IX_QMGR_QUECONFIG_SIZE 0x100
235
236/* Start of SRAM queue buffer space */
237#define IX_QMGR_QUEBUFFER_SPACE_OFFSET (IX_QMGR_QUECONFIG_BASE_OFFSET +\
238 IX_QMGR_MAX_NUM_QUEUES * IX_QMGR_NUM_BYTES_PER_WORD)
239
240/* Total bits in a word */
241#define BITS_PER_WORD 32
242
243/* Size of queue buffer space */
244#define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00
245
246/*
247 * This macro will return the address of the access register for the
248 * queue specified by qId
249 */
250#define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\
251 (((qId) * (IX_QMGR_QUEACC_SIZE * IX_QMGR_NUM_BYTES_PER_WORD))\
252 + IX_QMGR_QUEACC0_OFFSET)
253
254/*
255 * Bit location of bit-3 of INT0SRCSELREG0 register to enabled
256 * sticky interrupt register.
257 */
258#define IX_QMGR_INT0SRCSELREG0_BIT3 3
259
260/*
261 * Variable declerations global to this file. Externs are followed by
262 * statics.
263 */
264extern UINT32 aqmBaseAddress;
265
266/*
267 * Function declarations.
268 */
269void
270ixQMgrAqmIfInit (void);
271
272void
273ixQMgrAqmIfUninit (void);
274
275unsigned
276ixQMgrAqmIfLog2 (unsigned number);
277
278void
279ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId,
280 UINT32 registerBaseAddrOffset,
281 unsigned queuesPerRegWord,
282 UINT32 value);
283
284void
285ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId,
286 IxQMgrSourceId srcSel,
287 unsigned int *statusWordOffset,
288 UINT32 *checkValue,
289 UINT32 *mask);
290/*
291 * The Xscale software allways deals with logical addresses and so the
292 * base address of the AQM memory space is not a hardcoded value. This
293 * function must be called before any other function in this component.
294 * NO CHECKING is performed to ensure that the base address has been
295 * set.
296 */
297void
298ixQMgrAqmIfBaseAddressSet (UINT32 address);
299
300/*
301 * Get the base address of the AQM memory space.
302 */
303void
304ixQMgrAqmIfBaseAddressGet (UINT32 *address);
305
306/*
307 * Get the sram base address
308 */
309void
310ixQMgrAqmIfSramBaseAddressGet (UINT32 *address);
311
312/*
313 * Read a queue status
314 */
315void
316ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
317 IxQMgrQStatus* status);
318
319
320/*
321 * Set INT0SRCSELREG0 Bit3
322 */
323void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void);
324
325
326/*
327 * Set the interrupt source
328 */
329void
330ixQMgrAqmIfIntSrcSelWrite (IxQMgrQId qId,
331 IxQMgrSourceId sourceId);
332
333/*
334 * Enable interruptson a queue
335 */
336void
337ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId);
338
339/*
340 * Disable interrupt on a quee
341 */
342void
343ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId);
344
345/*
346 * Write the config register of the specified queue
347 */
348void
349ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId,
350 IxQMgrQSizeInWords qSizeInWords,
351 IxQMgrQEntrySizeInWords entrySizeInWords,
352 UINT32 freeSRAMAddress);
353
354/*
355 * read fields from the config of the specified queue.
356 */
357void
358ixQMgrAqmIfQueCfgRead (IxQMgrQId qId,
359 unsigned int numEntries,
360 UINT32 *baseAddress,
361 unsigned int *ne,
362 unsigned int *nf,
363 UINT32 *readPtr,
364 UINT32 *writePtr);
365
366/*
367 * Set the ne and nf watermark level on a queue.
368 */
369void
370ixQMgrAqmIfWatermarkSet (IxQMgrQId qId,
371 unsigned ne,
372 unsigned nf);
373
374/* Inspect an entry without moving the read pointer */
375IX_STATUS
376ixQMgrAqmIfQPeek (IxQMgrQId qId,
377 unsigned int entryIndex,
378 unsigned int *entry);
379
380/* Modify an entry without moving the write pointer */
381IX_STATUS
382ixQMgrAqmIfQPoke (IxQMgrQId qId,
383 unsigned int entryIndex,
384 unsigned int *entry);
385
386/*
387 * Function prototype for inline functions. For description refers to
388 * the functions defintion below.
389 */
390IX_QMGR_AQMIF_INLINE void
391ixQMgrAqmIfWordWrite (VUINT32 *address,
392 UINT32 word);
393
394IX_QMGR_AQMIF_INLINE void
395ixQMgrAqmIfWordRead (VUINT32 *address,
396 UINT32 *word);
397
398IX_QMGR_AQMIF_INLINE void
399ixQMgrAqmIfQPop (IxQMgrQId qId,
400 IxQMgrQEntrySizeInWords numWords,
401 UINT32 *entry);
402
403IX_QMGR_AQMIF_INLINE void
404ixQMgrAqmIfQPush (IxQMgrQId qId,
405 IxQMgrQEntrySizeInWords numWords,
406 UINT32 *entry);
407
408IX_QMGR_AQMIF_INLINE void
409ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group,
410 UINT32 *qStatusWords);
411
412IX_QMGR_AQMIF_INLINE BOOL
413ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
414 UINT32 *newQStatusWords,
415 unsigned int statusWordOffset,
416 UINT32 checkValue,
417 UINT32 mask);
418
419IX_QMGR_AQMIF_INLINE BOOL
420ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId,
421 UINT32 registerBaseAddrOffset,
422 unsigned queuesPerRegWord,
423 unsigned relativeBitOffset,
424 BOOL reset);
425
426IX_QMGR_AQMIF_INLINE BOOL
427ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId);
428
429IX_QMGR_AQMIF_INLINE BOOL
430ixQMgrAqmIfOverflowCheck (IxQMgrQId qId);
431
432IX_QMGR_AQMIF_INLINE UINT32
433ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId,
434 UINT32 registerBaseAddrOffset,
435 unsigned queuesPerRegWord);
436IX_QMGR_AQMIF_INLINE void
437ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group,
438 UINT32 reg);
439IX_QMGR_AQMIF_INLINE void
440ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group,
441 UINT32 *regVal);
442
443IX_QMGR_AQMIF_INLINE void
444ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
445 IxQMgrQStatus *status);
446
447IX_QMGR_AQMIF_INLINE void
448ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
449 IxQMgrQStatus *status);
450
451IX_QMGR_AQMIF_INLINE void
452ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
453 IxQMgrQStatus *qStatus);
454
455IX_QMGR_AQMIF_INLINE unsigned
456ixQMgrAqmIfPow2NumDivide (unsigned numerator,
457 unsigned denominator);
458
459IX_QMGR_AQMIF_INLINE void
460ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group,
461 UINT32 *regVal);
462/*
463 * Inline functions
464 */
465
466/*
467 * This inline function is used by other QMgr components to write one
468 * word to the specified address.
469 */
470IX_QMGR_AQMIF_INLINE void
471ixQMgrAqmIfWordWrite (VUINT32 *address,
472 UINT32 word)
473{
474 IX_OSAL_WRITE_LONG(address, word);
475}
476
477/*
478 * This inline function is used by other QMgr components to read a
479 * word from the specified address.
480 */
481IX_QMGR_AQMIF_INLINE void
482ixQMgrAqmIfWordRead (VUINT32 *address,
483 UINT32 *word)
484{
485 *word = IX_OSAL_READ_LONG(address);
486}
487
488
489/*
490 * This inline function is used by other QMgr components to pop an
491 * entry off the specified queue.
492 */
493IX_QMGR_AQMIF_INLINE void
494ixQMgrAqmIfQPop (IxQMgrQId qId,
495 IxQMgrQEntrySizeInWords numWords,
496 UINT32 *entry)
497{
498 volatile UINT32 *accRegAddr;
499
500 accRegAddr = (UINT32*)(aqmBaseAddress +
53677ef1 501 IX_QMGR_Q_ACCESS_ADDR_GET(qId));
ba94a1bb
WD		 502
503 switch (numWords)
504 {
505 case IX_QMGR_Q_ENTRY_SIZE1:
506 ixQMgrAqmIfWordRead (accRegAddr, entry);
507 break;
508 case IX_QMGR_Q_ENTRY_SIZE2:
509 ixQMgrAqmIfWordRead (accRegAddr++, entry++);
510 ixQMgrAqmIfWordRead (accRegAddr, entry);
511 break;
512 case IX_QMGR_Q_ENTRY_SIZE4:
513 ixQMgrAqmIfWordRead (accRegAddr++, entry++);
514 ixQMgrAqmIfWordRead (accRegAddr++, entry++);
515 ixQMgrAqmIfWordRead (accRegAddr++, entry++);
516 ixQMgrAqmIfWordRead (accRegAddr, entry);
517 break;
518 default:
519 IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPop");
520 break;
521 }
522}
523
524/*
525 * This inline function is used by other QMgr components to push an
526 * entry to the specified queue.
527 */
528IX_QMGR_AQMIF_INLINE void
529ixQMgrAqmIfQPush (IxQMgrQId qId,
530 IxQMgrQEntrySizeInWords numWords,
531 UINT32 *entry)
532{
533 volatile UINT32 *accRegAddr;
534
535 accRegAddr = (UINT32*)(aqmBaseAddress +
53677ef1 536 IX_QMGR_Q_ACCESS_ADDR_GET(qId));
ba94a1bb
WD		 537
538 switch (numWords)
539 {
540 case IX_QMGR_Q_ENTRY_SIZE1:
541 ixQMgrAqmIfWordWrite (accRegAddr, *entry);
542 break;
543 case IX_QMGR_Q_ENTRY_SIZE2:
544 ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
545 ixQMgrAqmIfWordWrite (accRegAddr, *entry);
546 break;
547 case IX_QMGR_Q_ENTRY_SIZE4:
548 ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
549 ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
550 ixQMgrAqmIfWordWrite (accRegAddr++, *entry++);
551 ixQMgrAqmIfWordWrite (accRegAddr, *entry);
552 break;
553 default:
554 IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfQPush");
555 break;
556 }
557}
558
559/*
560 * The AQM interrupt registers contains a bit for each AQM queue
561 * specifying the queue (s) that cause an interrupt to fire. This
562 * function is called by IxQMGrDispatcher component.
563 */
564IX_QMGR_AQMIF_INLINE void
565ixQMgrAqmIfQStatusRegsRead (IxQMgrDispatchGroup group,
566 UINT32 *qStatusWords)
567{
568 volatile UINT32 *regAddress = NULL;
569
570 if (group == IX_QMGR_QUELOW_GROUP)
571 {
572 regAddress = (UINT32*)(aqmBaseAddress +
573 IX_QMGR_QUELOWSTAT0_OFFSET);
574
575 ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
576 ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
577 ixQMgrAqmIfWordRead (regAddress++, qStatusWords++);
578 ixQMgrAqmIfWordRead (regAddress, qStatusWords);
579 }
580 else /* We have the upper queues */
581 {
582 /* Only need to read the Nearly Empty status register for
583 * queues 32-63 as for therse queues the interrtupt source
584 * condition is fixed to Nearly Empty
585 */
586 regAddress = (UINT32*)(aqmBaseAddress +
587 IX_QMGR_QUEUPPSTAT0_OFFSET);
588 ixQMgrAqmIfWordRead (regAddress, qStatusWords);
589 }
590}
591
592
593/*
594 * This function check if the status for a queue has changed between
595 * 2 snapshots and if it has, that the status matches a particular
596 * value after masking.
597 */
598IX_QMGR_AQMIF_INLINE BOOL
599ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords,
600 UINT32 *newQStatusWords,
601 unsigned int statusWordOffset,
602 UINT32 checkValue,
603 UINT32 mask)
604{
605 if (((oldQStatusWords[statusWordOffset] & mask) !=
606 (newQStatusWords[statusWordOffset] & mask)) &&
607 ((newQStatusWords[statusWordOffset] & mask) == checkValue))
608 {
472d5460 609 return true;
ba94a1bb
WD		 610 }
611
472d5460 612 return false;
ba94a1bb
WD		 613}
614
615/*
616 * The AQM interrupt register contains a bit for each AQM queue
617 * specifying the queue (s) that cause an interrupt to fire. This
618 * function is called by IxQMgrDispatcher component.
619 */
620IX_QMGR_AQMIF_INLINE void
621ixQMgrAqmIfQInterruptRegRead (IxQMgrDispatchGroup group,
622 UINT32 *regVal)
623{
624 volatile UINT32 *regAddress;
625
626 if (group == IX_QMGR_QUELOW_GROUP)
627 {
628 regAddress = (UINT32*)(aqmBaseAddress +
629 IX_QMGR_QINTREG0_OFFSET);
630 }
631 else
632 {
633 regAddress = (UINT32*)(aqmBaseAddress +
634 IX_QMGR_QINTREG1_OFFSET);
635 }
636
637 ixQMgrAqmIfWordRead (regAddress, regVal);
638}
639
640/*
641 * The AQM interrupt enable register contains a bit for each AQM queue.
642 * This function reads the interrupt enable register. This
643 * function is called by IxQMgrDispatcher component.
644 */
645IX_QMGR_AQMIF_INLINE void
646ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group,
647 UINT32 *regVal)
648{
649 volatile UINT32 *regAddress;
650
651 if (group == IX_QMGR_QUELOW_GROUP)
652 {
653 regAddress = (UINT32*)(aqmBaseAddress +
654 IX_QMGR_QUEIEREG0_OFFSET);
655 }
656 else
657 {
658 regAddress = (UINT32*)(aqmBaseAddress +
659 IX_QMGR_QUEIEREG1_OFFSET);
660 }
661
662 ixQMgrAqmIfWordRead (regAddress, regVal);
663}
664
665
666/*
667 * This inline function will read the status bit of a queue
472d5460 668 * specified by qId. If reset is true the bit is cleared.
ba94a1bb
WD		 669 */
670IX_QMGR_AQMIF_INLINE BOOL
671ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId,
672 UINT32 registerBaseAddrOffset,
673 unsigned queuesPerRegWord,
674 unsigned relativeBitOffset,
675 BOOL reset)
676{
677 UINT32 actualBitOffset;
678 volatile UINT32 *registerAddress;
679 UINT32 registerWord;
680
681 /*
682 * Calculate the registerAddress
683 * multiple queues split accross registers
684 */
685 registerAddress = (UINT32*)(aqmBaseAddress +
53677ef1
WD		 686 registerBaseAddrOffset +
687 ((qId / queuesPerRegWord) *
688 IX_QMGR_NUM_BYTES_PER_WORD));
ba94a1bb
WD		 689
690 /*
691 * Get the status word
692 */
693 ixQMgrAqmIfWordRead (registerAddress, &registerWord);
694
695 /*
696 * Calculate the actualBitOffset
697 * status for multiple queues stored in one register
698 */
699 actualBitOffset = (relativeBitOffset + 1) <<
700 ((qId & (queuesPerRegWord - 1)) * (BITS_PER_WORD / queuesPerRegWord));
701
702 /* Check if the status bit is set */
703 if (registerWord & actualBitOffset)
704 {
705 /* Clear the bit if reset */
706 if (reset)
707 {
708 ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset));
709 }
472d5460 710 return true;
ba94a1bb
WD		 711 }
712
713 /* Bit not set */
472d5460 714 return false;
ba94a1bb
WD		 715}
716
717
718/*
719 * @ingroup IxQmgrAqmIfAPI
720 *
721 * @brief Read the underflow status of a queue
722 *
723 * This inline function will read the underflow status of a queue
724 * specified by qId.
725 *
726 */
727IX_QMGR_AQMIF_INLINE BOOL
728ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId)
729{
730 if (qId < IX_QMGR_MIN_QUEUPP_QID)
731 {
732 return (ixQMgrAqmIfRegisterBitCheck (qId,
733 IX_QMGR_QUEUOSTAT0_OFFSET,
734 IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
735 IX_QMGR_UNDERFLOW_BIT_OFFSET,
472d5460 736 true/*reset*/));
ba94a1bb
WD		 737 }
738 else
739 {
740 /* Qs 32-63 have no underflow status */
472d5460 741 return false;
ba94a1bb
WD		 742 }
743}
744
745/*
746 * This inline function will read the overflow status of a queue
747 * specified by qId.
748 */
749IX_QMGR_AQMIF_INLINE BOOL
750ixQMgrAqmIfOverflowCheck (IxQMgrQId qId)
751{
752 if (qId < IX_QMGR_MIN_QUEUPP_QID)
753 {
754 return (ixQMgrAqmIfRegisterBitCheck (qId,
755 IX_QMGR_QUEUOSTAT0_OFFSET,
756 IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD,
757 IX_QMGR_OVERFLOW_BIT_OFFSET,
472d5460 758 true/*reset*/));
ba94a1bb
WD		 759 }
760 else
761 {
762 /* Qs 32-63 have no overflow status */
472d5460 763 return false;
ba94a1bb
WD		 764 }
765}
766
767/*
768 * This inline function will read the status bits of a queue
769 * specified by qId.
770 */
771IX_QMGR_AQMIF_INLINE UINT32
772ixQMgrAqmIfQRegisterBitsRead (IxQMgrQId qId,
773 UINT32 registerBaseAddrOffset,
774 unsigned queuesPerRegWord)
775{
776 volatile UINT32 *registerAddress;
777 UINT32 registerWord;
778 UINT32 statusBitsMask;
779 UINT32 bitsPerQueue;
780
781 bitsPerQueue = BITS_PER_WORD / queuesPerRegWord;
782
783 /*
784 * Calculate the registerAddress
785 * multiple queues split accross registers
786 */
787 registerAddress = (UINT32*)(aqmBaseAddress +
788 registerBaseAddrOffset +
789 ((qId / queuesPerRegWord) *
790 IX_QMGR_NUM_BYTES_PER_WORD));
791 /*
792 * Read the status word
793 */
794 ixQMgrAqmIfWordRead (registerAddress, &registerWord);
795
796
797 /*
798 * Calculate the mask for the status bits for this queue.
799 */
800 statusBitsMask = ((1 << bitsPerQueue) - 1);
801
802 /*
803 * Shift the status word so it is right justified
804 */
805 registerWord >>= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue);
806
807 /*
808 * Mask out all bar the status bits for this queue
809 */
810 return (registerWord &= statusBitsMask);
811}
812
813/*
814 * This function is called by IxQMgrDispatcher to set the contents of
815 * the AQM interrupt register.
816 */
817IX_QMGR_AQMIF_INLINE void
818ixQMgrAqmIfQInterruptRegWrite (IxQMgrDispatchGroup group,
819 UINT32 reg)
820{
821 volatile UINT32 *address;
822
823 if (group == IX_QMGR_QUELOW_GROUP)
824 {
825 address = (UINT32*)(aqmBaseAddress +
826 IX_QMGR_QINTREG0_OFFSET);
827 }
828 else
829 {
830 address = (UINT32*)(aqmBaseAddress +
831 IX_QMGR_QINTREG1_OFFSET);
832 }
833
834 ixQMgrAqmIfWordWrite (address, reg);
835}
836
837/*
838 * Read the status of a queue in the range 0-31.
839 *
840 * This function is used by other QMgr components to read the
841 * status of the queue specified by qId.
842 */
843IX_QMGR_AQMIF_INLINE void
844ixQMgrAqmIfQueLowStatRead (IxQMgrQId qId,
845 IxQMgrQStatus *status)
846{
847 /* Read the general status bits */
848 *status = ixQMgrAqmIfQRegisterBitsRead (qId,
849 IX_QMGR_QUELOWSTAT0_OFFSET,
850 IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
851}
852
853/*
854 * This function will read the status of the queue specified
855 * by qId.
856 */
857IX_QMGR_AQMIF_INLINE void
858ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId,
859 IxQMgrQStatus *status)
860{
861 /* Reset the status bits */
862 *status = 0;
863
864 /*
865 * Check if the queue is nearly empty,
866 * N.b. QUPP stat register contains status for regs 32-63 at each
867 * bit position so subtract 32 to get bit offset
868 */
869 if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
870 IX_QMGR_QUEUPPSTAT0_OFFSET,
871 IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
872 0/*relativeBitOffset*/,
472d5460 873 false/*!reset*/))
ba94a1bb
WD		 874 {
875 *status |= IX_QMGR_Q_STATUS_NE_BIT_MASK;
876 }
877
878 /*
879 * Check if the queue is full,
880 * N.b. QUPP stat register contains status for regs 32-63 at each
881 * bit position so subtract 32 to get bit offset
882 */
883 if (ixQMgrAqmIfRegisterBitCheck ((qId - IX_QMGR_MIN_QUEUPP_QID),
884 IX_QMGR_QUEUPPSTAT1_OFFSET,
885 IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD,
886 0/*relativeBitOffset*/,
472d5460 887 false/*!reset*/))
ba94a1bb
WD		 888 {
889 *status |= IX_QMGR_Q_STATUS_F_BIT_MASK;
890 }
891}
892
893/*
894 * This function is used by other QMgr components to read the
895 * status of the queue specified by qId.
896 */
897IX_QMGR_AQMIF_INLINE void
898ixQMgrAqmIfQueStatRead (IxQMgrQId qId,
899 IxQMgrQStatus *qStatus)
900{
901 if (qId < IX_QMGR_MIN_QUEUPP_QID)
902 {
903 ixQMgrAqmIfQueLowStatRead (qId, qStatus);
904 }
905 else
906 {
907 ixQMgrAqmIfQueUppStatRead (qId, qStatus);
908 }
909}
910
911
912/*
913 * This function performs a mod division
914 */
915IX_QMGR_AQMIF_INLINE unsigned
916ixQMgrAqmIfPow2NumDivide (unsigned numerator,
917 unsigned denominator)
918{
919 /* Number is evenly divisable by 2 */
920 return (numerator >> ixQMgrAqmIfLog2 (denominator));
921}
922
923/* Restore IX_COMPONENT_NAME */
924#undef IX_COMPONENT_NAME
925#define IX_COMPONENT_NAME IX_QMGR_AQMIF_SAVED_COMPONENT_NAME
926
927#endif/*IXQMGRAQMIF_P_H*/
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