[thirdparty/u-boot.git] / drivers / net / pfe_eth / pfe_eth.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2015-2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 */

#include <common.h>
#include <dm.h>
#include <log.h>
#include <malloc.h>
#include <dm/platform_data/pfe_dm_eth.h>
#include <net.h>
#include <linux/delay.h>
#include <net/pfe_eth/pfe_eth.h>
#include <net/pfe_eth/pfe_mdio.h>

struct gemac_s gem_info[] = {
	/* PORT_0 configuration */
	{
		/* GEMAC config */
		.gemac_speed = PFE_MAC_SPEED_1000M,
		.gemac_duplex = DUPLEX_FULL,

		/* phy iface */
		.phy_address = CONFIG_PFE_EMAC1_PHY_ADDR,
		.phy_mode = PHY_INTERFACE_MODE_SGMII,
	},
	/* PORT_1 configuration */
	{
		/* GEMAC config */
		.gemac_speed = PFE_MAC_SPEED_1000M,
		.gemac_duplex = DUPLEX_FULL,

		/* phy iface */
		.phy_address = CONFIG_PFE_EMAC2_PHY_ADDR,
		.phy_mode = PHY_INTERFACE_MODE_RGMII_ID,
	},
};

static inline void pfe_gemac_enable(void *gemac_base)
{
	writel(readl(gemac_base + EMAC_ECNTRL_REG) |
		EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
}

static inline void pfe_gemac_disable(void *gemac_base)
{
	writel(readl(gemac_base + EMAC_ECNTRL_REG) &
		~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
}

static inline void pfe_gemac_set_speed(void *gemac_base, u32 speed)
{
	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
	u32 ecr = readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
	u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
	u32 rgmii_pcr = in_be32(&scfg->rgmiipcr) &
			~(SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETSP_10M);

	if (speed == _1000BASET) {
		ecr |= EMAC_ECNTRL_SPEED;
		rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;
	} else if (speed != _100BASET) {
		rcr |= EMAC_RCNTRL_RMII_10T;
		rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;
	}

	writel(ecr, gemac_base + EMAC_ECNTRL_REG);
	out_be32(&scfg->rgmiipcr, rgmii_pcr | SCFG_RGMIIPCR_SETFD);

	/* remove loop back */
	rcr &= ~EMAC_RCNTRL_LOOP;
	/* enable flow control */
	rcr |= EMAC_RCNTRL_FCE;

	/* Enable MII mode */
	rcr |= EMAC_RCNTRL_MII_MODE;

	writel(rcr, gemac_base + EMAC_RCNTRL_REG);

	/* Enable Tx full duplex */
	writel(readl(gemac_base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN,
	       gemac_base + EMAC_TCNTRL_REG);
}

static int pfe_eth_write_hwaddr(struct udevice *dev)
{
	struct pfe_eth_dev *priv = dev_get_priv(dev);
	struct gemac_s *gem = priv->gem;
	struct eth_pdata *pdata = dev_get_plat(dev);
	uchar *mac = pdata->enetaddr;

	writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
	       gem->gemac_base + EMAC_PHY_ADDR_LOW);
	writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, gem->gemac_base +
	       EMAC_PHY_ADDR_HIGH);
	return 0;
}

/** Stops or Disables GEMAC pointing to this eth iface.
 *
 * @param[in]   edev    Pointer to eth device structure.
 *
 * Return:      none
 */
static inline void pfe_eth_stop(struct udevice *dev)
{
	struct pfe_eth_dev *priv = dev_get_priv(dev);

	pfe_gemac_disable(priv->gem->gemac_base);

	gpi_disable(priv->gem->egpi_base);
}

static int pfe_eth_start(struct udevice *dev)
{
	struct pfe_eth_dev *priv = dev_get_priv(dev);
	struct gemac_s *gem = priv->gem;
	int speed;

	/* set ethernet mac address */
	pfe_eth_write_hwaddr(dev);

	writel(EMAC_TFWR, gem->gemac_base + EMAC_TFWR_STR_FWD);
	writel(EMAC_RX_SECTION_FULL_32, gem->gemac_base + EMAC_RX_SECTIOM_FULL);
	writel(EMAC_TRUNC_FL_16K, gem->gemac_base + EMAC_TRUNC_FL);
	writel(EMAC_TX_SECTION_EMPTY_30, gem->gemac_base
	       + EMAC_TX_SECTION_EMPTY);
	writel(EMAC_MIBC_NO_CLR_NO_DIS, gem->gemac_base
	       + EMAC_MIB_CTRL_STS_REG);

#ifdef CONFIG_PHYLIB
	/* Start up the PHY */
	if (phy_startup(priv->phydev)) {
		printf("Could not initialize PHY %s\n",
		       priv->phydev->dev->name);
		return -1;
	}
	speed = priv->phydev->speed;
	printf("Speed detected %x\n", speed);
	if (priv->phydev->duplex == DUPLEX_HALF) {
		printf("Half duplex not supported\n");
		return -1;
	}
#endif

	pfe_gemac_set_speed(gem->gemac_base, speed);

	/* Enable GPI */
	gpi_enable(gem->egpi_base);

	/* Enable GEMAC */
	pfe_gemac_enable(gem->gemac_base);

	return 0;
}

static int pfe_eth_send(struct udevice *dev, void *packet, int length)
{
	struct pfe_eth_dev *priv = (struct pfe_eth_dev *)dev_get_priv(dev);

	int rc;
	int i = 0;

	rc = pfe_send(priv->gemac_port, packet, length);

	if (rc < 0) {
		printf("Tx Queue full\n");
		return rc;
	}

	while (1) {
		rc = pfe_tx_done();
		if (rc == 0)
			break;

		udelay(100);
		i++;
		if (i == 30000) {
			printf("Tx timeout, send failed\n");
			break;
		}
	}

	return 0;
}

static int pfe_eth_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct pfe_eth_dev *priv = dev_get_priv(dev);
	uchar *pkt_buf;
	int len;
	int phy_port;

	len = pfe_recv(&pkt_buf, &phy_port);

	if (len == 0)
		return -EAGAIN; /* no packet in rx */
	else if  (len < 0)
		return -EAGAIN;

	debug("Rx pkt: pkt_buf(0x%p), phy_port(%d), len(%d)\n", pkt_buf,
	      phy_port, len);
	if (phy_port != priv->gemac_port)  {
		printf("Rx pkt not on expected port\n");
		return -EAGAIN;
	}

	*packetp = pkt_buf;

	return len;
}

static int pfe_eth_probe(struct udevice *dev)
{
	struct pfe_eth_dev *priv = dev_get_priv(dev);
	struct pfe_ddr_address pfe_addr;
	struct pfe_eth_pdata *pdata = dev_get_plat(dev);
	int ret = 0;
	static int init_done;

	if (!init_done) {
		pfe_addr.ddr_pfe_baseaddr =
				(void *)pdata->pfe_ddr_addr.ddr_pfe_baseaddr;
		pfe_addr.ddr_pfe_phys_baseaddr =
		(unsigned long)pdata->pfe_ddr_addr.ddr_pfe_phys_baseaddr;

		debug("ddr_pfe_baseaddr: %p, ddr_pfe_phys_baseaddr: %08x\n",
		      pfe_addr.ddr_pfe_baseaddr,
		      (u32)pfe_addr.ddr_pfe_phys_baseaddr);

		ret = pfe_drv_init(&pfe_addr);
		if (ret)
			return ret;

		init_pfe_scfg_dcfg_regs();
		init_done = 1;
	}

	priv->gemac_port = pdata->pfe_eth_pdata_mac.phy_interface;
	priv->gem = &gem_info[priv->gemac_port];
	priv->dev = dev;

	switch (priv->gemac_port)  {
	case EMAC_PORT_0:
	default:
		priv->gem->gemac_base = EMAC1_BASE_ADDR;
		priv->gem->egpi_base = EGPI1_BASE_ADDR;
		break;
	case EMAC_PORT_1:
		priv->gem->gemac_base = EMAC2_BASE_ADDR;
		priv->gem->egpi_base = EGPI2_BASE_ADDR;
		break;
	}

	ret = pfe_eth_board_init(dev);
	if (ret)
		return ret;

#if defined(CONFIG_PHYLIB)
	ret = pfe_phy_configure(priv, pdata->pfe_eth_pdata_mac.phy_interface,
				gem_info[priv->gemac_port].phy_address);
#endif
	return ret;
}

static int pfe_eth_bind(struct udevice *dev)
{
	struct pfe_eth_pdata *pdata = dev_get_plat(dev);
	char name[20];

	sprintf(name, "pfe_eth%u", pdata->pfe_eth_pdata_mac.phy_interface);

	return device_set_name(dev, name);
}

static const struct eth_ops pfe_eth_ops = {
	.start		= pfe_eth_start,
	.send		= pfe_eth_send,
	.recv		= pfe_eth_recv,
	.free_pkt	= pfe_eth_free_pkt,
	.stop		= pfe_eth_stop,
	.write_hwaddr	= pfe_eth_write_hwaddr,
};

U_BOOT_DRIVER(pfe_eth) = {
	.name	= "pfe_eth",
	.id	= UCLASS_ETH,
	.bind	= pfe_eth_bind,
	.probe	= pfe_eth_probe,
	.remove = pfe_eth_remove,
	.ops	= &pfe_eth_ops,
	.priv_auto	= sizeof(struct pfe_eth_dev),
	.plat_auto	= sizeof(struct pfe_eth_pdata)
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
a4a40437 CJ	2	/*
	3	* Copyright 2015-2016 Freescale Semiconductor, Inc.
	4	* Copyright 2017 NXP
a4a40437 CJ	5	*/
a4a40437 CJ	6
d678a59d	7	#include <common.h>
a4a40437	8	#include <dm.h>
f7ae49fc	9	#include <log.h>
336d4615	10	#include <malloc.h>
a4a40437 CJ	11	#include <dm/platform_data/pfe_dm_eth.h>
a4a40437 CJ	12	#include <net.h>
c05ed00a	13	#include <linux/delay.h>
a4a40437 CJ	14	#include <net/pfe_eth/pfe_eth.h>
	15	#include <net/pfe_eth/pfe_mdio.h>
	16
	17	struct gemac_s gem_info[] = {
	18	/* PORT_0 configuration */
	19	{
	20	/* GEMAC config */
	21	.gemac_speed = PFE_MAC_SPEED_1000M,
	22	.gemac_duplex = DUPLEX_FULL,
	23
	24	/* phy iface */
	25	.phy_address = CONFIG_PFE_EMAC1_PHY_ADDR,
	26	.phy_mode = PHY_INTERFACE_MODE_SGMII,
	27	},
	28	/* PORT_1 configuration */
	29	{
	30	/* GEMAC config */
	31	.gemac_speed = PFE_MAC_SPEED_1000M,
	32	.gemac_duplex = DUPLEX_FULL,
	33
	34	/* phy iface */
	35	.phy_address = CONFIG_PFE_EMAC2_PHY_ADDR,
cb1de606	36	.phy_mode = PHY_INTERFACE_MODE_RGMII_ID,
a4a40437 CJ	37	},
	38	};
	39
	40	static inline void pfe_gemac_enable(void *gemac_base)
	41	{
	42	writel(readl(gemac_base + EMAC_ECNTRL_REG) \|
	43	EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
	44	}
	45
	46	static inline void pfe_gemac_disable(void *gemac_base)
	47	{
	48	writel(readl(gemac_base + EMAC_ECNTRL_REG) &
	49	~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
	50	}
	51
	52	static inline void pfe_gemac_set_speed(void *gemac_base, u32 speed)
	53	{
6cc04547	54	struct ccsr_scfg scfg = (struct ccsr_scfg )CFG_SYS_FSL_SCFG_ADDR;
a4a40437 CJ	55	u32 ecr = readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
	56	u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
	57	u32 rgmii_pcr = in_be32(&scfg->rgmiipcr) &
	58	~(SCFG_RGMIIPCR_SETSP_1000M \| SCFG_RGMIIPCR_SETSP_10M);
	59
	60	if (speed == _1000BASET) {
	61	ecr \|= EMAC_ECNTRL_SPEED;
	62	rgmii_pcr \|= SCFG_RGMIIPCR_SETSP_1000M;
	63	} else if (speed != _100BASET) {
	64	rcr \|= EMAC_RCNTRL_RMII_10T;
	65	rgmii_pcr \|= SCFG_RGMIIPCR_SETSP_10M;
	66	}
	67
	68	writel(ecr, gemac_base + EMAC_ECNTRL_REG);
	69	out_be32(&scfg->rgmiipcr, rgmii_pcr \| SCFG_RGMIIPCR_SETFD);
	70
	71	/* remove loop back */
	72	rcr &= ~EMAC_RCNTRL_LOOP;
	73	/* enable flow control */
	74	rcr \|= EMAC_RCNTRL_FCE;
	75
	76	/* Enable MII mode */
	77	rcr \|= EMAC_RCNTRL_MII_MODE;
	78
	79	writel(rcr, gemac_base + EMAC_RCNTRL_REG);
	80
	81	/* Enable Tx full duplex */
	82	writel(readl(gemac_base + EMAC_TCNTRL_REG) \| EMAC_TCNTRL_FDEN,
	83	gemac_base + EMAC_TCNTRL_REG);
	84	}
	85
	86	static int pfe_eth_write_hwaddr(struct udevice *dev)
	87	{
	88	struct pfe_eth_dev *priv = dev_get_priv(dev);
	89	struct gemac_s *gem = priv->gem;
c69cda25	90	struct eth_pdata *pdata = dev_get_plat(dev);
a4a40437 CJ	91	uchar *mac = pdata->enetaddr;
	92
	93	writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
	94	gem->gemac_base + EMAC_PHY_ADDR_LOW);
	95	writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, gem->gemac_base +
	96	EMAC_PHY_ADDR_HIGH);
	97	return 0;
	98	}
	99
	100	/** Stops or Disables GEMAC pointing to this eth iface.
	101	*
	102	* @param[in] edev Pointer to eth device structure.
	103	*
185f812c	104	* Return: none
a4a40437 CJ	105	*/
	106	static inline void pfe_eth_stop(struct udevice *dev)
	107	{
	108	struct pfe_eth_dev *priv = dev_get_priv(dev);
	109
	110	pfe_gemac_disable(priv->gem->gemac_base);
	111
	112	gpi_disable(priv->gem->egpi_base);
	113	}
	114
	115	static int pfe_eth_start(struct udevice *dev)
	116	{
	117	struct pfe_eth_dev *priv = dev_get_priv(dev);
	118	struct gemac_s *gem = priv->gem;
	119	int speed;
	120
	121	/* set ethernet mac address */
	122	pfe_eth_write_hwaddr(dev);
	123
	124	writel(EMAC_TFWR, gem->gemac_base + EMAC_TFWR_STR_FWD);
	125	writel(EMAC_RX_SECTION_FULL_32, gem->gemac_base + EMAC_RX_SECTIOM_FULL);
	126	writel(EMAC_TRUNC_FL_16K, gem->gemac_base + EMAC_TRUNC_FL);
	127	writel(EMAC_TX_SECTION_EMPTY_30, gem->gemac_base
	128	+ EMAC_TX_SECTION_EMPTY);
	129	writel(EMAC_MIBC_NO_CLR_NO_DIS, gem->gemac_base
	130	+ EMAC_MIB_CTRL_STS_REG);
	131
	132	#ifdef CONFIG_PHYLIB
	133	/* Start up the PHY */
	134	if (phy_startup(priv->phydev)) {
	135	printf("Could not initialize PHY %s\n",
	136	priv->phydev->dev->name);
	137	return -1;
	138	}
	139	speed = priv->phydev->speed;
	140	printf("Speed detected %x\n", speed);
	141	if (priv->phydev->duplex == DUPLEX_HALF) {
	142	printf("Half duplex not supported\n");
	143	return -1;
	144	}
	145	#endif
	146
	147	pfe_gemac_set_speed(gem->gemac_base, speed);
	148
	149	/* Enable GPI */
	150	gpi_enable(gem->egpi_base);
	151
	152	/* Enable GEMAC */
	153	pfe_gemac_enable(gem->gemac_base);
	154
	155	return 0;
	156	}
	157
	158	static int pfe_eth_send(struct udevice dev, void packet, int length)
	159	{
0fd3d911	160	struct pfe_eth_dev priv = (struct pfe_eth_dev )dev_get_priv(dev);
a4a40437 CJ	161
	162	int rc;
	163	int i = 0;
	164
	165	rc = pfe_send(priv->gemac_port, packet, length);
	166
	167	if (rc < 0) {
	168	printf("Tx Queue full\n");
	169	return rc;
	170	}
	171
	172	while (1) {
	173	rc = pfe_tx_done();
	174	if (rc == 0)
	175	break;
	176
	177	udelay(100);
	178	i++;
0649ab49	179	if (i == 30000) {
a4a40437	180	printf("Tx timeout, send failed\n");
0649ab49 CS	181	break;
0649ab49 CS	182	}
a4a40437 CJ	183	}
	184
	185	return 0;
	186	}
	187
	188	static int pfe_eth_recv(struct udevice dev, int flags, uchar *packetp)
	189	{
	190	struct pfe_eth_dev *priv = dev_get_priv(dev);
	191	uchar *pkt_buf;
	192	int len;
	193	int phy_port;
	194
	195	len = pfe_recv(&pkt_buf, &phy_port);
	196
	197	if (len == 0)
	198	return -EAGAIN; /* no packet in rx */
	199	else if (len < 0)
	200	return -EAGAIN;
	201
	202	debug("Rx pkt: pkt_buf(0x%p), phy_port(%d), len(%d)\n", pkt_buf,
	203	phy_port, len);
	204	if (phy_port != priv->gemac_port) {
	205	printf("Rx pkt not on expected port\n");
	206	return -EAGAIN;
	207	}
	208
	209	*packetp = pkt_buf;
	210
	211	return len;
	212	}
	213
	214	static int pfe_eth_probe(struct udevice *dev)
	215	{
	216	struct pfe_eth_dev *priv = dev_get_priv(dev);
ad827727	217	struct pfe_ddr_address pfe_addr;
c69cda25	218	struct pfe_eth_pdata *pdata = dev_get_plat(dev);
a4a40437 CJ	219	int ret = 0;
	220	static int init_done;
	221
	222	if (!init_done) {
ad827727	223	pfe_addr.ddr_pfe_baseaddr =
a4a40437	224	(void *)pdata->pfe_ddr_addr.ddr_pfe_baseaddr;
ad827727	225	pfe_addr.ddr_pfe_phys_baseaddr =
a4a40437 CJ	226	(unsigned long)pdata->pfe_ddr_addr.ddr_pfe_phys_baseaddr;
	227
	228	debug("ddr_pfe_baseaddr: %p, ddr_pfe_phys_baseaddr: %08x\n",
ad827727 CS	229	pfe_addr.ddr_pfe_baseaddr,
ad827727 CS	230	(u32)pfe_addr.ddr_pfe_phys_baseaddr);
a4a40437	231
ad827727	232	ret = pfe_drv_init(&pfe_addr);
a4a40437 CJ	233	if (ret)
	234	return ret;
	235
	236	init_pfe_scfg_dcfg_regs();
	237	init_done = 1;
	238	}
	239
	240	priv->gemac_port = pdata->pfe_eth_pdata_mac.phy_interface;
	241	priv->gem = &gem_info[priv->gemac_port];
	242	priv->dev = dev;
	243
	244	switch (priv->gemac_port) {
	245	case EMAC_PORT_0:
	246	default:
	247	priv->gem->gemac_base = EMAC1_BASE_ADDR;
	248	priv->gem->egpi_base = EGPI1_BASE_ADDR;
	249	break;
	250	case EMAC_PORT_1:
	251	priv->gem->gemac_base = EMAC2_BASE_ADDR;
	252	priv->gem->egpi_base = EGPI2_BASE_ADDR;
	253	break;
	254	}
	255
	256	ret = pfe_eth_board_init(dev);
	257	if (ret)
	258	return ret;
	259
	260	#if defined(CONFIG_PHYLIB)
	261	ret = pfe_phy_configure(priv, pdata->pfe_eth_pdata_mac.phy_interface,
	262	gem_info[priv->gemac_port].phy_address);
	263	#endif
	264	return ret;
	265	}
	266
	267	static int pfe_eth_bind(struct udevice *dev)
	268	{
c69cda25	269	struct pfe_eth_pdata *pdata = dev_get_plat(dev);
a4a40437 CJ	270	char name[20];
	271
	272	sprintf(name, "pfe_eth%u", pdata->pfe_eth_pdata_mac.phy_interface);
	273
	274	return device_set_name(dev, name);
	275	}
	276
	277	static const struct eth_ops pfe_eth_ops = {
	278	.start = pfe_eth_start,
	279	.send = pfe_eth_send,
	280	.recv = pfe_eth_recv,
	281	.free_pkt = pfe_eth_free_pkt,
	282	.stop = pfe_eth_stop,
	283	.write_hwaddr = pfe_eth_write_hwaddr,
	284	};
	285
	286	U_BOOT_DRIVER(pfe_eth) = {
	287	.name = "pfe_eth",
	288	.id = UCLASS_ETH,
	289	.bind = pfe_eth_bind,
	290	.probe = pfe_eth_probe,
	291	.remove = pfe_eth_remove,
	292	.ops = &pfe_eth_ops,
41575d8e	293	.priv_auto = sizeof(struct pfe_eth_dev),
caa4daa2	294	.plat_auto = sizeof(struct pfe_eth_pdata)
a4a40437	295	};