[thirdparty/u-boot.git] / drivers / net / phy / intel_xway.c

// SPDX-License-Identifier: GPL-2.0+
#include <common.h>
#include <phy.h>
#include <linux/bitfield.h>

#define XWAY_MDIO_MIICTRL		0x17	/* mii control */

#define XWAY_MDIO_MIICTRL_RXSKEW_MASK	GENMASK(14, 12)
#define XWAY_MDIO_MIICTRL_TXSKEW_MASK	GENMASK(10, 8)

static int xway_config(struct phy_device *phydev)
{
	ofnode node = phy_get_ofnode(phydev);
	u32 val = 0;

	if (ofnode_valid(node)) {
		u32 rx_delay, tx_delay;

		rx_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", 2000);
		tx_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", 2000);
		val |= FIELD_PREP(XWAY_MDIO_MIICTRL_TXSKEW_MASK, rx_delay / 500);
		val |= FIELD_PREP(XWAY_MDIO_MIICTRL_RXSKEW_MASK, tx_delay / 500);
		phy_modify(phydev, MDIO_DEVAD_NONE, XWAY_MDIO_MIICTRL,
			   XWAY_MDIO_MIICTRL_TXSKEW_MASK |
			   XWAY_MDIO_MIICTRL_RXSKEW_MASK, val);
	}

	genphy_config_aneg(phydev);

	return 0;
}

U_BOOT_PHY_DRIVER(xway) = {
	.name = "XWAY",
	.uid = 0xD565A400,
	.mask = 0xffffff00,
	.features = PHY_GBIT_FEATURES,
	.config = xway_config,
	.startup = genphy_startup,
	.shutdown = genphy_shutdown,
};
Commit	Line	Data
5e6c069b	1	// SPDX-License-Identifier: GPL-2.0+
d678a59d	2	#include <common.h>
5e6c069b TH	3	#include <phy.h>
	4	#include <linux/bitfield.h>
	5
	6	#define XWAY_MDIO_MIICTRL 0x17 /* mii control */
	7
	8	#define XWAY_MDIO_MIICTRL_RXSKEW_MASK GENMASK(14, 12)
	9	#define XWAY_MDIO_MIICTRL_TXSKEW_MASK GENMASK(10, 8)
	10
	11	static int xway_config(struct phy_device *phydev)
	12	{
	13	ofnode node = phy_get_ofnode(phydev);
	14	u32 val = 0;
	15
	16	if (ofnode_valid(node)) {
	17	u32 rx_delay, tx_delay;
	18
	19	rx_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", 2000);
	20	tx_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", 2000);
	21	val \|= FIELD_PREP(XWAY_MDIO_MIICTRL_TXSKEW_MASK, rx_delay / 500);
	22	val \|= FIELD_PREP(XWAY_MDIO_MIICTRL_RXSKEW_MASK, tx_delay / 500);
	23	phy_modify(phydev, MDIO_DEVAD_NONE, XWAY_MDIO_MIICTRL,
	24	XWAY_MDIO_MIICTRL_TXSKEW_MASK \|
	25	XWAY_MDIO_MIICTRL_RXSKEW_MASK, val);
	26	}
	27
	28	genphy_config_aneg(phydev);
	29
	30	return 0;
	31	}
	32
330d64f5	33	U_BOOT_PHY_DRIVER(xway) = {
5e6c069b TH	34	.name = "XWAY",
	35	.uid = 0xD565A400,
	36	.mask = 0xffffff00,
	37	.features = PHY_GBIT_FEATURES,
	38	.config = xway_config,
	39	.startup = genphy_startup,
	40	.shutdown = genphy_shutdown,
	41	};