[people/ms/u-boot.git] / drivers / net / phy / marvell.c

/*
 * Marvell PHY drivers
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Copyright 2010-2011 Freescale Semiconductor, Inc.
 * author Andy Fleming
 */
#include <config.h>
#include <common.h>
#include <phy.h>

#define PHY_AUTONEGOTIATE_TIMEOUT 5000

/* 88E1011 PHY Status Register */
#define MIIM_88E1xxx_PHY_STATUS		0x11
#define MIIM_88E1xxx_PHYSTAT_SPEED	0xc000
#define MIIM_88E1xxx_PHYSTAT_GBIT	0x8000
#define MIIM_88E1xxx_PHYSTAT_100	0x4000
#define MIIM_88E1xxx_PHYSTAT_DUPLEX	0x2000
#define MIIM_88E1xxx_PHYSTAT_SPDDONE	0x0800
#define MIIM_88E1xxx_PHYSTAT_LINK	0x0400

#define MIIM_88E1xxx_PHY_SCR		0x10
#define MIIM_88E1xxx_PHY_MDI_X_AUTO	0x0060

/* 88E1111 PHY LED Control Register */
#define MIIM_88E1111_PHY_LED_CONTROL	24
#define MIIM_88E1111_PHY_LED_DIRECT	0x4100
#define MIIM_88E1111_PHY_LED_COMBINE	0x411C

/* 88E1111 Extended PHY Specific Control Register */
#define MIIM_88E1111_PHY_EXT_CR		0x14
#define MIIM_88E1111_RX_DELAY		0x80
#define MIIM_88E1111_TX_DELAY		0x2

/* 88E1111 Extended PHY Specific Status Register */
#define MIIM_88E1111_PHY_EXT_SR		0x1b
#define MIIM_88E1111_HWCFG_MODE_MASK		0xf
#define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII	0xb
#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII	0x3
#define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK	0x4
#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI	0x9
#define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO	0x8000
#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES	0x2000

#define MIIM_88E1111_COPPER		0
#define MIIM_88E1111_FIBER		1

/* 88E1118 PHY defines */
#define MIIM_88E1118_PHY_PAGE		22
#define MIIM_88E1118_PHY_LED_PAGE	3

/* 88E1121 PHY LED Control Register */
#define MIIM_88E1121_PHY_LED_CTRL	16
#define MIIM_88E1121_PHY_LED_PAGE	3
#define MIIM_88E1121_PHY_LED_DEF	0x0030

/* 88E1121 PHY IRQ Enable/Status Register */
#define MIIM_88E1121_PHY_IRQ_EN		18
#define MIIM_88E1121_PHY_IRQ_STATUS	19

#define MIIM_88E1121_PHY_PAGE		22

/* 88E1145 Extended PHY Specific Control Register */
#define MIIM_88E1145_PHY_EXT_CR 20
#define MIIM_M88E1145_RGMII_RX_DELAY	0x0080
#define MIIM_M88E1145_RGMII_TX_DELAY	0x0002

#define MIIM_88E1145_PHY_LED_CONTROL	24
#define MIIM_88E1145_PHY_LED_DIRECT	0x4100

#define MIIM_88E1145_PHY_PAGE	29
#define MIIM_88E1145_PHY_CAL_OV 30

#define MIIM_88E1149_PHY_PAGE	29

/* 88E1310 PHY defines */
#define MIIM_88E1310_PHY_LED_CTRL	16
#define MIIM_88E1310_PHY_IRQ_EN		18
#define MIIM_88E1310_PHY_RGMII_CTRL	21
#define MIIM_88E1310_PHY_PAGE		22

/* Marvell 88E1011S */
static int m88e1011s_config(struct phy_device *phydev)
{
	/* Reset and configure the PHY */
	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);

	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);

	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);

	genphy_config_aneg(phydev);

	return 0;
}

/* Parse the 88E1011's status register for speed and duplex
 * information
 */
static uint m88e1xxx_parse_status(struct phy_device *phydev)
{
	unsigned int speed;
	unsigned int mii_reg;

	mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);

	if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
		!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
		int i = 0;

		puts("Waiting for PHY realtime link");
		while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
			/* Timeout reached ? */
			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
				puts(" TIMEOUT !\n");
				phydev->link = 0;
				break;
			}

			if ((i++ % 1000) == 0)
				putc('.');
			udelay(1000);
			mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
					MIIM_88E1xxx_PHY_STATUS);
		}
		puts(" done\n");
		udelay(500000);	/* another 500 ms (results in faster booting) */
	} else {
		if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
			phydev->link = 1;
		else
			phydev->link = 0;
	}

	if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
		phydev->duplex = DUPLEX_FULL;
	else
		phydev->duplex = DUPLEX_HALF;

	speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;

	switch (speed) {
	case MIIM_88E1xxx_PHYSTAT_GBIT:
		phydev->speed = SPEED_1000;
		break;
	case MIIM_88E1xxx_PHYSTAT_100:
		phydev->speed = SPEED_100;
		break;
	default:
		phydev->speed = SPEED_10;
		break;
	}

	return 0;
}

static int m88e1011s_startup(struct phy_device *phydev)
{
	genphy_update_link(phydev);
	m88e1xxx_parse_status(phydev);

	return 0;
}

/* Marvell 88E1111S */
static int m88e1111s_config(struct phy_device *phydev)
{
	int reg;
	int timeout;

	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
			(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
			(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
			(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
		reg = phy_read(phydev,
			MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
		if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
			(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
			reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
		} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
			reg &= ~MIIM_88E1111_TX_DELAY;
			reg |= MIIM_88E1111_RX_DELAY;
		} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
			reg &= ~MIIM_88E1111_RX_DELAY;
			reg |= MIIM_88E1111_TX_DELAY;
		}

		phy_write(phydev,
			MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);

		reg = phy_read(phydev,
			MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);

		reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);

		if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
			reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
		else
			reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;

		phy_write(phydev,
			MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
	}

	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
		reg = phy_read(phydev,
			MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);

		reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
		reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
		reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;

		phy_write(phydev, MDIO_DEVAD_NONE,
			MIIM_88E1111_PHY_EXT_SR, reg);
	}

	if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
		reg = phy_read(phydev,
			MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
		reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
		phy_write(phydev,
			MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);

		reg = phy_read(phydev, MDIO_DEVAD_NONE,
			MIIM_88E1111_PHY_EXT_SR);
		reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
			MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
		reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
		phy_write(phydev, MDIO_DEVAD_NONE,
			MIIM_88E1111_PHY_EXT_SR, reg);

		/* soft reset */
		timeout = 1000;
		phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
		udelay(1000);
		reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
		while ((reg & BMCR_RESET) && --timeout) {
			udelay(1000);
			reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
		}
		if (!timeout)
			printf("%s: phy soft reset timeout\n", __func__);

		reg = phy_read(phydev, MDIO_DEVAD_NONE,
			MIIM_88E1111_PHY_EXT_SR);
		reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
			MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
		reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
			MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
		phy_write(phydev, MDIO_DEVAD_NONE,
			MIIM_88E1111_PHY_EXT_SR, reg);
	}

	/* soft reset */
	timeout = 1000;
	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
	udelay(1000);
	reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
	while ((reg & BMCR_RESET) && --timeout) {
		udelay(1000);
		reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
	}
	if (!timeout)
		printf("%s: phy soft reset timeout\n", __func__);

	genphy_config_aneg(phydev);

	phy_reset(phydev);

	return 0;
}

/* Marvell 88E1118 */
static int m88e1118_config(struct phy_device *phydev)
{
	/* Change Page Number */
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
	/* Delay RGMII TX and RX */
	phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
	/* Change Page Number */
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
	/* Adjust LED control */
	phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
	/* Change Page Number */
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);

	genphy_config_aneg(phydev);

	phy_reset(phydev);

	return 0;
}

static int m88e1118_startup(struct phy_device *phydev)
{
	/* Change Page Number */
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);

	genphy_update_link(phydev);
	m88e1xxx_parse_status(phydev);

	return 0;
}

/* Marvell 88E1121R */
static int m88e1121_config(struct phy_device *phydev)
{
	int pg;

	/* Configure the PHY */
	genphy_config_aneg(phydev);

	/* Switch the page to access the led register */
	pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
			MIIM_88E1121_PHY_LED_PAGE);
	/* Configure leds */
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
			MIIM_88E1121_PHY_LED_DEF);
	/* Restore the page pointer */
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);

	/* Disable IRQs and de-assert interrupt */
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
	phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);

	return 0;
}

/* Marvell 88E1145 */
static int m88e1145_config(struct phy_device *phydev)
{
	int reg;

	/* Errata E0, E1 */
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);

	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
			MIIM_88E1xxx_PHY_MDI_X_AUTO);

	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
		reg |= MIIM_M88E1145_RGMII_RX_DELAY |
			MIIM_M88E1145_RGMII_TX_DELAY;
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);

	genphy_config_aneg(phydev);

	phy_reset(phydev);

	return 0;
}

static int m88e1145_startup(struct phy_device *phydev)
{
	genphy_update_link(phydev);
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
			MIIM_88E1145_PHY_LED_DIRECT);
	m88e1xxx_parse_status(phydev);

	return 0;
}

/* Marvell 88E1149S */
static int m88e1149_config(struct phy_device *phydev)
{
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);

	genphy_config_aneg(phydev);

	phy_reset(phydev);

	return 0;
}

/* Marvell 88E1310 */
static int m88e1310_config(struct phy_device *phydev)
{
	u16 reg;

	/* LED link and activity */
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
	reg = (reg & ~0xf) | 0x1;
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);

	/* Set LED2/INT to INT mode, low active */
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
	reg = (reg & 0x77ff) | 0x0880;
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);

	/* Set RGMII delay */
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
	reg |= 0x0030;
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);

	/* Ensure to return to page 0 */
	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);

	genphy_config_aneg(phydev);
	phy_reset(phydev);

	return 0;
}

static struct phy_driver M88E1011S_driver = {
	.name = "Marvell 88E1011S",
	.uid = 0x1410c60,
	.mask = 0xffffff0,
	.features = PHY_GBIT_FEATURES,
	.config = &m88e1011s_config,
	.startup = &m88e1011s_startup,
	.shutdown = &genphy_shutdown,
};

static struct phy_driver M88E1111S_driver = {
	.name = "Marvell 88E1111S",
	.uid = 0x1410cc0,
	.mask = 0xffffff0,
	.features = PHY_GBIT_FEATURES,
	.config = &m88e1111s_config,
	.startup = &m88e1011s_startup,
	.shutdown = &genphy_shutdown,
};

static struct phy_driver M88E1118_driver = {
	.name = "Marvell 88E1118",
	.uid = 0x1410e10,
	.mask = 0xffffff0,
	.features = PHY_GBIT_FEATURES,
	.config = &m88e1118_config,
	.startup = &m88e1118_startup,
	.shutdown = &genphy_shutdown,
};

static struct phy_driver M88E1118R_driver = {
	.name = "Marvell 88E1118R",
	.uid = 0x1410e40,
	.mask = 0xffffff0,
	.features = PHY_GBIT_FEATURES,
	.config = &m88e1118_config,
	.startup = &m88e1118_startup,
	.shutdown = &genphy_shutdown,
};

static struct phy_driver M88E1121R_driver = {
	.name = "Marvell 88E1121R",
	.uid = 0x1410cb0,
	.mask = 0xffffff0,
	.features = PHY_GBIT_FEATURES,
	.config = &m88e1121_config,
	.startup = &genphy_startup,
	.shutdown = &genphy_shutdown,
};

static struct phy_driver M88E1145_driver = {
	.name = "Marvell 88E1145",
	.uid = 0x1410cd0,
	.mask = 0xffffff0,
	.features = PHY_GBIT_FEATURES,
	.config = &m88e1145_config,
	.startup = &m88e1145_startup,
	.shutdown = &genphy_shutdown,
};

static struct phy_driver M88E1149S_driver = {
	.name = "Marvell 88E1149S",
	.uid = 0x1410ca0,
	.mask = 0xffffff0,
	.features = PHY_GBIT_FEATURES,
	.config = &m88e1149_config,
	.startup = &m88e1011s_startup,
	.shutdown = &genphy_shutdown,
};

static struct phy_driver M88E1518_driver = {
	.name = "Marvell 88E1518",
	.uid = 0x1410dd1,
	.mask = 0xffffff0,
	.features = PHY_GBIT_FEATURES,
	.config = &m88e1111s_config,
	.startup = &m88e1011s_startup,
	.shutdown = &genphy_shutdown,
};

static struct phy_driver M88E1310_driver = {
	.name = "Marvell 88E1310",
	.uid = 0x01410e90,
	.mask = 0xffffff0,
	.features = PHY_GBIT_FEATURES,
	.config = &m88e1310_config,
	.startup = &m88e1011s_startup,
	.shutdown = &genphy_shutdown,
};

int phy_marvell_init(void)
{
	phy_register(&M88E1310_driver);
	phy_register(&M88E1149S_driver);
	phy_register(&M88E1145_driver);
	phy_register(&M88E1121R_driver);
	phy_register(&M88E1118_driver);
	phy_register(&M88E1118R_driver);
	phy_register(&M88E1111S_driver);
	phy_register(&M88E1011S_driver);
	phy_register(&M88E1518_driver);

	return 0;
}
Commit	Line	Data
9082eeac AF	1	/*
	2	* Marvell PHY drivers
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
9082eeac AF	5	*
	6	* Copyright 2010-2011 Freescale Semiconductor, Inc.
	7	* author Andy Fleming
9082eeac AF	8	*/
	9	#include <config.h>
	10	#include <common.h>
	11	#include <phy.h>
	12
	13	#define PHY_AUTONEGOTIATE_TIMEOUT 5000
	14
	15	/* 88E1011 PHY Status Register */
	16	#define MIIM_88E1xxx_PHY_STATUS 0x11
	17	#define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
	18	#define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
	19	#define MIIM_88E1xxx_PHYSTAT_100 0x4000
	20	#define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
	21	#define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
	22	#define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
	23
	24	#define MIIM_88E1xxx_PHY_SCR 0x10
	25	#define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
	26
	27	/* 88E1111 PHY LED Control Register */
	28	#define MIIM_88E1111_PHY_LED_CONTROL 24
	29	#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
	30	#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
	31
fa12a08e ZRR	32	/* 88E1111 Extended PHY Specific Control Register */
	33	#define MIIM_88E1111_PHY_EXT_CR 0x14
	34	#define MIIM_88E1111_RX_DELAY 0x80
	35	#define MIIM_88E1111_TX_DELAY 0x2
	36
	37	/* 88E1111 Extended PHY Specific Status Register */
	38	#define MIIM_88E1111_PHY_EXT_SR 0x1b
	39	#define MIIM_88E1111_HWCFG_MODE_MASK 0xf
	40	#define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
	41	#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
	42	#define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
	43	#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
	44	#define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
	45	#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
	46
	47	#define MIIM_88E1111_COPPER 0
	48	#define MIIM_88E1111_FIBER 1
	49
9082eeac AF	50	/* 88E1118 PHY defines */
	51	#define MIIM_88E1118_PHY_PAGE 22
	52	#define MIIM_88E1118_PHY_LED_PAGE 3
	53
	54	/* 88E1121 PHY LED Control Register */
	55	#define MIIM_88E1121_PHY_LED_CTRL 16
	56	#define MIIM_88E1121_PHY_LED_PAGE 3
	57	#define MIIM_88E1121_PHY_LED_DEF 0x0030
	58
	59	/* 88E1121 PHY IRQ Enable/Status Register */
	60	#define MIIM_88E1121_PHY_IRQ_EN 18
	61	#define MIIM_88E1121_PHY_IRQ_STATUS 19
	62
	63	#define MIIM_88E1121_PHY_PAGE 22
	64
	65	/* 88E1145 Extended PHY Specific Control Register */
	66	#define MIIM_88E1145_PHY_EXT_CR 20
	67	#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
	68	#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
	69
	70	#define MIIM_88E1145_PHY_LED_CONTROL 24
	71	#define MIIM_88E1145_PHY_LED_DIRECT 0x4100
	72
	73	#define MIIM_88E1145_PHY_PAGE 29
	74	#define MIIM_88E1145_PHY_CAL_OV 30
	75
	76	#define MIIM_88E1149_PHY_PAGE 29
	77
aeceec0d SH	78	/* 88E1310 PHY defines */
	79	#define MIIM_88E1310_PHY_LED_CTRL 16
	80	#define MIIM_88E1310_PHY_IRQ_EN 18
	81	#define MIIM_88E1310_PHY_RGMII_CTRL 21
	82	#define MIIM_88E1310_PHY_PAGE 22
	83
9082eeac AF	84	/* Marvell 88E1011S */
	85	static int m88e1011s_config(struct phy_device *phydev)
	86	{
	87	/* Reset and configure the PHY */
	88	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
	89
	90	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
	91	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
	92	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	93	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
	94	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
	95
	96	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
	97
	98	genphy_config_aneg(phydev);
	99
	100	return 0;
	101	}
	102
	103	/* Parse the 88E1011's status register for speed and duplex
	104	* information
	105	*/
	106	static uint m88e1xxx_parse_status(struct phy_device *phydev)
	107	{
	108	unsigned int speed;
	109	unsigned int mii_reg;
	110
	111	mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
	112
	113	if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
	114	!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
	115	int i = 0;
	116
	117	puts("Waiting for PHY realtime link");
	118	while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
	119	/* Timeout reached ? */
	120	if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
	121	puts(" TIMEOUT !\n");
	122	phydev->link = 0;
	123	break;
	124	}
	125
	126	if ((i++ % 1000) == 0)
	127	putc('.');
	128	udelay(1000);
	129	mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
	130	MIIM_88E1xxx_PHY_STATUS);
	131	}
	132	puts(" done\n");
	133	udelay(500000); /* another 500 ms (results in faster booting) */
	134	} else {
	135	if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
	136	phydev->link = 1;
	137	else
	138	phydev->link = 0;
	139	}
	140
	141	if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
	142	phydev->duplex = DUPLEX_FULL;
	143	else
	144	phydev->duplex = DUPLEX_HALF;
	145
	146	speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
	147
148	switch (speed) {
149	case MIIM_88E1xxx_PHYSTAT_GBIT:
150	phydev->speed = SPEED_1000;
151	break;
152	case MIIM_88E1xxx_PHYSTAT_100:
153	phydev->speed = SPEED_100;
154	break;
155	default:
156	phydev->speed = SPEED_10;
157	break;
158	}
159
160	return 0;
161	}
162
163	static int m88e1011s_startup(struct phy_device *phydev)
164	{
165	genphy_update_link(phydev);
166	m88e1xxx_parse_status(phydev);
167
168	return 0;
169	}
170
171	/* Marvell 88E1111S */
172	static int m88e1111s_config(struct phy_device *phydev)
173	{
174	int reg;
fa12a08e	175	int timeout;
9082eeac AF	176
	177	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) \|\|
	178	(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) \|\|
	179	(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) \|\|
	180	(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
fa12a08e ZRR	181	reg = phy_read(phydev,
	182	MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
	183	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) \|\|
	184	(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
	185	reg \|= (MIIM_88E1111_RX_DELAY \| MIIM_88E1111_TX_DELAY);
	186	} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
	187	reg &= ~MIIM_88E1111_TX_DELAY;
	188	reg \|= MIIM_88E1111_RX_DELAY;
	189	} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
	190	reg &= ~MIIM_88E1111_RX_DELAY;
	191	reg \|= MIIM_88E1111_TX_DELAY;
	192	}
	193
	194	phy_write(phydev,
	195	MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
	196
	197	reg = phy_read(phydev,
	198	MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
	199
	200	reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
	201
	202	if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
	203	reg \|= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
	204	else
	205	reg \|= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
	206
	207	phy_write(phydev,
	208	MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
9082eeac AF	209	}
9082eeac AF	210
fa12a08e ZRR	211	if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
	212	reg = phy_read(phydev,
	213	MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
	214
	215	reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
	216	reg \|= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
	217	reg \|= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
	218
	219	phy_write(phydev, MDIO_DEVAD_NONE,
	220	MIIM_88E1111_PHY_EXT_SR, reg);
	221	}
	222
	223	if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
	224	reg = phy_read(phydev,
	225	MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
	226	reg \|= (MIIM_88E1111_RX_DELAY \| MIIM_88E1111_TX_DELAY);
	227	phy_write(phydev,
	228	MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
	229
	230	reg = phy_read(phydev, MDIO_DEVAD_NONE,
	231	MIIM_88E1111_PHY_EXT_SR);
	232	reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK \|
	233	MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
	234	reg \|= 0x7 \| MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
	235	phy_write(phydev, MDIO_DEVAD_NONE,
	236	MIIM_88E1111_PHY_EXT_SR, reg);
	237
	238	/* soft reset */
	239	timeout = 1000;
	240	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
	241	udelay(1000);
	242	reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
	243	while ((reg & BMCR_RESET) && --timeout) {
	244	udelay(1000);
	245	reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
	246	}
	247	if (!timeout)
	248	printf("%s: phy soft reset timeout\n", __func__);
	249
	250	reg = phy_read(phydev, MDIO_DEVAD_NONE,
	251	MIIM_88E1111_PHY_EXT_SR);
	252	reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK \|
	253	MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
	254	reg \|= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI \|
	255	MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
	256	phy_write(phydev, MDIO_DEVAD_NONE,
	257	MIIM_88E1111_PHY_EXT_SR, reg);
	258	}
	259
	260	/* soft reset */
	261	timeout = 1000;
	262	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
	263	udelay(1000);
	264	reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
	265	while ((reg & BMCR_RESET) && --timeout) {
	266	udelay(1000);
	267	reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
	268	}
	269	if (!timeout)
	270	printf("%s: phy soft reset timeout\n", __func__);
9082eeac AF	271
	272	genphy_config_aneg(phydev);
	273
	274	phy_reset(phydev);
	275
	276	return 0;
	277	}
	278
	279	/* Marvell 88E1118 */
	280	static int m88e1118_config(struct phy_device *phydev)
	281	{
	282	/* Change Page Number */
	283	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
	284	/* Delay RGMII TX and RX */
	285	phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
	286	/* Change Page Number */
	287	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
	288	/* Adjust LED control */
	289	phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
	290	/* Change Page Number */
	291	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
	292
	293	genphy_config_aneg(phydev);
	294
	295	phy_reset(phydev);
	296
	297	return 0;
	298	}
	299
	300	static int m88e1118_startup(struct phy_device *phydev)
	301	{
	302	/* Change Page Number */
	303	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
	304
	305	genphy_update_link(phydev);
	306	m88e1xxx_parse_status(phydev);
	307
	308	return 0;
	309	}
	310
	311	/* Marvell 88E1121R */
	312	static int m88e1121_config(struct phy_device *phydev)
	313	{
	314	int pg;
	315
	316	/* Configure the PHY */
	317	genphy_config_aneg(phydev);
	318
	319	/* Switch the page to access the led register */
	320	pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
	321	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
	322	MIIM_88E1121_PHY_LED_PAGE);
	323	/* Configure leds */
	324	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
	325	MIIM_88E1121_PHY_LED_DEF);
	326	/* Restore the page pointer */
	327	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
	328
	329	/* Disable IRQs and de-assert interrupt */
	330	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
	331	phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
	332
	333	return 0;
	334	}
335
336	/* Marvell 88E1145 */
337	static int m88e1145_config(struct phy_device *phydev)
338	{
339	int reg;
340
341	/* Errata E0, E1 */
342	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
343	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
344	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
345	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
346
347	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
348	MIIM_88E1xxx_PHY_MDI_X_AUTO);
349
350	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
351	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
352	reg \|= MIIM_M88E1145_RGMII_RX_DELAY \|
353	MIIM_M88E1145_RGMII_TX_DELAY;
354	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
355
356	genphy_config_aneg(phydev);
357
358	phy_reset(phydev);
359
360	return 0;
361	}
362
363	static int m88e1145_startup(struct phy_device *phydev)
364	{
365	genphy_update_link(phydev);
366	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
367	MIIM_88E1145_PHY_LED_DIRECT);
368	m88e1xxx_parse_status(phydev);
369
370	return 0;
371	}
372
373	/* Marvell 88E1149S */
374	static int m88e1149_config(struct phy_device *phydev)
375	{
376	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
377	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
378	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
379	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
380	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
381
382	genphy_config_aneg(phydev);
383
384	phy_reset(phydev);
385
386	return 0;
387	}
388
aeceec0d SH	389	/* Marvell 88E1310 */
	390	static int m88e1310_config(struct phy_device *phydev)
	391	{
	392	u16 reg;
	393
	394	/* LED link and activity */
	395	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
	396	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
	397	reg = (reg & ~0xf) \| 0x1;
	398	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
	399
	400	/* Set LED2/INT to INT mode, low active */
	401	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
	402	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
	403	reg = (reg & 0x77ff) \| 0x0880;
	404	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
	405
	406	/* Set RGMII delay */
	407	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
	408	reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
	409	reg \|= 0x0030;
	410	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
	411
	412	/* Ensure to return to page 0 */
	413	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
	414
	415	genphy_config_aneg(phydev);
	416	phy_reset(phydev);
	417
	418	return 0;
	419	}
9082eeac AF	420
	421	static struct phy_driver M88E1011S_driver = {
	422	.name = "Marvell 88E1011S",
	423	.uid = 0x1410c60,
	424	.mask = 0xffffff0,
	425	.features = PHY_GBIT_FEATURES,
	426	.config = &m88e1011s_config,
	427	.startup = &m88e1011s_startup,
	428	.shutdown = &genphy_shutdown,
	429	};
	430
	431	static struct phy_driver M88E1111S_driver = {
	432	.name = "Marvell 88E1111S",
	433	.uid = 0x1410cc0,
	434	.mask = 0xffffff0,
	435	.features = PHY_GBIT_FEATURES,
	436	.config = &m88e1111s_config,
	437	.startup = &m88e1011s_startup,
	438	.shutdown = &genphy_shutdown,
	439	};
	440
	441	static struct phy_driver M88E1118_driver = {
	442	.name = "Marvell 88E1118",
	443	.uid = 0x1410e10,
	444	.mask = 0xffffff0,
	445	.features = PHY_GBIT_FEATURES,
	446	.config = &m88e1118_config,
	447	.startup = &m88e1118_startup,
	448	.shutdown = &genphy_shutdown,
	449	};
	450
b4b81e83 MS	451	static struct phy_driver M88E1118R_driver = {
	452	.name = "Marvell 88E1118R",
	453	.uid = 0x1410e40,
	454	.mask = 0xffffff0,
	455	.features = PHY_GBIT_FEATURES,
	456	.config = &m88e1118_config,
	457	.startup = &m88e1118_startup,
	458	.shutdown = &genphy_shutdown,
	459	};
	460
9082eeac AF	461	static struct phy_driver M88E1121R_driver = {
	462	.name = "Marvell 88E1121R",
	463	.uid = 0x1410cb0,
	464	.mask = 0xffffff0,
	465	.features = PHY_GBIT_FEATURES,
	466	.config = &m88e1121_config,
	467	.startup = &genphy_startup,
	468	.shutdown = &genphy_shutdown,
	469	};
	470
	471	static struct phy_driver M88E1145_driver = {
	472	.name = "Marvell 88E1145",
	473	.uid = 0x1410cd0,
	474	.mask = 0xffffff0,
	475	.features = PHY_GBIT_FEATURES,
	476	.config = &m88e1145_config,
	477	.startup = &m88e1145_startup,
	478	.shutdown = &genphy_shutdown,
	479	};
	480
	481	static struct phy_driver M88E1149S_driver = {
	482	.name = "Marvell 88E1149S",
	483	.uid = 0x1410ca0,
	484	.mask = 0xffffff0,
	485	.features = PHY_GBIT_FEATURES,
	486	.config = &m88e1149_config,
	487	.startup = &m88e1011s_startup,
	488	.shutdown = &genphy_shutdown,
	489	};
	490
1415107e MS	491	static struct phy_driver M88E1518_driver = {
	492	.name = "Marvell 88E1518",
	493	.uid = 0x1410dd1,
	494	.mask = 0xffffff0,
	495	.features = PHY_GBIT_FEATURES,
	496	.config = &m88e1111s_config,
	497	.startup = &m88e1011s_startup,
	498	.shutdown = &genphy_shutdown,
	499	};
	500
aeceec0d SH	501	static struct phy_driver M88E1310_driver = {
	502	.name = "Marvell 88E1310",
	503	.uid = 0x01410e90,
	504	.mask = 0xffffff0,
	505	.features = PHY_GBIT_FEATURES,
	506	.config = &m88e1310_config,
	507	.startup = &m88e1011s_startup,
	508	.shutdown = &genphy_shutdown,
	509	};
	510
9082eeac AF	511	int phy_marvell_init(void)
9082eeac AF	512	{
aeceec0d	513	phy_register(&M88E1310_driver);
9082eeac AF	514	phy_register(&M88E1149S_driver);
	515	phy_register(&M88E1145_driver);
	516	phy_register(&M88E1121R_driver);
	517	phy_register(&M88E1118_driver);
b4b81e83	518	phy_register(&M88E1118R_driver);
9082eeac AF	519	phy_register(&M88E1111S_driver);
9082eeac AF	520	phy_register(&M88E1011S_driver);
1415107e	521	phy_register(&M88E1518_driver);
9082eeac AF	522
	523	return 0;
	524	}