[people/ms/u-boot.git] / drivers / net / phy / micrel_ksz90x1.c

/*
 * Micrel PHY drivers
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Copyright 2010-2011 Freescale Semiconductor, Inc.
 * author Andy Fleming
 * (C) 2012 NetModule AG, David Andrey, added KSZ9031
 * (C) Copyright 2017 Adaptrum, Inc.
 * Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
 */

#include <config.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <micrel.h>
#include <phy.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * KSZ9021 - KSZ9031 common
 */

#define MII_KSZ90xx_PHY_CTL		0x1f
#define MIIM_KSZ90xx_PHYCTL_1000	(1 << 6)
#define MIIM_KSZ90xx_PHYCTL_100		(1 << 5)
#define MIIM_KSZ90xx_PHYCTL_10		(1 << 4)
#define MIIM_KSZ90xx_PHYCTL_DUPLEX	(1 << 3)

/* KSZ9021 PHY Registers */
#define MII_KSZ9021_EXTENDED_CTRL	0x0b
#define MII_KSZ9021_EXTENDED_DATAW	0x0c
#define MII_KSZ9021_EXTENDED_DATAR	0x0d

#define CTRL1000_PREFER_MASTER		(1 << 10)
#define CTRL1000_CONFIG_MASTER		(1 << 11)
#define CTRL1000_MANUAL_CONFIG		(1 << 12)

/* KSZ9031 PHY Registers */
#define MII_KSZ9031_MMD_ACCES_CTRL	0x0d
#define MII_KSZ9031_MMD_REG_DATA	0x0e

static int ksz90xx_startup(struct phy_device *phydev)
{
	unsigned phy_ctl;
	int ret;

	ret = genphy_update_link(phydev);
	if (ret)
		return ret;

	phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);

	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
		phydev->duplex = DUPLEX_FULL;
	else
		phydev->duplex = DUPLEX_HALF;

	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
		phydev->speed = SPEED_1000;
	else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
		phydev->speed = SPEED_100;
	else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
		phydev->speed = SPEED_10;
	return 0;
}

/* Common OF config bits for KSZ9021 and KSZ9031 */
#ifdef CONFIG_DM_ETH
struct ksz90x1_reg_field {
	const char	*name;
	const u8	size;	/* Size of the bitfield, in bits */
	const u8	off;	/* Offset from bit 0 */
	const u8	dflt;	/* Default value */
};

struct ksz90x1_ofcfg {
	const u16			reg;
	const u16			devad;
	const struct ksz90x1_reg_field	*grp;
	const u16			grpsz;
};

static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
	{ "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
	{ "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
};

static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
	{ "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
	{ "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
};

static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
	{ "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
	{ "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
};

static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
	{ "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
};

static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
	{ "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
};

static int ksz90x1_of_config_group(struct phy_device *phydev,
				   struct ksz90x1_ofcfg *ofcfg)
{
	struct udevice *dev = phydev->dev;
	struct phy_driver *drv = phydev->drv;
	const int ps_to_regval = 60;
	int val[4];
	int i, changed = 0, offset, max;
	u16 regval = 0;

	if (!drv || !drv->writeext)
		return -EOPNOTSUPP;

	for (i = 0; i < ofcfg->grpsz; i++) {
		val[i] = dev_read_u32_default(dev, ofcfg->grp[i].name, ~0);
		offset = ofcfg->grp[i].off;
		if (val[i] == -1) {
			/* Default register value for KSZ9021 */
			regval |= ofcfg->grp[i].dflt << offset;
		} else {
			changed = 1;	/* Value was changed in OF */
			/* Calculate the register value and fix corner cases */
			if (val[i] > ps_to_regval * 0xf) {
				max = (1 << ofcfg->grp[i].size) - 1;
				regval |= max << offset;
			} else {
				regval |= (val[i] / ps_to_regval) << offset;
			}
		}
	}

	if (!changed)
		return 0;

	return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
}

static int ksz9021_of_config(struct phy_device *phydev)
{
	struct ksz90x1_ofcfg ofcfg[] = {
		{ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
		{ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
		{ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
	};
	int i, ret = 0;

	for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
		ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
		if (ret)
			return ret;
	}

	return 0;
}

static int ksz9031_of_config(struct phy_device *phydev)
{
	struct ksz90x1_ofcfg ofcfg[] = {
		{ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
		{ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
		{ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
		{ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
	};
	int i, ret = 0;

	for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
		ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
		if (ret)
			return ret;
	}

	return 0;
}

static int ksz9031_center_flp_timing(struct phy_device *phydev)
{
	struct phy_driver *drv = phydev->drv;
	int ret = 0;

	if (!drv || !drv->writeext)
		return -EOPNOTSUPP;

	ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
	if (ret)
		return ret;

	ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
	return ret;
}

#else /* !CONFIG_DM_ETH */
static int ksz9021_of_config(struct phy_device *phydev)
{
	return 0;
}

static int ksz9031_of_config(struct phy_device *phydev)
{
	return 0;
}

static int ksz9031_center_flp_timing(struct phy_device *phydev)
{
	return 0;
}
#endif

/*
 * KSZ9021
 */
int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
{
	/* extended registers */
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
	return phy_write(phydev, MDIO_DEVAD_NONE,
			 MII_KSZ9021_EXTENDED_DATAW, val);
}

int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
{
	/* extended registers */
	phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
	return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
}


static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
			       int regnum)
{
	return ksz9021_phy_extended_read(phydev, regnum);
}

static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
				int devaddr, int regnum, u16 val)
{
	return ksz9021_phy_extended_write(phydev, regnum, val);
}

static int ksz9021_config(struct phy_device *phydev)
{
	unsigned ctrl1000 = 0;
	const unsigned master = CTRL1000_PREFER_MASTER |
	CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
	unsigned features = phydev->drv->features;
	int ret;

	ret = ksz9021_of_config(phydev);
	if (ret)
		return ret;

	if (env_get("disable_giga"))
		features &= ~(SUPPORTED_1000baseT_Half |
		SUPPORTED_1000baseT_Full);
	/* force master mode for 1000BaseT due to chip errata */
	if (features & SUPPORTED_1000baseT_Half)
		ctrl1000 |= ADVERTISE_1000HALF | master;
	if (features & SUPPORTED_1000baseT_Full)
		ctrl1000 |= ADVERTISE_1000FULL | master;
	phydev->advertising = features;
	phydev->supported = features;
	phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
	genphy_config_aneg(phydev);
	genphy_restart_aneg(phydev);
	return 0;
}

static struct phy_driver ksz9021_driver = {
	.name = "Micrel ksz9021",
	.uid  = 0x221610,
	.mask = 0xfffff0,
	.features = PHY_GBIT_FEATURES,
	.config = &ksz9021_config,
	.startup = &ksz90xx_startup,
	.shutdown = &genphy_shutdown,
	.writeext = &ksz9021_phy_extwrite,
	.readext = &ksz9021_phy_extread,
};

/*
 * KSZ9031
 */
int ksz9031_phy_extended_write(struct phy_device *phydev,
			       int devaddr, int regnum, u16 mode, u16 val)
{
	/*select register addr for mmd*/
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
	/*select register for mmd*/
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_REG_DATA, regnum);
	/*setup mode*/
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
	/*write the value*/
	return	phy_write(phydev, MDIO_DEVAD_NONE,
			  MII_KSZ9031_MMD_REG_DATA, val);
}

int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
			      int regnum, u16 mode)
{
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_REG_DATA, regnum);
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
	return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
}

static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
			       int regnum)
{
	return ksz9031_phy_extended_read(phydev, devaddr, regnum,
					 MII_KSZ9031_MOD_DATA_NO_POST_INC);
}

static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
				int devaddr, int regnum, u16 val)
{
	return ksz9031_phy_extended_write(phydev, devaddr, regnum,
					  MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
}

static int ksz9031_config(struct phy_device *phydev)
{
	int ret;

	ret = ksz9031_of_config(phydev);
	if (ret)
		return ret;
	ret = ksz9031_center_flp_timing(phydev);
	if (ret)
		return ret;

	/* add an option to disable the gigabit feature of this PHY */
	if (env_get("disable_giga")) {
		unsigned features;
		unsigned bmcr;

		/* disable speed 1000 in features supported by the PHY */
		features = phydev->drv->features;
		features &= ~(SUPPORTED_1000baseT_Half |
				SUPPORTED_1000baseT_Full);
		phydev->advertising = phydev->supported = features;

		/* disable speed 1000 in Basic Control Register */
		bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
		bmcr &= ~(1 << 6);
		phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);

		/* disable speed 1000 in 1000Base-T Control Register */
		phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);

		/* start autoneg */
		genphy_config_aneg(phydev);
		genphy_restart_aneg(phydev);

		return 0;
	}

	return genphy_config(phydev);
}

static struct phy_driver ksz9031_driver = {
	.name = "Micrel ksz9031",
	.uid  = 0x221620,
	.mask = 0xfffff0,
	.features = PHY_GBIT_FEATURES,
	.config   = &ksz9031_config,
	.startup  = &ksz90xx_startup,
	.shutdown = &genphy_shutdown,
	.writeext = &ksz9031_phy_extwrite,
	.readext = &ksz9031_phy_extread,
};

int phy_micrel_ksz90x1_init(void)
{
	phy_register(&ksz9021_driver);
	phy_register(&ksz9031_driver);
	return 0;
}
Commit	Line	Data
9082eeac AF	1	/*
	2	* Micrel PHY drivers
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
9082eeac AF	5	*
	6	* Copyright 2010-2011 Freescale Semiconductor, Inc.
	7	* author Andy Fleming
62d7dba7	8	* (C) 2012 NetModule AG, David Andrey, added KSZ9031
d397f7c4 AG	9	* (C) Copyright 2017 Adaptrum, Inc.
d397f7c4 AG	10	* Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
9082eeac	11	*/
b343837e	12
8682aba7 TK	13	#include <config.h>
8682aba7 TK	14	#include <common.h>
22854bda MV	15	#include <dm.h>
22854bda MV	16	#include <errno.h>
8682aba7	17	#include <micrel.h>
9082eeac AF	18	#include <phy.h>
9082eeac AF	19
22854bda MV	20	DECLARE_GLOBAL_DATA_PTR;
22854bda MV	21
58ec63d6	22	/*
62d7dba7 DA	23	* KSZ9021 - KSZ9031 common
	24	*/
	25
	26	#define MII_KSZ90xx_PHY_CTL 0x1f
	27	#define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
	28	#define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
	29	#define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
	30	#define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
	31
d397f7c4 AG	32	/* KSZ9021 PHY Registers */
	33	#define MII_KSZ9021_EXTENDED_CTRL 0x0b
	34	#define MII_KSZ9021_EXTENDED_DATAW 0x0c
	35	#define MII_KSZ9021_EXTENDED_DATAR 0x0d
	36
	37	#define CTRL1000_PREFER_MASTER (1 << 10)
	38	#define CTRL1000_CONFIG_MASTER (1 << 11)
	39	#define CTRL1000_MANUAL_CONFIG (1 << 12)
	40
	41	/* KSZ9031 PHY Registers */
	42	#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
	43	#define MII_KSZ9031_MMD_REG_DATA 0x0e
	44
62d7dba7 DA	45	static int ksz90xx_startup(struct phy_device *phydev)
	46	{
	47	unsigned phy_ctl;
b733c278 MS	48	int ret;
	49
	50	ret = genphy_update_link(phydev);
	51	if (ret)
	52	return ret;
	53
62d7dba7 DA	54	phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
	55
	56	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
	57	phydev->duplex = DUPLEX_FULL;
	58	else
	59	phydev->duplex = DUPLEX_HALF;
	60
	61	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
	62	phydev->speed = SPEED_1000;
	63	else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
	64	phydev->speed = SPEED_100;
	65	else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
	66	phydev->speed = SPEED_10;
	67	return 0;
	68	}
62d7dba7	69
22854bda	70	/* Common OF config bits for KSZ9021 and KSZ9031 */
22854bda MV	71	#ifdef CONFIG_DM_ETH
	72	struct ksz90x1_reg_field {
	73	const char *name;
	74	const u8 size; /* Size of the bitfield, in bits */
	75	const u8 off; /* Offset from bit 0 */
	76	const u8 dflt; /* Default value */
	77	};
	78
	79	struct ksz90x1_ofcfg {
	80	const u16 reg;
	81	const u16 devad;
	82	const struct ksz90x1_reg_field *grp;
	83	const u16 grpsz;
	84	};
	85
	86	static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
	87	{ "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
	88	{ "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
	89	};
	90
	91	static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
	92	{ "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
	93	{ "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
	94	};
	95
d397f7c4 AG	96	static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
	97	{ "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
	98	{ "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
	99	};
	100
	101	static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
	102	{ "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
	103	};
	104
	105	static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
	106	{ "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
	107	};
	108
22854bda MV	109	static int ksz90x1_of_config_group(struct phy_device *phydev,
	110	struct ksz90x1_ofcfg *ofcfg)
	111	{
	112	struct udevice *dev = phydev->dev;
	113	struct phy_driver *drv = phydev->drv;
ff7bd212	114	const int ps_to_regval = 60;
22854bda MV	115	int val[4];
	116	int i, changed = 0, offset, max;
	117	u16 regval = 0;
	118
	119	if (!drv \|\| !drv->writeext)
	120	return -EOPNOTSUPP;
	121
	122	for (i = 0; i < ofcfg->grpsz; i++) {
b343837e	123	val[i] = dev_read_u32_default(dev, ofcfg->grp[i].name, ~0);
22854bda MV	124	offset = ofcfg->grp[i].off;
	125	if (val[i] == -1) {
	126	/* Default register value for KSZ9021 */
	127	regval \|= ofcfg->grp[i].dflt << offset;
	128	} else {
	129	changed = 1; /* Value was changed in OF */
	130	/* Calculate the register value and fix corner cases */
	131	if (val[i] > ps_to_regval * 0xf) {
	132	max = (1 << ofcfg->grp[i].size) - 1;
	133	regval \|= max << offset;
	134	} else {
	135	regval \|= (val[i] / ps_to_regval) << offset;
	136	}
	137	}
	138	}
	139
	140	if (!changed)
	141	return 0;
	142
	143	return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
	144	}
22854bda MV	145
	146	static int ksz9021_of_config(struct phy_device *phydev)
	147	{
	148	struct ksz90x1_ofcfg ofcfg[] = {
	149	{ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
	150	{ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
	151	{ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
	152	};
	153	int i, ret = 0;
	154
75c056d7	155	for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
22854bda MV	156	ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
	157	if (ret)
	158	return ret;
75c056d7	159	}
22854bda MV	160
	161	return 0;
	162	}
d397f7c4 AG	163
	164	static int ksz9031_of_config(struct phy_device *phydev)
	165	{
	166	struct ksz90x1_ofcfg ofcfg[] = {
	167	{ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
	168	{ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
	169	{ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
	170	{ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
	171	};
	172	int i, ret = 0;
	173
	174	for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
	175	ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
	176	if (ret)
	177	return ret;
	178	}
	179
	180	return 0;
	181	}
	182
	183	static int ksz9031_center_flp_timing(struct phy_device *phydev)
	184	{
	185	struct phy_driver *drv = phydev->drv;
	186	int ret = 0;
	187
	188	if (!drv \|\| !drv->writeext)
	189	return -EOPNOTSUPP;
	190
	191	ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
	192	if (ret)
	193	return ret;
	194
	195	ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
	196	return ret;
	197	}
	198
	199	#else /* !CONFIG_DM_ETH */
22854bda MV	200	static int ksz9021_of_config(struct phy_device *phydev)
	201	{
	202	return 0;
	203	}
d397f7c4 AG	204
	205	static int ksz9031_of_config(struct phy_device *phydev)
	206	{
	207	return 0;
	208	}
	209
	210	static int ksz9031_center_flp_timing(struct phy_device *phydev)
	211	{
	212	return 0;
	213	}
22854bda MV	214	#endif
22854bda MV	215
d397f7c4 AG	216	/*
	217	* KSZ9021
	218	*/
8682aba7 TK	219	int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
	220	{
	221	/* extended registers */
	222	phy_write(phydev, MDIO_DEVAD_NONE,
d397f7c4	223	MII_KSZ9021_EXTENDED_CTRL, regnum \| 0x8000);
8682aba7	224	return phy_write(phydev, MDIO_DEVAD_NONE,
d397f7c4	225	MII_KSZ9021_EXTENDED_DATAW, val);
8682aba7 TK	226	}
	227
	228	int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
	229	{
	230	/* extended registers */
	231	phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
	232	return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
	233	}
	234
9ced16fe SB	235
9ced16fe SB	236	static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
d397f7c4	237	int regnum)
9ced16fe SB	238	{
	239	return ksz9021_phy_extended_read(phydev, regnum);
	240	}
	241
	242	static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
d397f7c4	243	int devaddr, int regnum, u16 val)
9ced16fe SB	244	{
	245	return ksz9021_phy_extended_write(phydev, regnum, val);
	246	}
	247
8682aba7 TK	248	static int ksz9021_config(struct phy_device *phydev)
	249	{
	250	unsigned ctrl1000 = 0;
	251	const unsigned master = CTRL1000_PREFER_MASTER \|
d397f7c4	252	CTRL1000_CONFIG_MASTER \| CTRL1000_MANUAL_CONFIG;
8682aba7	253	unsigned features = phydev->drv->features;
22854bda MV	254	int ret;
	255
	256	ret = ksz9021_of_config(phydev);
	257	if (ret)
	258	return ret;
8682aba7	259
00caae6d	260	if (env_get("disable_giga"))
8682aba7	261	features &= ~(SUPPORTED_1000baseT_Half \|
d397f7c4	262	SUPPORTED_1000baseT_Full);
8682aba7 TK	263	/* force master mode for 1000BaseT due to chip errata */
	264	if (features & SUPPORTED_1000baseT_Half)
	265	ctrl1000 \|= ADVERTISE_1000HALF \| master;
	266	if (features & SUPPORTED_1000baseT_Full)
	267	ctrl1000 \|= ADVERTISE_1000FULL \| master;
d397f7c4 AG	268	phydev->advertising = features;
d397f7c4 AG	269	phydev->supported = features;
8682aba7 TK	270	phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
	271	genphy_config_aneg(phydev);
	272	genphy_restart_aneg(phydev);
	273	return 0;
	274	}
	275
8682aba7 TK	276	static struct phy_driver ksz9021_driver = {
	277	.name = "Micrel ksz9021",
	278	.uid = 0x221610,
	279	.mask = 0xfffff0,
	280	.features = PHY_GBIT_FEATURES,
	281	.config = &ksz9021_config,
62d7dba7	282	.startup = &ksz90xx_startup,
8682aba7	283	.shutdown = &genphy_shutdown,
9ced16fe SB	284	.writeext = &ksz9021_phy_extwrite,
9ced16fe SB	285	.readext = &ksz9021_phy_extread,
8682aba7 TK	286	};
8682aba7 TK	287
d397f7c4	288	/*
62d7dba7 DA	289	* KSZ9031
62d7dba7 DA	290	*/
42a7cb50 SL	291	int ksz9031_phy_extended_write(struct phy_device *phydev,
	292	int devaddr, int regnum, u16 mode, u16 val)
	293	{
	294	/select register addr for mmd/
	295	phy_write(phydev, MDIO_DEVAD_NONE,
	296	MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
	297	/select register for mmd/
	298	phy_write(phydev, MDIO_DEVAD_NONE,
	299	MII_KSZ9031_MMD_REG_DATA, regnum);
	300	/setup mode/
	301	phy_write(phydev, MDIO_DEVAD_NONE,
	302	MII_KSZ9031_MMD_ACCES_CTRL, (mode \| devaddr));
	303	/write the value/
	304	return phy_write(phydev, MDIO_DEVAD_NONE,
d397f7c4	305	MII_KSZ9031_MMD_REG_DATA, val);
42a7cb50 SL	306	}
	307
	308	int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
	309	int regnum, u16 mode)
	310	{
	311	phy_write(phydev, MDIO_DEVAD_NONE,
	312	MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
	313	phy_write(phydev, MDIO_DEVAD_NONE,
	314	MII_KSZ9031_MMD_REG_DATA, regnum);
	315	phy_write(phydev, MDIO_DEVAD_NONE,
	316	MII_KSZ9031_MMD_ACCES_CTRL, (devaddr \| mode));
	317	return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
	318	}
	319
9ced16fe SB	320	static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
	321	int regnum)
	322	{
	323	return ksz9031_phy_extended_read(phydev, devaddr, regnum,
	324	MII_KSZ9031_MOD_DATA_NO_POST_INC);
d397f7c4	325	}
9ced16fe SB	326
	327	static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
	328	int devaddr, int regnum, u16 val)
	329	{
	330	return ksz9031_phy_extended_write(phydev, devaddr, regnum,
d397f7c4 AG	331	MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
d397f7c4 AG	332	}
9ced16fe	333
22854bda MV	334	static int ksz9031_config(struct phy_device *phydev)
	335	{
	336	int ret;
ef1f61aa	337
22854bda	338	ret = ksz9031_of_config(phydev);
f018545e AC	339	if (ret)
	340	return ret;
	341	ret = ksz9031_center_flp_timing(phydev);
22854bda MV	342	if (ret)
22854bda MV	343	return ret;
ef1f61aa SB	344
ef1f61aa SB	345	/* add an option to disable the gigabit feature of this PHY */
00caae6d	346	if (env_get("disable_giga")) {
ef1f61aa SB	347	unsigned features;
	348	unsigned bmcr;
	349
	350	/* disable speed 1000 in features supported by the PHY */
	351	features = phydev->drv->features;
	352	features &= ~(SUPPORTED_1000baseT_Half \|
	353	SUPPORTED_1000baseT_Full);
	354	phydev->advertising = phydev->supported = features;
	355
	356	/* disable speed 1000 in Basic Control Register */
	357	bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
	358	bmcr &= ~(1 << 6);
	359	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
	360
	361	/* disable speed 1000 in 1000Base-T Control Register */
	362	phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
	363
	364	/* start autoneg */
	365	genphy_config_aneg(phydev);
	366	genphy_restart_aneg(phydev);
	367
	368	return 0;
	369	}
	370
22854bda MV	371	return genphy_config(phydev);
22854bda MV	372	}
9ced16fe	373
62d7dba7 DA	374	static struct phy_driver ksz9031_driver = {
	375	.name = "Micrel ksz9031",
	376	.uid = 0x221620,
e8194d58	377	.mask = 0xfffff0,
62d7dba7	378	.features = PHY_GBIT_FEATURES,
22854bda	379	.config = &ksz9031_config,
62d7dba7 DA	380	.startup = &ksz90xx_startup,
62d7dba7 DA	381	.shutdown = &genphy_shutdown,
9ced16fe SB	382	.writeext = &ksz9031_phy_extwrite,
9ced16fe SB	383	.readext = &ksz9031_phy_extread,
62d7dba7 DA	384	};
62d7dba7 DA	385
d397f7c4	386	int phy_micrel_ksz90x1_init(void)
9082eeac	387	{
8682aba7	388	phy_register(&ksz9021_driver);
62d7dba7	389	phy_register(&ksz9031_driver);
9082eeac AF	390	return 0;
9082eeac AF	391	}