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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / drivers / net / phy / mv88e61xx.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
24ae3961
KS		 2/*
3 * (C) Copyright 2015
4 * Elecsys Corporation <www.elecsyscorp.com>
5 * Kevin Smith <kevin.smith@elecsyscorp.com>
6 *
7 * Original driver:
8 * (C) Copyright 2009
9 * Marvell Semiconductor <www.marvell.com>
10 * Prafulla Wadaskar <prafulla@marvell.com>
24ae3961
KS		 11 */
12
13/*
14 * PHY driver for mv88e61xx ethernet switches.
15 *
16 * This driver configures the mv88e61xx for basic use as a PHY. The switch
17 * supports a VLAN configuration that determines how traffic will be routed
18 * between the ports. This driver uses a simple configuration that routes
19 * traffic from each PHY port only to the CPU port, and from the CPU port to
20 * any PHY port.
21 *
22 * The configuration determines which PHY ports to activate using the
23 * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit
24 * 1 activates port 1, etc. Do not set the bit for the port the CPU is
25 * connected to unless it is connected over a PHY interface (not MII).
26 *
27 * This driver was written for and tested on the mv88e6176 with an SGMII
28 * connection. Other configurations should be supported, but some additions or
29 * changes may be required.
30 */
31
d678a59d 32#include <common.h>
f7ae49fc 33#include <log.h>
cd93d625 34#include <linux/bitops.h>
c05ed00a 35#include <linux/delay.h>
24ae3961
KS		 36
37#include <bitfield.h>
38#include <errno.h>
39#include <malloc.h>
40#include <miiphy.h>
41#include <netdev.h>
42
43#define PHY_AUTONEGOTIATE_TIMEOUT 5000
44
f41a722b 45#define PORT_MASK(port_count) ((1 << (port_count)) - 1)
24ae3961
KS		 46
47/* Device addresses */
48#define DEVADDR_PHY(p) (p)
24ae3961 49#define DEVADDR_SERDES 0x0F
24ae3961
KS		 50
51/* SMI indirection registers for multichip addressing mode */
52#define SMI_CMD_REG 0x00
53#define SMI_DATA_REG 0x01
54
55/* Global registers */
56#define GLOBAL1_STATUS 0x00
57#define GLOBAL1_CTRL 0x04
58#define GLOBAL1_MON_CTRL 0x1A
59
60/* Global 2 registers */
61#define GLOBAL2_REG_PHY_CMD 0x18
62#define GLOBAL2_REG_PHY_DATA 0x19
63
64/* Port registers */
65#define PORT_REG_STATUS 0x00
66#define PORT_REG_PHYS_CTRL 0x01
67#define PORT_REG_SWITCH_ID 0x03
68#define PORT_REG_CTRL 0x04
69#define PORT_REG_VLAN_MAP 0x06
70#define PORT_REG_VLAN_ID 0x07
71
72/* Phy registers */
73#define PHY_REG_CTRL1 0x10
74#define PHY_REG_STATUS1 0x11
75#define PHY_REG_PAGE 0x16
76
77/* Serdes registers */
78#define SERDES_REG_CTRL_1 0x10
79
80/* Phy page numbers */
81#define PHY_PAGE_COPPER 0
82#define PHY_PAGE_SERDES 1
83
84/* Register fields */
85#define GLOBAL1_CTRL_SWRESET BIT(15)
86
87#define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4
88#define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4
89
24ae3961 90#define PORT_REG_STATUS_SPEED_SHIFT 8
24ae3961
KS		 91#define PORT_REG_STATUS_SPEED_10 0
92#define PORT_REG_STATUS_SPEED_100 1
93#define PORT_REG_STATUS_SPEED_1000 2
94
95#define PORT_REG_STATUS_CMODE_MASK 0xF
96#define PORT_REG_STATUS_CMODE_100BASE_X 0x8
97#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
98#define PORT_REG_STATUS_CMODE_SGMII 0xa
99
b755abec
CP		 100#define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10)
101#define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9)
102#define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7)
103#define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6)
24ae3961
KS		 104#define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
105#define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
b755abec
CP		 106#define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3)
107#define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2)
108#define PORT_REG_PHYS_CTRL_SPD1000 BIT(1)
4aa05f6c 109#define PORT_REG_PHYS_CTRL_SPD100 BIT(0)
b755abec 110#define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0))
24ae3961
KS		 111
112#define PORT_REG_CTRL_PSTATE_SHIFT 0
113#define PORT_REG_CTRL_PSTATE_WIDTH 2
114
115#define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0
116#define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12
117
118#define PORT_REG_VLAN_MAP_TABLE_SHIFT 0
119#define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
120
121#define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
122
24ae3961
KS		 123/* Field values */
124#define PORT_REG_CTRL_PSTATE_DISABLED 0
125#define PORT_REG_CTRL_PSTATE_FORWARD 3
126
127#define PHY_REG_CTRL1_ENERGY_DET_OFF 0
41820c4b 128#define PHY_REG_CTRL1_ENERGY_DET_SENSE_PULSE 1
24ae3961
KS		 129#define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2
130#define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3
131
132/* PHY Status Register */
133#define PHY_REG_STATUS1_SPEED 0xc000
134#define PHY_REG_STATUS1_GBIT 0x8000
135#define PHY_REG_STATUS1_100 0x4000
136#define PHY_REG_STATUS1_DUPLEX 0x2000
137#define PHY_REG_STATUS1_SPDDONE 0x0800
138#define PHY_REG_STATUS1_LINK 0x0400
139#define PHY_REG_STATUS1_ENERGY 0x0010
140
141/*
142 * Macros for building commands for indirect addressing modes. These are valid
143 * for both the indirect multichip addressing mode and the PHY indirection
144 * required for the writes to any PHY register.
145 */
146#define SMI_BUSY BIT(15)
147#define SMI_CMD_CLAUSE_22 BIT(12)
148#define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
149#define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
150
151#define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
152 SMI_CMD_CLAUSE_22_OP_READ)
153#define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
154 SMI_CMD_CLAUSE_22_OP_WRITE)
155
156#define SMI_CMD_ADDR_SHIFT 5
157#define SMI_CMD_ADDR_WIDTH 5
158#define SMI_CMD_REG_SHIFT 0
159#define SMI_CMD_REG_WIDTH 5
160
161/* Check for required macros */
162#ifndef CONFIG_MV88E61XX_PHY_PORTS
163#error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
164 to activate
165#endif
166#ifndef CONFIG_MV88E61XX_CPU_PORT
167#error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
168#endif
169
170/* ID register values for different switch models */
f41a722b
AG		 171#define PORT_SWITCH_ID_6020 0x0200
172#define PORT_SWITCH_ID_6070 0x0700
173#define PORT_SWITCH_ID_6071 0x0710
65d4d00a
CP		 174#define PORT_SWITCH_ID_6096 0x0980
175#define PORT_SWITCH_ID_6097 0x0990
24ae3961
KS		 176#define PORT_SWITCH_ID_6172 0x1720
177#define PORT_SWITCH_ID_6176 0x1760
f41a722b 178#define PORT_SWITCH_ID_6220 0x2200
24ae3961 179#define PORT_SWITCH_ID_6240 0x2400
f41a722b 180#define PORT_SWITCH_ID_6250 0x2500
24ae3961
KS		 181#define PORT_SWITCH_ID_6352 0x3520
182
183struct mv88e61xx_phy_priv {
184 struct mii_dev *mdio_bus;
185 int smi_addr;
186 int id;
f41a722b
AG		 187 int port_count; /* Number of switch ports */
188 int port_reg_base; /* Base of the switch port registers */
4aa05f6c
AG		 189 u16 port_stat_link_mask;/* Bitmask for port link status bits */
190 u16 port_stat_dup_mask; /* Bitmask for port duplex status bits */
191 u8 port_stat_speed_width;/* Width of speed status bitfield */
f41a722b
AG		 192 u8 global1; /* Offset of Switch Global 1 registers */
193 u8 global2; /* Offset of Switch Global 2 registers */
41820c4b
AG		 194 u8 phy_ctrl1_en_det_shift; /* 'EDet' bit field offset */
195 u8 phy_ctrl1_en_det_width; /* Width of 'EDet' bit field */
196 u8 phy_ctrl1_en_det_ctrl; /* 'EDet' control value */
24ae3961
KS		 197};
198
199static inline int smi_cmd(int cmd, int addr, int reg)
200{
201 cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
202 addr);
203 cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
204 return cmd;
205}
206
207static inline int smi_cmd_read(int addr, int reg)
208{
209 return smi_cmd(SMI_CMD_READ, addr, reg);
210}
211
212static inline int smi_cmd_write(int addr, int reg)
213{
214 return smi_cmd(SMI_CMD_WRITE, addr, reg);
215}
216
217__weak int mv88e61xx_hw_reset(struct phy_device *phydev)
218{
219 return 0;
220}
221
222/* Wait for the current SMI indirect command to complete */
223static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
224{
225 int val;
226 u32 timeout = 100;
227
228 do {
229 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
230 if (val >= 0 && (val & SMI_BUSY) == 0)
231 return 0;
232
233 mdelay(1);
234 } while (--timeout);
235
236 puts("SMI busy timeout\n");
237 return -ETIMEDOUT;
238}
239
240/*
241 * The mv88e61xx has three types of addresses: the smi bus address, the device
242 * address, and the register address. The smi bus address distinguishes it on
243 * the smi bus from other PHYs or switches. The device address determines
244 * which on-chip register set you are reading/writing (the various PHYs, their
245 * associated ports, or global configuration registers). The register address
246 * is the offset of the register you are reading/writing.
247 *
248 * When the mv88e61xx is hardware configured to have address zero, it behaves in
249 * single-chip addressing mode, where it responds to all SMI addresses, using
250 * the smi address as its device address. This obviously only works when this
251 * is the only chip on the SMI bus. This allows the driver to access device
252 * registers without using indirection. When the chip is configured to a
253 * non-zero address, it only responds to that SMI address and requires indirect
254 * writes to access the different device addresses.
255 */
256static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
257{
258 struct mv88e61xx_phy_priv *priv = phydev->priv;
259 struct mii_dev *mdio_bus = priv->mdio_bus;
260 int smi_addr = priv->smi_addr;
261 int res;
262
263 /* In single-chip mode, the device can be addressed directly */
264 if (smi_addr == 0)
265 return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
266
267 /* Wait for the bus to become free */
268 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
269 if (res < 0)
270 return res;
271
272 /* Issue the read command */
273 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
274 smi_cmd_read(dev, reg));
275 if (res < 0)
276 return res;
277
278 /* Wait for the read command to complete */
279 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
280 if (res < 0)
281 return res;
282
283 /* Read the data */
284 res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
285 if (res < 0)
286 return res;
287
288 return bitfield_extract(res, 0, 16);
289}
290
291/* See the comment above mv88e61xx_reg_read */
292static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
293 u16 val)
294{
295 struct mv88e61xx_phy_priv *priv = phydev->priv;
296 struct mii_dev *mdio_bus = priv->mdio_bus;
297 int smi_addr = priv->smi_addr;
298 int res;
299
300 /* In single-chip mode, the device can be addressed directly */
301 if (smi_addr == 0) {
302 return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
303 val);
304 }
305
306 /* Wait for the bus to become free */
307 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
308 if (res < 0)
309 return res;
310
311 /* Set the data to write */
312 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
313 SMI_DATA_REG, val);
314 if (res < 0)
315 return res;
316
317 /* Issue the write command */
318 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
319 smi_cmd_write(dev, reg));
320 if (res < 0)
321 return res;
322
323 /* Wait for the write command to complete */
324 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
325 if (res < 0)
326 return res;
327
328 return 0;
329}
330
331static int mv88e61xx_phy_wait(struct phy_device *phydev)
332{
f41a722b 333 struct mv88e61xx_phy_priv *priv = phydev->priv;
24ae3961
KS		 334 int val;
335 u32 timeout = 100;
336
337 do {
f41a722b 338 val = mv88e61xx_reg_read(phydev, priv->global2,
24ae3961
KS		 339 GLOBAL2_REG_PHY_CMD);
340 if (val >= 0 && (val & SMI_BUSY) == 0)
341 return 0;
342
343 mdelay(1);
344 } while (--timeout);
345
346 return -ETIMEDOUT;
347}
348
349static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
350 int devad, int reg)
351{
f41a722b 352 struct mv88e61xx_phy_priv *priv;
24ae3961
KS		 353 struct phy_device *phydev;
354 int res;
355
356 phydev = (struct phy_device *)smi_wrapper->priv;
f41a722b 357 priv = phydev->priv;
24ae3961
KS		 358
359 /* Issue command to read */
f41a722b 360 res = mv88e61xx_reg_write(phydev, priv->global2,
24ae3961
KS		 361 GLOBAL2_REG_PHY_CMD,
362 smi_cmd_read(dev, reg));
363
364 /* Wait for data to be read */
365 res = mv88e61xx_phy_wait(phydev);
366 if (res < 0)
367 return res;
368
369 /* Read retrieved data */
f41a722b 370 return mv88e61xx_reg_read(phydev, priv->global2,
24ae3961
KS		 371 GLOBAL2_REG_PHY_DATA);
372}
373
374static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
375 int devad, int reg, u16 data)
376{
f41a722b 377 struct mv88e61xx_phy_priv *priv;
24ae3961
KS		 378 struct phy_device *phydev;
379 int res;
380
381 phydev = (struct phy_device *)smi_wrapper->priv;
f41a722b 382 priv = phydev->priv;
24ae3961
KS		 383
384 /* Set the data to write */
f41a722b 385 res = mv88e61xx_reg_write(phydev, priv->global2,
24ae3961
KS		 386 GLOBAL2_REG_PHY_DATA, data);
387 if (res < 0)
388 return res;
389 /* Issue the write command */
f41a722b 390 res = mv88e61xx_reg_write(phydev, priv->global2,
24ae3961
KS		 391 GLOBAL2_REG_PHY_CMD,
392 smi_cmd_write(dev, reg));
393 if (res < 0)
394 return res;
395
396 /* Wait for command to complete */
397 return mv88e61xx_phy_wait(phydev);
398}
399
400/* Wrapper function to make calls to phy_read_indirect simpler */
401static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
402{
403 return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
404 MDIO_DEVAD_NONE, reg);
405}
406
407/* Wrapper function to make calls to phy_read_indirect simpler */
408static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
409 int reg, u16 val)
410{
411 return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
412 MDIO_DEVAD_NONE, reg, val);
413}
414
415static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
416{
f41a722b
AG		 417 struct mv88e61xx_phy_priv *priv = phydev->priv;
418
419 return mv88e61xx_reg_read(phydev, priv->port_reg_base + port, reg);
24ae3961
KS		 420}
421
422static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
423 u16 val)
424{
f41a722b
AG		 425 struct mv88e61xx_phy_priv *priv = phydev->priv;
426
427 return mv88e61xx_reg_write(phydev, priv->port_reg_base + port,
428 reg, val);
24ae3961
KS		 429}
430
431static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
432{
433 return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
434}
435
436static int mv88e61xx_get_switch_id(struct phy_device *phydev)
437{
438 int res;
439
440 res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
441 if (res < 0)
442 return res;
443 return res & 0xfff0;
444}
445
446static bool mv88e61xx_6352_family(struct phy_device *phydev)
447{
448 struct mv88e61xx_phy_priv *priv = phydev->priv;
449
450 switch (priv->id) {
451 case PORT_SWITCH_ID_6172:
452 case PORT_SWITCH_ID_6176:
453 case PORT_SWITCH_ID_6240:
454 case PORT_SWITCH_ID_6352:
455 return true;
456 }
457 return false;
458}
459
460static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
461{
462 int res;
463
464 res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
465 if (res < 0)
466 return res;
467 return res & PORT_REG_STATUS_CMODE_MASK;
468}
469
470static int mv88e61xx_parse_status(struct phy_device *phydev)
471{
472 unsigned int speed;
473 unsigned int mii_reg;
474
475 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
476
477 if ((mii_reg & PHY_REG_STATUS1_LINK) &&
478 !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
479 int i = 0;
480
481 puts("Waiting for PHY realtime link");
482 while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
483 /* Timeout reached ? */
484 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
485 puts(" TIMEOUT !\n");
486 phydev->link = 0;
487 break;
488 }
489
490 if ((i++ % 1000) == 0)
491 putc('.');
492 udelay(1000);
493 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
494 PHY_REG_STATUS1);
495 }
496 puts(" done\n");
497 udelay(500000); /* another 500 ms (results in faster booting) */
498 } else {
499 if (mii_reg & PHY_REG_STATUS1_LINK)
500 phydev->link = 1;
501 else
502 phydev->link = 0;
503 }
504
505 if (mii_reg & PHY_REG_STATUS1_DUPLEX)
506 phydev->duplex = DUPLEX_FULL;
507 else
508 phydev->duplex = DUPLEX_HALF;
509
510 speed = mii_reg & PHY_REG_STATUS1_SPEED;
511
512 switch (speed) {
513 case PHY_REG_STATUS1_GBIT:
514 phydev->speed = SPEED_1000;
515 break;
516 case PHY_REG_STATUS1_100:
517 phydev->speed = SPEED_100;
518 break;
519 default:
520 phydev->speed = SPEED_10;
521 break;
522 }
523
524 return 0;
525}
526
527static int mv88e61xx_switch_reset(struct phy_device *phydev)
528{
f41a722b 529 struct mv88e61xx_phy_priv *priv = phydev->priv;
24ae3961
KS		 530 int time;
531 int val;
532 u8 port;
533
534 /* Disable all ports */
f41a722b 535 for (port = 0; port < priv->port_count; port++) {
24ae3961
KS		 536 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
537 if (val < 0)
538 return val;
539 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
540 PORT_REG_CTRL_PSTATE_WIDTH,
541 PORT_REG_CTRL_PSTATE_DISABLED);
542 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
543 if (val < 0)
544 return val;
545 }
546
547 /* Wait 2 ms for queues to drain */
548 udelay(2000);
549
550 /* Reset switch */
f41a722b 551 val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_CTRL);
24ae3961
KS		 552 if (val < 0)
553 return val;
554 val |= GLOBAL1_CTRL_SWRESET;
f41a722b
AG		 555 val = mv88e61xx_reg_write(phydev, priv->global1,
556 GLOBAL1_CTRL, val);
24ae3961
KS		 557 if (val < 0)
558 return val;
559
560 /* Wait up to 1 second for switch reset complete */
561 for (time = 1000; time; time--) {
f41a722b
AG		 562 val = mv88e61xx_reg_read(phydev, priv->global1,
563 GLOBAL1_CTRL);
24ae3961
KS		 564 if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
565 break;
566 udelay(1000);
567 }
568 if (!time)
569 return -ETIMEDOUT;
570
571 return 0;
572}
573
574static int mv88e61xx_serdes_init(struct phy_device *phydev)
575{
576 int val;
577
578 val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
579 if (val < 0)
580 return val;
581
582 /* Power up serdes module */
583 val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
584 if (val < 0)
585 return val;
586 val &= ~(BMCR_PDOWN);
587 val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
588 if (val < 0)
589 return val;
590
591 return 0;
592}
593
594static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
595{
596 int val;
597
598 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
599 if (val < 0)
600 return val;
601 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
602 PORT_REG_CTRL_PSTATE_WIDTH,
603 PORT_REG_CTRL_PSTATE_FORWARD);
604 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
605 if (val < 0)
606 return val;
607
608 return 0;
609}
610
611static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
65d4d00a 612 u16 mask)
24ae3961
KS		 613{
614 int val;
615
616 /* Set VID to port number plus one */
617 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
618 if (val < 0)
619 return val;
620 val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
621 PORT_REG_VLAN_ID_DEF_VID_WIDTH,
622 port + 1);
623 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
624 if (val < 0)
625 return val;
626
627 /* Set VID mask */
628 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
629 if (val < 0)
630 return val;
631 val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
632 PORT_REG_VLAN_MAP_TABLE_WIDTH,
633 mask);
634 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
635 if (val < 0)
636 return val;
637
638 return 0;
639}
640
641static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
642{
4aa05f6c 643 struct mv88e61xx_phy_priv *priv = phydev->priv;
24ae3961
KS		 644 int res;
645 int val;
646 bool forced = false;
647
648 val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
649 if (val < 0)
650 return val;
4aa05f6c 651 if (!(val & priv->port_stat_link_mask)) {
24ae3961
KS		 652 /* Temporarily force link to read port configuration */
653 u32 timeout = 100;
654 forced = true;
655
656 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
657 if (val < 0)
658 return val;
659 val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
660 PORT_REG_PHYS_CTRL_LINK_VALUE);
661 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
662 val);
663 if (val < 0)
664 return val;
665
666 /* Wait for status register to reflect forced link */
667 do {
668 val = mv88e61xx_port_read(phydev, port,
669 PORT_REG_STATUS);
4201223d
TR		 670 if (val < 0) {
671 res = -EIO;
24ae3961 672 goto unforce;
4201223d 673 }
4aa05f6c 674 if (val & priv->port_stat_link_mask)
24ae3961
KS		 675 break;
676 } while (--timeout);
677
678 if (timeout == 0) {
679 res = -ETIMEDOUT;
680 goto unforce;
681 }
682 }
683
4aa05f6c 684 if (val & priv->port_stat_dup_mask)
24ae3961
KS		 685 phydev->duplex = DUPLEX_FULL;
686 else
687 phydev->duplex = DUPLEX_HALF;
688
689 val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
4aa05f6c 690 priv->port_stat_speed_width);
24ae3961
KS		 691 switch (val) {
692 case PORT_REG_STATUS_SPEED_1000:
693 phydev->speed = SPEED_1000;
694 break;
695 case PORT_REG_STATUS_SPEED_100:
696 phydev->speed = SPEED_100;
697 break;
698 default:
699 phydev->speed = SPEED_10;
700 break;
701 }
702
703 res = 0;
704
705unforce:
706 if (forced) {
707 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
708 if (val < 0)
709 return val;
710 val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
711 PORT_REG_PHYS_CTRL_LINK_VALUE);
712 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
713 val);
714 if (val < 0)
715 return val;
716 }
717
718 return res;
719}
720
3cb51dad
CP		 721static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
722{
4aa05f6c 723 struct mv88e61xx_phy_priv *priv = phydev->priv;
3cb51dad
CP		 724 int val;
725
726 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
727 if (val < 0)
728 return val;
729
730 val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK |
4aa05f6c
AG		 731 PORT_REG_PHYS_CTRL_FC_VALUE |
732 PORT_REG_PHYS_CTRL_FC_FORCE);
733 val |= PORT_REG_PHYS_CTRL_FC_FORCE |
3cb51dad 734 PORT_REG_PHYS_CTRL_DUPLEX_VALUE |
4aa05f6c
AG		 735 PORT_REG_PHYS_CTRL_DUPLEX_FORCE;
736
737 if (priv->id == PORT_SWITCH_ID_6071) {
738 val |= PORT_REG_PHYS_CTRL_SPD100;
739 } else {
740 val |= PORT_REG_PHYS_CTRL_PCS_AN_EN |
741 PORT_REG_PHYS_CTRL_PCS_AN_RST |
742 PORT_REG_PHYS_CTRL_SPD1000;
743 }
3cb51dad
CP		 744
745 if (port == CONFIG_MV88E61XX_CPU_PORT)
746 val |= PORT_REG_PHYS_CTRL_LINK_VALUE |
747 PORT_REG_PHYS_CTRL_LINK_FORCE;
748
749 return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
750 val);
751}
752
24ae3961
KS		 753static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
754{
f41a722b 755 struct mv88e61xx_phy_priv *priv = phydev->priv;
24ae3961
KS		 756 int val;
757
758 /* Set CPUDest */
f41a722b 759 val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_MON_CTRL);
24ae3961
KS		 760 if (val < 0)
761 return val;
762 val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
763 GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
764 CONFIG_MV88E61XX_CPU_PORT);
f41a722b
AG		 765 val = mv88e61xx_reg_write(phydev, priv->global1,
766 GLOBAL1_MON_CTRL, val);
24ae3961
KS		 767 if (val < 0)
768 return val;
769
770 /* Allow CPU to route to any port */
f41a722b 771 val = PORT_MASK(priv->port_count) & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
24ae3961
KS		 772 val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
773 if (val < 0)
774 return val;
775
776 /* Enable CPU port */
777 val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
778 if (val < 0)
779 return val;
780
781 val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
782 if (val < 0)
783 return val;
784
785 /* If CPU is connected to serdes, initialize serdes */
786 if (mv88e61xx_6352_family(phydev)) {
787 val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
788 if (val < 0)
789 return val;
790 if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
791 val == PORT_REG_STATUS_CMODE_1000BASE_X ||
792 val == PORT_REG_STATUS_CMODE_SGMII) {
793 val = mv88e61xx_serdes_init(phydev);
794 if (val < 0)
795 return val;
796 }
3cb51dad
CP		 797 } else {
798 val = mv88e61xx_fixed_port_setup(phydev,
799 CONFIG_MV88E61XX_CPU_PORT);
800 if (val < 0)
801 return val;
24ae3961
KS		 802 }
803
804 return 0;
805}
806
807static int mv88e61xx_switch_init(struct phy_device *phydev)
808{
809 static int init;
810 int res;
811
812 if (init)
813 return 0;
814
815 res = mv88e61xx_switch_reset(phydev);
816 if (res < 0)
817 return res;
818
819 res = mv88e61xx_set_cpu_port(phydev);
820 if (res < 0)
821 return res;
822
823 init = 1;
824
825 return 0;
826}
827
828static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
829{
830 int val;
831
832 val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
833 if (val < 0)
834 return val;
835 val &= ~(BMCR_PDOWN);
836 val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
837 if (val < 0)
838 return val;
839
840 return 0;
841}
842
843static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
844{
41820c4b 845 struct mv88e61xx_phy_priv *priv = phydev->priv;
24ae3961
KS		 846 int val;
847
848 /*
849 * Enable energy-detect sensing on PHY, used to determine when a PHY
850 * port is physically connected
851 */
852 val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
853 if (val < 0)
854 return val;
41820c4b
AG		 855 val = bitfield_replace(val, priv->phy_ctrl1_en_det_shift,
856 priv->phy_ctrl1_en_det_width,
857 priv->phy_ctrl1_en_det_ctrl);
24ae3961
KS		 858 val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
859 if (val < 0)
860 return val;
861
862 return 0;
863}
864
865static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
866{
867 int val;
868
869 val = mv88e61xx_port_enable(phydev, phy);
870 if (val < 0)
871 return val;
872
873 val = mv88e61xx_port_set_vlan(phydev, phy,
874 1 << CONFIG_MV88E61XX_CPU_PORT);
875 if (val < 0)
876 return val;
877
878 return 0;
879}
880
f41a722b
AG		 881/*
882 * This function is used to pre-configure the required register
883 * offsets, so that the indirect register access to the PHY registers
884 * is possible. This is necessary to be able to read the PHY ID
885 * while driver probing or in get_phy_id(). The globalN register
886 * offsets must be initialized correctly for a detected switch,
887 * otherwise detection of the PHY ID won't work!
888 */
889static int mv88e61xx_priv_reg_offs_pre_init(struct phy_device *phydev)
890{
891 struct mv88e61xx_phy_priv *priv = phydev->priv;
892
893 /*
894 * Initial 'port_reg_base' value must be an offset of existing
895 * port register, then reading the ID should succeed. First, try
896 * to read via port registers with device address 0x10 (88E6096
897 * and compatible switches).
898 */
899 priv->port_reg_base = 0x10;
900 priv->id = mv88e61xx_get_switch_id(phydev);
901 if (priv->id != 0xfff0) {
902 priv->global1 = 0x1B;
903 priv->global2 = 0x1C;
904 return 0;
905 }
906
907 /*
908 * Now try via port registers with device address 0x08
909 * (88E6020 and compatible switches).
910 */
911 priv->port_reg_base = 0x08;
912 priv->id = mv88e61xx_get_switch_id(phydev);
913 if (priv->id != 0xfff0) {
914 priv->global1 = 0x0F;
915 priv->global2 = 0x07;
916 return 0;
917 }
918
919 debug("%s Unknown ID 0x%x\n", __func__, priv->id);
920 return -ENODEV;
921}
922
24ae3961
KS		 923static int mv88e61xx_probe(struct phy_device *phydev)
924{
925 struct mii_dev *smi_wrapper;
926 struct mv88e61xx_phy_priv *priv;
927 int res;
928
929 res = mv88e61xx_hw_reset(phydev);
930 if (res < 0)
931 return res;
932
933 priv = malloc(sizeof(*priv));
934 if (!priv)
935 return -ENOMEM;
936
937 memset(priv, 0, sizeof(*priv));
938
939 /*
940 * This device requires indirect reads/writes to the PHY registers
941 * which the generic PHY code can't handle. Make a wrapper MII device
942 * to handle reads/writes
943 */
944 smi_wrapper = mdio_alloc();
945 if (!smi_wrapper) {
946 free(priv);
947 return -ENOMEM;
948 }
949
950 /*
951 * Store the mdio bus in the private data, as we are going to replace
952 * the bus with the wrapper bus
953 */
954 priv->mdio_bus = phydev->bus;
955
956 /*
957 * Store the smi bus address in private data. This lets us use the
958 * phydev addr field for device address instead, as the genphy code
959 * expects.
960 */
961 priv->smi_addr = phydev->addr;
962
963 /*
964 * Store the phy_device in the wrapper mii device. This lets us get it
965 * back when genphy functions call phy_read/phy_write.
966 */
967 smi_wrapper->priv = phydev;
968 strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
969 smi_wrapper->read = mv88e61xx_phy_read_indirect;
970 smi_wrapper->write = mv88e61xx_phy_write_indirect;
971
972 /* Replace the bus with the wrapper device */
973 phydev->bus = smi_wrapper;
974
975 phydev->priv = priv;
976
f41a722b
AG		 977 res = mv88e61xx_priv_reg_offs_pre_init(phydev);
978 if (res < 0)
979 return res;
980
981 debug("%s ID 0x%x\n", __func__, priv->id);
982
983 switch (priv->id) {
984 case PORT_SWITCH_ID_6096:
985 case PORT_SWITCH_ID_6097:
986 case PORT_SWITCH_ID_6172:
987 case PORT_SWITCH_ID_6176:
988 case PORT_SWITCH_ID_6240:
989 case PORT_SWITCH_ID_6352:
990 priv->port_count = 11;
4aa05f6c
AG		 991 priv->port_stat_link_mask = BIT(11);
992 priv->port_stat_dup_mask = BIT(10);
993 priv->port_stat_speed_width = 2;
41820c4b
AG		 994 priv->phy_ctrl1_en_det_shift = 8;
995 priv->phy_ctrl1_en_det_width = 2;
996 priv->phy_ctrl1_en_det_ctrl =
997 PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT;
f41a722b
AG		 998 break;
999 case PORT_SWITCH_ID_6020:
1000 case PORT_SWITCH_ID_6070:
1001 case PORT_SWITCH_ID_6071:
1002 case PORT_SWITCH_ID_6220:
1003 case PORT_SWITCH_ID_6250:
1004 priv->port_count = 7;
4aa05f6c
AG		 1005 priv->port_stat_link_mask = BIT(12);
1006 priv->port_stat_dup_mask = BIT(9);
1007 priv->port_stat_speed_width = 1;
41820c4b
AG		 1008 priv->phy_ctrl1_en_det_shift = 14;
1009 priv->phy_ctrl1_en_det_width = 1;
1010 priv->phy_ctrl1_en_det_ctrl =
1011 PHY_REG_CTRL1_ENERGY_DET_SENSE_PULSE;
f41a722b
AG		 1012 break;
1013 default:
1014 free(priv);
1015 return -ENODEV;
1016 }
1017
1018 res = mdio_register(smi_wrapper);
1019 if (res)
1020 printf("Failed to register SMI bus\n");
24ae3961
KS		 1021
1022 return 0;
1023}
1024
1025static int mv88e61xx_phy_config(struct phy_device *phydev)
1026{
f41a722b 1027 struct mv88e61xx_phy_priv *priv = phydev->priv;
24ae3961
KS		 1028 int res;
1029 int i;
1030 int ret = -1;
1031
1032 res = mv88e61xx_switch_init(phydev);
1033 if (res < 0)
1034 return res;
1035
f41a722b 1036 for (i = 0; i < priv->port_count; i++) {
24ae3961
KS		 1037 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
1038 phydev->addr = i;
1039
1040 res = mv88e61xx_phy_enable(phydev, i);
1041 if (res < 0) {
1042 printf("Error enabling PHY %i\n", i);
1043 continue;
1044 }
1045 res = mv88e61xx_phy_setup(phydev, i);
1046 if (res < 0) {
1047 printf("Error setting up PHY %i\n", i);
1048 continue;
1049 }
1050 res = mv88e61xx_phy_config_port(phydev, i);
1051 if (res < 0) {
1052 printf("Error configuring PHY %i\n", i);
1053 continue;
1054 }
1055
69280961 1056 res = phy_reset(phydev);
24ae3961 1057 if (res < 0) {
69280961 1058 printf("Error resetting PHY %i\n", i);
24ae3961
KS		 1059 continue;
1060 }
69280961 1061 res = genphy_config_aneg(phydev);
24ae3961 1062 if (res < 0) {
69280961 1063 printf("Error setting PHY %i autoneg\n", i);
24ae3961
KS		 1064 continue;
1065 }
1066
1067 /* Return success if any PHY succeeds */
1068 ret = 0;
b755abec
CP		 1069 } else if ((1 << i) & CONFIG_MV88E61XX_FIXED_PORTS) {
1070 res = mv88e61xx_fixed_port_setup(phydev, i);
1071 if (res < 0) {
1072 printf("Error configuring port %i\n", i);
1073 continue;
1074 }
24ae3961
KS		 1075 }
1076 }
1077
1078 return ret;
1079}
1080
1081static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
1082{
1083 int val;
1084
1085 val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
1086 if (val < 0)
1087 return 0;
1088
1089 /*
1090 * After reset, the energy detect signal remains high for a few seconds
1091 * regardless of whether a cable is connected. This function will
1092 * return false positives during this time.
1093 */
1094 return (val & PHY_REG_STATUS1_ENERGY) == 0;
1095}
1096
1097static int mv88e61xx_phy_startup(struct phy_device *phydev)
1098{
f41a722b 1099 struct mv88e61xx_phy_priv *priv = phydev->priv;
24ae3961
KS		 1100 int i;
1101 int link = 0;
1102 int res;
1103 int speed = phydev->speed;
1104 int duplex = phydev->duplex;
1105
f41a722b 1106 for (i = 0; i < priv->port_count; i++) {
24ae3961
KS		 1107 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
1108 phydev->addr = i;
1109 if (!mv88e61xx_phy_is_connected(phydev))
1110 continue;
1111 res = genphy_update_link(phydev);
1112 if (res < 0)
1113 continue;
1114 res = mv88e61xx_parse_status(phydev);
1115 if (res < 0)
1116 continue;
1117 link = (link || phydev->link);
1118 }
1119 }
1120 phydev->link = link;
1121
1122 /* Restore CPU interface speed and duplex after it was changed for
1123 * other ports */
1124 phydev->speed = speed;
1125 phydev->duplex = duplex;
1126
1127 return 0;
1128}
1129
abdbfad2 1130U_BOOT_PHY_DRIVER(mv88e61xx) = {
24ae3961
KS		 1131 .name = "Marvell MV88E61xx",
1132 .uid = 0x01410eb1,
1133 .mask = 0xfffffff0,
1134 .features = PHY_GBIT_FEATURES,
1135 .probe = mv88e61xx_probe,
1136 .config = mv88e61xx_phy_config,
1137 .startup = mv88e61xx_phy_startup,
1138 .shutdown = &genphy_shutdown,
1139};
1140
abdbfad2 1141U_BOOT_PHY_DRIVER(mv88e609x) = {
65d4d00a
CP		 1142 .name = "Marvell MV88E609x",
1143 .uid = 0x1410c89,
1144 .mask = 0xfffffff0,
1145 .features = PHY_GBIT_FEATURES,
1146 .probe = mv88e61xx_probe,
1147 .config = mv88e61xx_phy_config,
1148 .startup = mv88e61xx_phy_startup,
1149 .shutdown = &genphy_shutdown,
1150};
1151
abdbfad2 1152U_BOOT_PHY_DRIVER(mv88e6071) = {
5bcb4b8f
AG		 1153 .name = "Marvell MV88E6071",
1154 .uid = 0x1410db0,
1155 .mask = 0xfffffff0,
1156 .features = PHY_BASIC_FEATURES | SUPPORTED_MII,
1157 .probe = mv88e61xx_probe,
1158 .config = mv88e61xx_phy_config,
1159 .startup = mv88e61xx_phy_startup,
1160 .shutdown = &genphy_shutdown,
1161};
1162
24ae3961
KS		 1163/*
1164 * Overload weak get_phy_id definition since we need non-standard functions
1165 * to read PHY registers
1166 */
1167int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
1168{
1169 struct phy_device temp_phy;
1170 struct mv88e61xx_phy_priv temp_priv;
1171 struct mii_dev temp_mii;
1172 int val;
1173
1174 /*
1175 * Buid temporary data structures that the chip reading code needs to
1176 * read the ID
1177 */
1178 temp_priv.mdio_bus = bus;
1179 temp_priv.smi_addr = smi_addr;
1180 temp_phy.priv = &temp_priv;
1181 temp_mii.priv = &temp_phy;
1182
f41a722b
AG		 1183 /*
1184 * get_phy_id() can be called by framework before mv88e61xx driver
1185 * probing, in this case the global register offsets are not
1186 * initialized yet. Do this initialization here before indirect
1187 * PHY register access.
1188 */
1189 val = mv88e61xx_priv_reg_offs_pre_init(&temp_phy);
1190 if (val < 0)
1191 return val;
1192
24ae3961
KS		 1193 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
1194 if (val < 0)
1195 return -EIO;
1196
1197 *phy_id = val << 16;
1198
1199 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
1200 if (val < 0)
1201 return -EIO;
1202
1203 *phy_id |= (val & 0xffff);
1204
1205 return 0;
1206}
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