]> git.ipfire.org Git - thirdparty/u-boot.git/blame - drivers/net/qe/dm_qe_uec.c
projects / thirdparty / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / drivers / net / qe / dm_qe_uec.c
CommitLineData
6e31c62a
HS		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * QE UEC ethernet controller driver
4 *
5 * based on drivers/qe/uec.c from NXP
6 *
7 * Copyright (C) 2020 Heiko Schocher <hs@denx.de>
8 */
9
d678a59d 10#include <common.h>
6e31c62a
HS		 11#include <dm.h>
12#include <errno.h>
13#include <memalign.h>
14#include <miiphy.h>
401d1c4f 15#include <asm/global_data.h>
6e31c62a
HS		 16#include <asm/io.h>
17
18#include "dm_qe_uec.h"
19
20#define QE_UEC_DRIVER_NAME "ucc_geth"
21
22/* Default UTBIPAR SMI address */
6e7df1d1
TR		 23#ifndef CFG_UTBIPAR_INIT_TBIPA
24#define CFG_UTBIPAR_INIT_TBIPA 0x1F
6e31c62a
HS		 25#endif
26
27static int uec_mac_enable(struct uec_priv *uec, comm_dir_e mode)
28{
29 uec_t *uec_regs;
30 u32 maccfg1;
31
32 uec_regs = uec->uec_regs;
33 maccfg1 = in_be32(&uec_regs->maccfg1);
34
35 if (mode & COMM_DIR_TX) {
36 maccfg1 |= MACCFG1_ENABLE_TX;
37 out_be32(&uec_regs->maccfg1, maccfg1);
38 uec->mac_tx_enabled = 1;
39 }
40
41 if (mode & COMM_DIR_RX) {
42 maccfg1 |= MACCFG1_ENABLE_RX;
43 out_be32(&uec_regs->maccfg1, maccfg1);
44 uec->mac_rx_enabled = 1;
45 }
46
47 return 0;
48}
49
50static int uec_mac_disable(struct uec_priv *uec, comm_dir_e mode)
51{
52 uec_t *uec_regs;
53 u32 maccfg1;
54
55 uec_regs = uec->uec_regs;
56 maccfg1 = in_be32(&uec_regs->maccfg1);
57
58 if (mode & COMM_DIR_TX) {
59 maccfg1 &= ~MACCFG1_ENABLE_TX;
60 out_be32(&uec_regs->maccfg1, maccfg1);
61 uec->mac_tx_enabled = 0;
62 }
63
64 if (mode & COMM_DIR_RX) {
65 maccfg1 &= ~MACCFG1_ENABLE_RX;
66 out_be32(&uec_regs->maccfg1, maccfg1);
67 uec->mac_rx_enabled = 0;
68 }
69
70 return 0;
71}
72
73static int uec_restart_tx(struct uec_priv *uec)
74{
75 struct uec_inf *ui = uec->uec_info;
76 u32 cecr_subblock;
77
78 cecr_subblock = ucc_fast_get_qe_cr_subblock(ui->uf_info.ucc_num);
79 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
80 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
81
82 uec->grace_stopped_tx = 0;
83
84 return 0;
85}
86
87static int uec_restart_rx(struct uec_priv *uec)
88{
89 struct uec_inf *ui = uec->uec_info;
90 u32 cecr_subblock;
91
92 cecr_subblock = ucc_fast_get_qe_cr_subblock(ui->uf_info.ucc_num);
93 qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
94 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
95
96 uec->grace_stopped_rx = 0;
97
98 return 0;
99}
100
101static int uec_open(struct uec_priv *uec, comm_dir_e mode)
102{
103 struct ucc_fast_priv *uccf;
104
105 uccf = uec->uccf;
106
107 /* check if the UCC number is in range. */
108 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
109 printf("%s: ucc_num out of range.\n", __func__);
110 return -EINVAL;
111 }
112
113 /* Enable MAC */
114 uec_mac_enable(uec, mode);
115
116 /* Enable UCC fast */
117 ucc_fast_enable(uccf, mode);
118
119 /* RISC microcode start */
120 if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx)
121 uec_restart_tx(uec);
122
123 if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx)
124 uec_restart_rx(uec);
125
126 return 0;
127}
128
129static int uec_set_mac_if_mode(struct uec_priv *uec)
130{
131 struct uec_inf *uec_info = uec->uec_info;
132 phy_interface_t enet_if_mode;
133 uec_t *uec_regs;
134 u32 upsmr;
135 u32 maccfg2;
136
137 uec_regs = uec->uec_regs;
138 enet_if_mode = uec_info->enet_interface_type;
139
140 maccfg2 = in_be32(&uec_regs->maccfg2);
141 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
142
143 upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
144 upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
145
146 switch (uec_info->speed) {
147 case SPEED_10:
148 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
149 switch (enet_if_mode) {
150 case PHY_INTERFACE_MODE_MII:
151 break;
152 case PHY_INTERFACE_MODE_RGMII:
153 upsmr |= (UPSMR_RPM | UPSMR_R10M);
154 break;
155 case PHY_INTERFACE_MODE_RMII:
156 upsmr |= (UPSMR_R10M | UPSMR_RMM);
157 break;
158 default:
159 return -EINVAL;
160 }
161 break;
162 case SPEED_100:
163 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
164 switch (enet_if_mode) {
165 case PHY_INTERFACE_MODE_MII:
166 break;
167 case PHY_INTERFACE_MODE_RGMII:
168 upsmr |= UPSMR_RPM;
169 break;
170 case PHY_INTERFACE_MODE_RMII:
171 upsmr |= UPSMR_RMM;
172 break;
173 default:
174 return -EINVAL;
69bd7dfc
RV		 175 }
176 break;
6e31c62a
HS		 177 case SPEED_1000:
178 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
179 switch (enet_if_mode) {
180 case PHY_INTERFACE_MODE_GMII:
181 break;
182 case PHY_INTERFACE_MODE_TBI:
183 upsmr |= UPSMR_TBIM;
184 break;
185 case PHY_INTERFACE_MODE_RTBI:
186 upsmr |= (UPSMR_RPM | UPSMR_TBIM);
187 break;
188 case PHY_INTERFACE_MODE_RGMII_RXID:
189 case PHY_INTERFACE_MODE_RGMII_TXID:
190 case PHY_INTERFACE_MODE_RGMII_ID:
191 case PHY_INTERFACE_MODE_RGMII:
192 upsmr |= UPSMR_RPM;
193 break;
194 case PHY_INTERFACE_MODE_SGMII:
195 upsmr |= UPSMR_SGMM;
196 break;
197 default:
198 return -EINVAL;
199 }
200 break;
201 default:
202 return -EINVAL;
203 }
204
205 out_be32(&uec_regs->maccfg2, maccfg2);
206 out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
207
208 return 0;
209}
210
211static int qe_uec_start(struct udevice *dev)
212{
213 struct qe_uec_priv *priv = dev_get_priv(dev);
214 struct uec_priv *uec = priv->uec;
215 struct phy_device *phydev = priv->phydev;
216 struct uec_inf *uec_info = uec->uec_info;
217 int err;
218
219 if (!phydev)
220 return -ENODEV;
221
222 /* Setup MAC interface mode */
223 genphy_update_link(phydev);
224 genphy_parse_link(phydev);
225 uec_info->speed = phydev->speed;
226 uec_set_mac_if_mode(uec);
227
228 err = uec_open(uec, COMM_DIR_RX_AND_TX);
229 if (err) {
230 printf("%s: cannot enable UEC device\n", dev->name);
231 return -EINVAL;
232 }
233
234 return (phydev->link ? 0 : -EINVAL);
235}
236
237static int qe_uec_send(struct udevice *dev, void *packet, int length)
238{
239 struct qe_uec_priv *priv = dev_get_priv(dev);
240 struct uec_priv *uec = priv->uec;
241 struct ucc_fast_priv *uccf = uec->uccf;
242 struct buffer_descriptor *bd;
243 u16 status;
244 int i;
245 int result = 0;
246
247 uccf = uec->uccf;
248 bd = uec->tx_bd;
249
250 /* Find an empty TxBD */
251 for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
252 if (i > 0x100000) {
253 printf("%s: tx buffer not ready\n", dev->name);
254 return result;
255 }
256 }
257
258 /* Init TxBD */
259 BD_DATA_SET(bd, packet);
260 BD_LENGTH_SET(bd, length);
261 status = BD_STATUS(bd);
262 status &= BD_WRAP;
263 status |= (TX_BD_READY | TX_BD_LAST);
264 BD_STATUS_SET(bd, status);
265
266 /* Tell UCC to transmit the buffer */
267 ucc_fast_transmit_on_demand(uccf);
268
269 /* Wait for buffer to be transmitted */
270 for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
271 if (i > 0x100000) {
272 printf("%s: tx error\n", dev->name);
273 return result;
274 }
275 }
276
277 /* Ok, the buffer be transimitted */
278 BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
279 uec->tx_bd = bd;
280 result = 1;
281
282 return result;
283}
284
285/*
286 * Receive frame:
287 * - wait for the next BD to get ready bit set
288 * - clean up the descriptor
289 * - move on and indicate to HW that the cleaned BD is available for Rx
290 */
291static int qe_uec_recv(struct udevice *dev, int flags, uchar **packetp)
292{
293 struct qe_uec_priv *priv = dev_get_priv(dev);
294 struct uec_priv *uec = priv->uec;
295 struct buffer_descriptor *bd;
296 u16 status;
297 u16 len = 0;
298 u8 *data;
299
300 *packetp = memalign(ARCH_DMA_MINALIGN, MAX_RXBUF_LEN);
301 if (*packetp == 0) {
302 printf("%s: error allocating packetp\n", __func__);
303 return -ENOMEM;
304 }
305
306 bd = uec->rx_bd;
307 status = BD_STATUS(bd);
308
309 while (!(status & RX_BD_EMPTY)) {
310 if (!(status & RX_BD_ERROR)) {
311 data = BD_DATA(bd);
312 len = BD_LENGTH(bd);
313 memcpy(*packetp, (char *)data, len);
314 } else {
315 printf("%s: Rx error\n", dev->name);
316 }
317 status &= BD_CLEAN;
318 BD_LENGTH_SET(bd, 0);
319 BD_STATUS_SET(bd, status | RX_BD_EMPTY);
320 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
321 status = BD_STATUS(bd);
322 }
323 uec->rx_bd = bd;
324
325 return len;
326}
327
328static int uec_graceful_stop_tx(struct uec_priv *uec)
329{
330 ucc_fast_t *uf_regs;
331 u32 cecr_subblock;
332 u32 ucce;
333
334 uf_regs = uec->uccf->uf_regs;
335
336 /* Clear the grace stop event */
337 out_be32(&uf_regs->ucce, UCCE_GRA);
338
339 /* Issue host command */
340 cecr_subblock =
341 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
342 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
343 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
344
345 /* Wait for command to complete */
346 do {
347 ucce = in_be32(&uf_regs->ucce);
348 } while (!(ucce & UCCE_GRA));
349
350 uec->grace_stopped_tx = 1;
351
352 return 0;
353}
354
355static int uec_graceful_stop_rx(struct uec_priv *uec)
356{
357 u32 cecr_subblock;
358 u8 ack;
359
360 if (!uec->p_rx_glbl_pram) {
361 printf("%s: No init rx global parameter\n", __func__);
362 return -EINVAL;
363 }
364
365 /* Clear acknowledge bit */
366 ack = uec->p_rx_glbl_pram->rxgstpack;
367 ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
368 uec->p_rx_glbl_pram->rxgstpack = ack;
369
370 /* Keep issuing cmd and checking ack bit until it is asserted */
371 do {
372 /* Issue host command */
373 cecr_subblock =
374 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
375 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
376 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
377 ack = uec->p_rx_glbl_pram->rxgstpack;
378 } while (!(ack & GRACEFUL_STOP_ACKNOWLEDGE_RX));
379
380 uec->grace_stopped_rx = 1;
381
382 return 0;
383}
384
385static int uec_stop(struct uec_priv *uec, comm_dir_e mode)
386{
387 /* check if the UCC number is in range. */
388 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
389 printf("%s: ucc_num out of range.\n", __func__);
390 return -EINVAL;
391 }
392 /* Stop any transmissions */
393 if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx)
394 uec_graceful_stop_tx(uec);
395
396 /* Stop any receptions */
397 if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx)
398 uec_graceful_stop_rx(uec);
399
400 /* Disable the UCC fast */
401 ucc_fast_disable(uec->uccf, mode);
402
403 /* Disable the MAC */
404 uec_mac_disable(uec, mode);
405
406 return 0;
407}
408
409static void qe_uec_stop(struct udevice *dev)
410{
411 struct qe_uec_priv *priv = dev_get_priv(dev);
412 struct uec_priv *uec = priv->uec;
413
414 uec_stop(uec, COMM_DIR_RX_AND_TX);
415}
416
417static int qe_uec_set_hwaddr(struct udevice *dev)
418{
419 struct qe_uec_priv *priv = dev_get_priv(dev);
c69cda25 420 struct eth_pdata *pdata = dev_get_plat(dev);
6e31c62a
HS		 421 struct uec_priv *uec = priv->uec;
422 uec_t *uec_regs = uec->uec_regs;
423 uchar *mac = pdata->enetaddr;
424 u32 mac_addr1;
425 u32 mac_addr2;
426
427 /*
428 * if a station address of 0x12345678ABCD, perform a write to
429 * MACSTNADDR1 of 0xCDAB7856,
430 * MACSTNADDR2 of 0x34120000
431 */
432
433 mac_addr1 = (mac[5] << 24) | (mac[4] << 16) |
434 (mac[3] << 8) | (mac[2]);
435 out_be32(&uec_regs->macstnaddr1, mac_addr1);
436
437 mac_addr2 = ((mac[1] << 24) | (mac[0] << 16)) & 0xffff0000;
438 out_be32(&uec_regs->macstnaddr2, mac_addr2);
439
440 return 0;
441}
442
443static int qe_uec_free_pkt(struct udevice *dev, uchar *packet, int length)
444{
445 if (packet)
446 free(packet);
447
448 return 0;
449}
450
451static const struct eth_ops qe_uec_eth_ops = {
452 .start = qe_uec_start,
453 .send = qe_uec_send,
454 .recv = qe_uec_recv,
455 .free_pkt = qe_uec_free_pkt,
456 .stop = qe_uec_stop,
457 .write_hwaddr = qe_uec_set_hwaddr,
458};
459
460static int uec_convert_threads_num(enum uec_num_of_threads threads_num,
461 int *threads_num_ret)
462{
463 int num_threads_numerica;
464
465 switch (threads_num) {
466 case UEC_NUM_OF_THREADS_1:
467 num_threads_numerica = 1;
468 break;
469 case UEC_NUM_OF_THREADS_2:
470 num_threads_numerica = 2;
471 break;
472 case UEC_NUM_OF_THREADS_4:
473 num_threads_numerica = 4;
474 break;
475 case UEC_NUM_OF_THREADS_6:
476 num_threads_numerica = 6;
477 break;
478 case UEC_NUM_OF_THREADS_8:
479 num_threads_numerica = 8;
480 break;
481 default:
482 printf("%s: Bad number of threads value.",
483 __func__);
484 return -EINVAL;
485 }
486
487 *threads_num_ret = num_threads_numerica;
488
489 return 0;
490}
491
492static void uec_init_tx_parameter(struct uec_priv *uec, int num_threads_tx)
493{
494 struct uec_inf *uec_info;
495 u32 end_bd;
496 u8 bmrx = 0;
497 int i;
498
499 uec_info = uec->uec_info;
500
501 /* Alloc global Tx parameter RAM page */
502 uec->tx_glbl_pram_offset =
503 qe_muram_alloc(sizeof(struct uec_tx_global_pram),
504 UEC_TX_GLOBAL_PRAM_ALIGNMENT);
505 uec->p_tx_glbl_pram = (struct uec_tx_global_pram *)
506 qe_muram_addr(uec->tx_glbl_pram_offset);
507
508 /* Zero the global Tx prameter RAM */
509 memset(uec->p_tx_glbl_pram, 0, sizeof(struct uec_tx_global_pram));
510
511 /* Init global Tx parameter RAM */
512
513 /* TEMODER, RMON statistics disable, one Tx queue */
514 out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
515
516 /* SQPTR */
517 uec->send_q_mem_reg_offset =
518 qe_muram_alloc(sizeof(struct uec_send_queue_qd),
519 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
520 uec->p_send_q_mem_reg = (struct uec_send_queue_mem_region *)
521 qe_muram_addr(uec->send_q_mem_reg_offset);
522 out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
523
524 /* Setup the table with TxBDs ring */
525 end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
526 * SIZEOFBD;
527 out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
528 (u32)(uec->p_tx_bd_ring));
529 out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
530 end_bd);
531
532 /* Scheduler Base Pointer, we have only one Tx queue, no need it */
533 out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
534
535 /* TxRMON Base Pointer, TxRMON disable, we don't need it */
536 out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
537
538 /* TSTATE, global snooping, big endian, the CSB bus selected */
539 bmrx = BMR_INIT_VALUE;
540 out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
541
542 /* IPH_Offset */
543 for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++)
544 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
545
546 /* VTAG table */
547 for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++)
548 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
549
550 /* TQPTR */
551 uec->thread_dat_tx_offset =
552 qe_muram_alloc(num_threads_tx *
553 sizeof(struct uec_thread_data_tx) +
554 32 * (num_threads_tx == 1),
555 UEC_THREAD_DATA_ALIGNMENT);
556
557 uec->p_thread_data_tx = (struct uec_thread_data_tx *)
558 qe_muram_addr(uec->thread_dat_tx_offset);
559 out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
560}
561
562static void uec_init_rx_parameter(struct uec_priv *uec, int num_threads_rx)
563{
564 u8 bmrx = 0;
565 int i;
566 struct uec_82xx_add_filtering_pram *p_af_pram;
567
568 /* Allocate global Rx parameter RAM page */
569 uec->rx_glbl_pram_offset =
570 qe_muram_alloc(sizeof(struct uec_rx_global_pram),
571 UEC_RX_GLOBAL_PRAM_ALIGNMENT);
572 uec->p_rx_glbl_pram = (struct uec_rx_global_pram *)
573 qe_muram_addr(uec->rx_glbl_pram_offset);
574
575 /* Zero Global Rx parameter RAM */
576 memset(uec->p_rx_glbl_pram, 0, sizeof(struct uec_rx_global_pram));
577
578 /* Init global Rx parameter RAM */
579 /*
580 * REMODER, Extended feature mode disable, VLAN disable,
581 * LossLess flow control disable, Receive firmware statisic disable,
582 * Extended address parsing mode disable, One Rx queues,
583 * Dynamic maximum/minimum frame length disable, IP checksum check
584 * disable, IP address alignment disable
585 */
586 out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
587
588 /* RQPTR */
589 uec->thread_dat_rx_offset =
590 qe_muram_alloc(num_threads_rx *
591 sizeof(struct uec_thread_data_rx),
592 UEC_THREAD_DATA_ALIGNMENT);
593 uec->p_thread_data_rx = (struct uec_thread_data_rx *)
594 qe_muram_addr(uec->thread_dat_rx_offset);
595 out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
596
597 /* Type_or_Len */
598 out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
599
600 /* RxRMON base pointer, we don't need it */
601 out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
602
603 /* IntCoalescingPTR, we don't need it, no interrupt */
604 out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
605
606 /* RSTATE, global snooping, big endian, the CSB bus selected */
607 bmrx = BMR_INIT_VALUE;
608 out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
609
610 /* MRBLR */
611 out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
612
613 /* RBDQPTR */
614 uec->rx_bd_qs_tbl_offset =
615 qe_muram_alloc(sizeof(struct uec_rx_bd_queues_entry) +
616 sizeof(struct uec_rx_pref_bds),
617 UEC_RX_BD_QUEUES_ALIGNMENT);
618 uec->p_rx_bd_qs_tbl = (struct uec_rx_bd_queues_entry *)
619 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
620
621 /* Zero it */
622 memset(uec->p_rx_bd_qs_tbl, 0, sizeof(struct uec_rx_bd_queues_entry) +
623 sizeof(struct uec_rx_pref_bds));
624 out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
625 out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
626 (u32)uec->p_rx_bd_ring);
627
628 /* MFLR */
629 out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
630 /* MINFLR */
631 out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
632 /* MAXD1 */
633 out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
634 /* MAXD2 */
635 out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
636 /* ECAM_PTR */
637 out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
638 /* L2QT */
639 out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
640 /* L3QT */
641 for (i = 0; i < 8; i++)
642 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
643
644 /* VLAN_TYPE */
645 out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
646 /* TCI */
647 out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
648
649 /* Clear PQ2 style address filtering hash table */
650 p_af_pram = (struct uec_82xx_add_filtering_pram *)
651 uec->p_rx_glbl_pram->addressfiltering;
652
653 p_af_pram->iaddr_h = 0;
654 p_af_pram->iaddr_l = 0;
655 p_af_pram->gaddr_h = 0;
656 p_af_pram->gaddr_l = 0;
657}
658
659static int uec_issue_init_enet_rxtx_cmd(struct uec_priv *uec,
660 int thread_tx, int thread_rx)
661{
662 struct uec_init_cmd_pram *p_init_enet_param;
663 u32 init_enet_param_offset;
664 struct uec_inf *uec_info;
665 struct ucc_fast_inf *uf_info;
666 int i;
667 int snum;
668 u32 off;
669 u32 entry_val;
670 u32 command;
671 u32 cecr_subblock;
672
673 uec_info = uec->uec_info;
674 uf_info = &uec_info->uf_info;
675
676 /* Allocate init enet command parameter */
677 uec->init_enet_param_offset =
678 qe_muram_alloc(sizeof(struct uec_init_cmd_pram), 4);
679 init_enet_param_offset = uec->init_enet_param_offset;
680 uec->p_init_enet_param = (struct uec_init_cmd_pram *)
681 qe_muram_addr(uec->init_enet_param_offset);
682
683 /* Zero init enet command struct */
684 memset((void *)uec->p_init_enet_param, 0,
685 sizeof(struct uec_init_cmd_pram));
686
687 /* Init the command struct */
688 p_init_enet_param = uec->p_init_enet_param;
689 p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
690 p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
691 p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
692 p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
693 p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
694 p_init_enet_param->largestexternallookupkeysize = 0;
695
696 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
697 << ENET_INIT_PARAM_RGF_SHIFT;
698 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
699 << ENET_INIT_PARAM_TGF_SHIFT;
700
701 /* Init Rx global parameter pointer */
702 p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
703 (u32)uec_info->risc_rx;
704
705 /* Init Rx threads */
706 for (i = 0; i < (thread_rx + 1); i++) {
707 snum = qe_get_snum();
708 if (snum < 0) {
709 printf("%s can not get snum\n", __func__);
710 return -ENOMEM;
711 }
712
713 if (i == 0) {
714 off = 0;
715 } else {
716 off = qe_muram_alloc(sizeof(struct uec_thread_rx_pram),
717 UEC_THREAD_RX_PRAM_ALIGNMENT);
718 }
719
720 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
721 off | (u32)uec_info->risc_rx;
722 p_init_enet_param->rxthread[i] = entry_val;
723 }
724
725 /* Init Tx global parameter pointer */
726 p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
727 (u32)uec_info->risc_tx;
728
729 /* Init Tx threads */
730 for (i = 0; i < thread_tx; i++) {
731 snum = qe_get_snum();
732 if (snum < 0) {
733 printf("%s can not get snum\n", __func__);
734 return -ENOMEM;
735 }
736
737 off = qe_muram_alloc(sizeof(struct uec_thread_tx_pram),
738 UEC_THREAD_TX_PRAM_ALIGNMENT);
739
740 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
741 off | (u32)uec_info->risc_tx;
742 p_init_enet_param->txthread[i] = entry_val;
743 }
744
745 __asm__ __volatile__("sync");
746
747 /* Issue QE command */
748 command = QE_INIT_TX_RX;
749 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
750 qe_issue_cmd(command, cecr_subblock, (u8)QE_CR_PROTOCOL_ETHERNET,
751 init_enet_param_offset);
752
753 return 0;
754}
755
756static int uec_startup(struct udevice *dev)
757{
758 struct qe_uec_priv *priv = dev_get_priv(dev);
759 struct uec_priv *uec = priv->uec;
760 struct uec_inf *uec_info;
761 struct ucc_fast_inf *uf_info;
762 struct ucc_fast_priv *uccf;
763 ucc_fast_t *uf_regs;
764 uec_t *uec_regs;
765 int num_threads_tx;
766 int num_threads_rx;
767 u32 utbipar;
768 u32 length;
769 u32 align;
770 struct buffer_descriptor *bd;
771 u8 *buf;
772 int i;
773
774 uec_info = uec->uec_info;
775 uf_info = &uec_info->uf_info;
776
777 /* Check if Rx BD ring len is illegal */
778 if (uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN ||
779 uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT) {
780 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
781 __func__);
782 return -EINVAL;
783 }
784
785 /* Check if Tx BD ring len is illegal */
786 if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
787 printf("%s: Tx BD ring length must not be smaller than 2.\n",
788 __func__);
789 return -EINVAL;
790 }
791
792 /* Check if MRBLR is illegal */
793 if (MAX_RXBUF_LEN == 0 || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) {
794 printf("%s: max rx buffer length must be mutliple of 128.\n",
795 __func__);
796 return -EINVAL;
797 }
798
799 /* Both Rx and Tx are stopped */
800 uec->grace_stopped_rx = 1;
801 uec->grace_stopped_tx = 1;
802
803 /* Init UCC fast */
804 if (ucc_fast_init(uf_info, &uccf)) {
805 printf("%s: failed to init ucc fast\n", __func__);
806 return -ENOMEM;
807 }
808
809 /* Save uccf */
810 uec->uccf = uccf;
811
812 /* Convert the Tx threads number */
813 if (uec_convert_threads_num(uec_info->num_threads_tx,
814 &num_threads_tx))
815 return -EINVAL;
816
817 /* Convert the Rx threads number */
818 if (uec_convert_threads_num(uec_info->num_threads_rx,
819 &num_threads_rx))
820 return -EINVAL;
821
822 uf_regs = uccf->uf_regs;
823
824 /* UEC register is following UCC fast registers */
825 uec_regs = (uec_t *)(&uf_regs->ucc_eth);
826
827 /* Save the UEC register pointer to UEC private struct */
828 uec->uec_regs = uec_regs;
829
830 /* Init UPSMR, enable hardware statistics (UCC) */
831 out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
832
833 /* Init MACCFG1, flow control disable, disable Tx and Rx */
834 out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
835
836 /* Init MACCFG2, length check, MAC PAD and CRC enable */
837 out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
838
839 /* Setup UTBIPAR */
840 utbipar = in_be32(&uec_regs->utbipar);
841 utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
842
6e7df1d1 843 /* Initialize UTBIPAR address to CFG_UTBIPAR_INIT_TBIPA for ALL UEC.
6e31c62a
HS		 844 * This frees up the remaining SMI addresses for use.
845 */
6e7df1d1 846 utbipar |= CFG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
6e31c62a
HS		 847 out_be32(&uec_regs->utbipar, utbipar);
848
849 /* Allocate Tx BDs */
850 length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
851 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
852 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
853 if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
854 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
855 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
856
857 align = UEC_TX_BD_RING_ALIGNMENT;
858 uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
859 if (uec->tx_bd_ring_offset != 0)
860 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
861 & ~(align - 1));
862
863 /* Zero all of Tx BDs */
864 memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
865
866 /* Allocate Rx BDs */
867 length = uec_info->rx_bd_ring_len * SIZEOFBD;
868 align = UEC_RX_BD_RING_ALIGNMENT;
869 uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
870 if (uec->rx_bd_ring_offset != 0)
871 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
872 & ~(align - 1));
873
874 /* Zero all of Rx BDs */
875 memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
876
877 /* Allocate Rx buffer */
878 length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
879 align = UEC_RX_DATA_BUF_ALIGNMENT;
880 uec->rx_buf_offset = (u32)malloc(length + align);
881 if (uec->rx_buf_offset != 0)
882 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
883 & ~(align - 1));
884
885 /* Zero all of the Rx buffer */
886 memset((void *)(uec->rx_buf_offset), 0, length + align);
887
888 /* Init TxBD ring */
889 bd = (struct buffer_descriptor *)uec->p_tx_bd_ring;
890 uec->tx_bd = bd;
891
892 for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
893 BD_DATA_CLEAR(bd);
894 BD_STATUS_SET(bd, 0);
895 BD_LENGTH_SET(bd, 0);
896 bd++;
897 }
898 BD_STATUS_SET((--bd), TX_BD_WRAP);
899
900 /* Init RxBD ring */
901 bd = (struct buffer_descriptor *)uec->p_rx_bd_ring;
902 uec->rx_bd = bd;
903 buf = uec->p_rx_buf;
904 for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
905 BD_DATA_SET(bd, buf);
906 BD_LENGTH_SET(bd, 0);
907 BD_STATUS_SET(bd, RX_BD_EMPTY);
908 buf += MAX_RXBUF_LEN;
909 bd++;
910 }
911 BD_STATUS_SET((--bd), RX_BD_WRAP | RX_BD_EMPTY);
912
913 /* Init global Tx parameter RAM */
914 uec_init_tx_parameter(uec, num_threads_tx);
915
916 /* Init global Rx parameter RAM */
917 uec_init_rx_parameter(uec, num_threads_rx);
918
919 /* Init ethernet Tx and Rx parameter command */
920 if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
921 num_threads_rx)) {
922 printf("%s issue init enet cmd failed\n", __func__);
923 return -ENOMEM;
924 }
925 return 0;
926}
927
928/* Convert a string to a QE clock source enum
929 *
930 * This function takes a string, typically from a property in the device
931 * tree, and returns the corresponding "enum qe_clock" value.
932 */
933enum qe_clock qe_clock_source(const char *source)
934{
935 unsigned int i;
936
937 if (strcasecmp(source, "none") == 0)
938 return QE_CLK_NONE;
939
940 if (strncasecmp(source, "brg", 3) == 0) {
0b1284eb 941 i = dectoul(source + 3, NULL);
6e31c62a
HS		 942 if (i >= 1 && i <= 16)
943 return (QE_BRG1 - 1) + i;
944 else
945 return QE_CLK_DUMMY;
946 }
947
948 if (strncasecmp(source, "clk", 3) == 0) {
0b1284eb 949 i = dectoul(source + 3, NULL);
6e31c62a
HS		 950 if (i >= 1 && i <= 24)
951 return (QE_CLK1 - 1) + i;
952 else
953 return QE_CLK_DUMMY;
954 }
955
956 return QE_CLK_DUMMY;
957}
958
959static void qe_uec_set_eth_type(struct udevice *dev)
960{
961 struct qe_uec_priv *priv = dev_get_priv(dev);
962 struct uec_priv *uec = priv->uec;
963 struct uec_inf *uec_info = uec->uec_info;
964 struct ucc_fast_inf *uf_info = &uec_info->uf_info;
965
966 switch (uec_info->enet_interface_type) {
967 case PHY_INTERFACE_MODE_GMII:
968 case PHY_INTERFACE_MODE_RGMII:
969 case PHY_INTERFACE_MODE_RGMII_ID:
970 case PHY_INTERFACE_MODE_RGMII_RXID:
971 case PHY_INTERFACE_MODE_RGMII_TXID:
972 case PHY_INTERFACE_MODE_TBI:
973 case PHY_INTERFACE_MODE_RTBI:
974 case PHY_INTERFACE_MODE_SGMII:
975 uf_info->eth_type = GIGA_ETH;
976 break;
977 default:
978 uf_info->eth_type = FAST_ETH;
979 break;
980 }
981}
982
983static int qe_uec_set_uec_info(struct udevice *dev)
984{
985 struct qe_uec_priv *priv = dev_get_priv(dev);
c69cda25 986 struct eth_pdata *pdata = dev_get_plat(dev);
6e31c62a
HS		 987 struct uec_priv *uec = priv->uec;
988 struct uec_inf *uec_info;
989 struct ucc_fast_inf *uf_info;
990 const char *s;
991 int ret;
992 u32 val;
993
994 uec_info = (struct uec_inf *)malloc(sizeof(struct uec_inf));
995 if (!uec_info)
996 return -ENOMEM;
997
998 uf_info = &uec_info->uf_info;
999
1000 ret = dev_read_u32(dev, "cell-index", &val);
1001 if (ret) {
1002 ret = dev_read_u32(dev, "device-id", &val);
1003 if (ret) {
1004 pr_err("no cell-index nor device-id found!");
1005 goto out;
1006 }
1007 }
1008
1009 uf_info->ucc_num = val - 1;
1010 if (uf_info->ucc_num < 0 || uf_info->ucc_num > 7) {
1011 ret = -ENODEV;
1012 goto out;
1013 }
1014
1015 ret = dev_read_string_index(dev, "rx-clock-name", 0, &s);
1016 if (!ret) {
1017 uf_info->rx_clock = qe_clock_source(s);
1018 if (uf_info->rx_clock < QE_CLK_NONE ||
1019 uf_info->rx_clock > QE_CLK24) {
1020 pr_err("invalid rx-clock-name property\n");
1021 ret = -EINVAL;
1022 goto out;
1023 }
1024 } else {
1025 ret = dev_read_u32(dev, "rx-clock", &val);
1026 if (ret) {
1027 /*
1028 * If both rx-clock-name and rx-clock are missing,
1029 * we want to tell people to use rx-clock-name.
1030 */
1031 pr_err("missing rx-clock-name property\n");
1032 goto out;
1033 }
1034 if (val < QE_CLK_NONE || val > QE_CLK24) {
1035 pr_err("invalid rx-clock property\n");
1036 ret = -EINVAL;
1037 goto out;
1038 }
1039 uf_info->rx_clock = val;
1040 }
1041
1042 ret = dev_read_string_index(dev, "tx-clock-name", 0, &s);
1043 if (!ret) {
1044 uf_info->tx_clock = qe_clock_source(s);
1045 if (uf_info->tx_clock < QE_CLK_NONE ||
1046 uf_info->tx_clock > QE_CLK24) {
1047 pr_err("invalid tx-clock-name property\n");
1048 ret = -EINVAL;
1049 goto out;
1050 }
1051 } else {
1052 ret = dev_read_u32(dev, "tx-clock", &val);
1053 if (ret) {
1054 pr_err("missing tx-clock-name property\n");
1055 goto out;
1056 }
1057 if (val < QE_CLK_NONE || val > QE_CLK24) {
1058 pr_err("invalid tx-clock property\n");
1059 ret = -EINVAL;
1060 goto out;
1061 }
1062 uf_info->tx_clock = val;
1063 }
1064
1065 uec_info->num_threads_tx = UEC_NUM_OF_THREADS_1;
1066 uec_info->num_threads_rx = UEC_NUM_OF_THREADS_1;
1067 uec_info->risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2;
1068 uec_info->risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2;
1069 uec_info->tx_bd_ring_len = 16;
1070 uec_info->rx_bd_ring_len = 16;
1071#if (MAX_QE_RISC == 4)
1072 uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
1073 uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
1074#endif
1075
1076 uec_info->enet_interface_type = pdata->phy_interface;
1077
1078 uec->uec_info = uec_info;
1079 qe_uec_set_eth_type(dev);
1080
1081 return 0;
1082out:
1083 free(uec_info);
1084 return ret;
1085}
1086
1087static int qe_uec_probe(struct udevice *dev)
1088{
1089 struct qe_uec_priv *priv = dev_get_priv(dev);
c69cda25 1090 struct eth_pdata *pdata = dev_get_plat(dev);
6e31c62a
HS		 1091 struct uec_priv *uec;
1092 int ret;
1093
1094 /* Allocate the UEC private struct */
1095 uec = (struct uec_priv *)malloc(sizeof(struct uec_priv));
1096 if (!uec)
1097 return -ENOMEM;
1098
1099 memset(uec, 0, sizeof(struct uec_priv));
1100 priv->uec = uec;
1101 uec->uec_regs = (uec_t *)pdata->iobase;
1102
1103 /* setup uec info struct */
1104 ret = qe_uec_set_uec_info(dev);
1105 if (ret) {
1106 free(uec);
1107 return ret;
1108 }
1109
1110 ret = uec_startup(dev);
1111 if (ret) {
1112 free(uec->uec_info);
1113 free(uec);
1114 return ret;
1115 }
1116
1117 priv->phydev = dm_eth_phy_connect(dev);
1118 return 0;
1119}
1120
1121/*
1122 * Remove the driver from an interface:
1123 * - free up allocated memory
1124 */
1125static int qe_uec_remove(struct udevice *dev)
1126{
1127 struct qe_uec_priv *priv = dev_get_priv(dev);
1128
1129 free(priv->uec);
1130 return 0;
1131}
1132
d1998a9f 1133static int qe_uec_of_to_plat(struct udevice *dev)
6e31c62a 1134{
c69cda25 1135 struct eth_pdata *pdata = dev_get_plat(dev);
6e31c62a
HS		 1136
1137 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
1138
123ca114 1139 pdata->phy_interface = dev_read_phy_mode(dev);
ffb0f6f4 1140 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
6e31c62a 1141 return -EINVAL;
6e31c62a
HS		 1142
1143 return 0;
1144}
1145
1146static const struct udevice_id qe_uec_ids[] = {
1147 { .compatible = QE_UEC_DRIVER_NAME },
1148 { }
1149};
1150
1151U_BOOT_DRIVER(eth_qe_uec) = {
1152 .name = QE_UEC_DRIVER_NAME,
1153 .id = UCLASS_ETH,
1154 .of_match = qe_uec_ids,
d1998a9f 1155 .of_to_plat = qe_uec_of_to_plat,
6e31c62a
HS		 1156 .probe = qe_uec_probe,
1157 .remove = qe_uec_remove,
1158 .ops = &qe_uec_eth_ops,
41575d8e 1159 .priv_auto = sizeof(struct qe_uec_priv),
caa4daa2 1160 .plat_auto = sizeof(struct eth_pdata),
6e31c62a 1161};
"Das U-Boot" Source Tree