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Commit | Line | Data |
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9751ee09 | 1 | /* |
1cc0a9f4 | 2 | * sh_eth.c - Driver for Renesas ethernet controller. |
9751ee09 | 3 | * |
3bb4cc31 | 4 | * Copyright (C) 2008, 2011 Renesas Solutions Corp. |
f7ca1f76 | 5 | * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu |
9751ee09 | 6 | * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> |
f7ca1f76 | 7 | * Copyright (C) 2013, 2014 Renesas Electronics Corporation |
9751ee09 | 8 | * |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
9751ee09 NI |
10 | */ |
11 | ||
12 | #include <config.h> | |
13 | #include <common.h> | |
14 | #include <malloc.h> | |
15 | #include <net.h> | |
bd3980cc | 16 | #include <netdev.h> |
bd1024b0 | 17 | #include <miiphy.h> |
1221ce45 | 18 | #include <linux/errno.h> |
9751ee09 NI |
19 | #include <asm/io.h> |
20 | ||
21 | #include "sh_eth.h" | |
22 | ||
23 | #ifndef CONFIG_SH_ETHER_USE_PORT | |
24 | # error "Please define CONFIG_SH_ETHER_USE_PORT" | |
25 | #endif | |
26 | #ifndef CONFIG_SH_ETHER_PHY_ADDR | |
27 | # error "Please define CONFIG_SH_ETHER_PHY_ADDR" | |
28 | #endif | |
870cc23f | 29 | |
92f07134 NI |
30 | #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF) |
31 | #define flush_cache_wback(addr, len) \ | |
aae5d237 NI |
32 | flush_dcache_range((u32)addr, \ |
33 | (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE))) | |
68260aab YS |
34 | #else |
35 | #define flush_cache_wback(...) | |
36 | #endif | |
9751ee09 | 37 | |
92f07134 NI |
38 | #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) |
39 | #define invalidate_cache(addr, len) \ | |
40 | { \ | |
41 | u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \ | |
42 | u32 start, end; \ | |
43 | \ | |
44 | start = (u32)addr; \ | |
45 | end = start + len; \ | |
46 | start &= ~(line_size - 1); \ | |
47 | end = ((end + line_size - 1) & ~(line_size - 1)); \ | |
48 | \ | |
49 | invalidate_dcache_range(start, end); \ | |
50 | } | |
51 | #else | |
52 | #define invalidate_cache(...) | |
53 | #endif | |
54 | ||
4ba62c72 NI |
55 | #define TIMEOUT_CNT 1000 |
56 | ||
dca221bd | 57 | static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len) |
9751ee09 | 58 | { |
bd3980cc NI |
59 | int port = eth->port, ret = 0, timeout; |
60 | struct sh_eth_info *port_info = ð->port_info[port]; | |
9751ee09 NI |
61 | |
62 | if (!packet || len > 0xffff) { | |
bd3980cc NI |
63 | printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); |
64 | ret = -EINVAL; | |
65 | goto err; | |
9751ee09 NI |
66 | } |
67 | ||
68 | /* packet must be a 4 byte boundary */ | |
ee6ec5d4 | 69 | if ((int)packet & 3) { |
dc14867d | 70 | printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n" |
e2752db0 | 71 | , __func__); |
bd3980cc NI |
72 | ret = -EFAULT; |
73 | goto err; | |
9751ee09 NI |
74 | } |
75 | ||
76 | /* Update tx descriptor */ | |
68260aab | 77 | flush_cache_wback(packet, len); |
9751ee09 NI |
78 | port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); |
79 | port_info->tx_desc_cur->td1 = len << 16; | |
80 | /* Must preserve the end of descriptor list indication */ | |
81 | if (port_info->tx_desc_cur->td0 & TD_TDLE) | |
82 | port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; | |
83 | else | |
84 | port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; | |
85 | ||
f7ca1f76 NI |
86 | flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s)); |
87 | ||
9751ee09 | 88 | /* Restart the transmitter if disabled */ |
fbfb5115 NI |
89 | if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS)) |
90 | sh_eth_write(port_info, EDTRR_TRNS, EDTRR); | |
9751ee09 NI |
91 | |
92 | /* Wait until packet is transmitted */ | |
4ba62c72 | 93 | timeout = TIMEOUT_CNT; |
92f07134 NI |
94 | do { |
95 | invalidate_cache(port_info->tx_desc_cur, | |
96 | sizeof(struct tx_desc_s)); | |
9751ee09 | 97 | udelay(100); |
92f07134 | 98 | } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--); |
9751ee09 NI |
99 | |
100 | if (timeout < 0) { | |
bd3980cc NI |
101 | printf(SHETHER_NAME ": transmit timeout\n"); |
102 | ret = -ETIMEDOUT; | |
9751ee09 NI |
103 | goto err; |
104 | } | |
105 | ||
9751ee09 NI |
106 | port_info->tx_desc_cur++; |
107 | if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) | |
108 | port_info->tx_desc_cur = port_info->tx_desc_base; | |
109 | ||
bd3980cc NI |
110 | err: |
111 | return ret; | |
9751ee09 NI |
112 | } |
113 | ||
dca221bd | 114 | static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len) |
9751ee09 | 115 | { |
bd3980cc | 116 | struct sh_eth_dev *eth = dev->priv; |
dca221bd MV |
117 | |
118 | return sh_eth_send_common(eth, packet, len); | |
119 | } | |
120 | ||
52c15e22 | 121 | static int sh_eth_recv_start(struct sh_eth_dev *eth) |
dca221bd | 122 | { |
bd3980cc NI |
123 | int port = eth->port, len = 0; |
124 | struct sh_eth_info *port_info = ð->port_info[port]; | |
9751ee09 NI |
125 | |
126 | /* Check if the rx descriptor is ready */ | |
92f07134 | 127 | invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); |
52c15e22 MV |
128 | if (port_info->rx_desc_cur->rd0 & RD_RACT) |
129 | return -EINVAL; | |
130 | ||
131 | /* Check for errors */ | |
132 | if (port_info->rx_desc_cur->rd0 & RD_RFE) | |
133 | return -EINVAL; | |
134 | ||
135 | len = port_info->rx_desc_cur->rd1 & 0xffff; | |
136 | ||
137 | return len; | |
138 | } | |
139 | ||
140 | static void sh_eth_recv_finish(struct sh_eth_dev *eth) | |
141 | { | |
142 | struct sh_eth_info *port_info = ð->port_info[eth->port]; | |
143 | ||
144 | /* Make current descriptor available again */ | |
145 | if (port_info->rx_desc_cur->rd0 & RD_RDLE) | |
146 | port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; | |
147 | else | |
148 | port_info->rx_desc_cur->rd0 = RD_RACT; | |
149 | ||
150 | flush_cache_wback(port_info->rx_desc_cur, | |
151 | sizeof(struct rx_desc_s)); | |
152 | ||
153 | /* Point to the next descriptor */ | |
154 | port_info->rx_desc_cur++; | |
155 | if (port_info->rx_desc_cur >= | |
156 | port_info->rx_desc_base + NUM_RX_DESC) | |
157 | port_info->rx_desc_cur = port_info->rx_desc_base; | |
158 | } | |
159 | ||
160 | static int sh_eth_recv_common(struct sh_eth_dev *eth) | |
161 | { | |
162 | int port = eth->port, len = 0; | |
163 | struct sh_eth_info *port_info = ð->port_info[port]; | |
164 | uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2); | |
165 | ||
166 | len = sh_eth_recv_start(eth); | |
167 | if (len > 0) { | |
168 | invalidate_cache(packet, len); | |
169 | net_process_received_packet(packet, len); | |
170 | sh_eth_recv_finish(eth); | |
171 | } else | |
172 | len = 0; | |
9751ee09 NI |
173 | |
174 | /* Restart the receiver if disabled */ | |
fbfb5115 NI |
175 | if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R)) |
176 | sh_eth_write(port_info, EDRRR_R, EDRRR); | |
9751ee09 NI |
177 | |
178 | return len; | |
179 | } | |
180 | ||
dca221bd MV |
181 | static int sh_eth_recv_legacy(struct eth_device *dev) |
182 | { | |
183 | struct sh_eth_dev *eth = dev->priv; | |
184 | ||
185 | return sh_eth_recv_common(eth); | |
186 | } | |
187 | ||
bd3980cc | 188 | static int sh_eth_reset(struct sh_eth_dev *eth) |
9751ee09 | 189 | { |
fbfb5115 | 190 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
62cbddc4 | 191 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) |
bd3980cc | 192 | int ret = 0, i; |
9751ee09 NI |
193 | |
194 | /* Start e-dmac transmitter and receiver */ | |
fbfb5115 | 195 | sh_eth_write(port_info, EDSR_ENALL, EDSR); |
9751ee09 NI |
196 | |
197 | /* Perform a software reset and wait for it to complete */ | |
fbfb5115 | 198 | sh_eth_write(port_info, EDMR_SRST, EDMR); |
e2752db0 | 199 | for (i = 0; i < TIMEOUT_CNT; i++) { |
fbfb5115 | 200 | if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST)) |
9751ee09 NI |
201 | break; |
202 | udelay(1000); | |
203 | } | |
204 | ||
4ba62c72 | 205 | if (i == TIMEOUT_CNT) { |
bd3980cc NI |
206 | printf(SHETHER_NAME ": Software reset timeout\n"); |
207 | ret = -EIO; | |
9751ee09 | 208 | } |
bd3980cc NI |
209 | |
210 | return ret; | |
903de461 | 211 | #else |
fbfb5115 | 212 | sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR); |
903de461 | 213 | udelay(3000); |
fbfb5115 NI |
214 | sh_eth_write(port_info, |
215 | sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR); | |
903de461 YS |
216 | |
217 | return 0; | |
218 | #endif | |
9751ee09 NI |
219 | } |
220 | ||
bd3980cc | 221 | static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) |
9751ee09 | 222 | { |
bd3980cc | 223 | int port = eth->port, i, ret = 0; |
000889cd | 224 | u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s); |
bd3980cc | 225 | struct sh_eth_info *port_info = ð->port_info[port]; |
9751ee09 | 226 | struct tx_desc_s *cur_tx_desc; |
9751ee09 | 227 | |
bd3980cc | 228 | /* |
703949e4 NI |
229 | * Allocate rx descriptors. They must be aligned to size of struct |
230 | * tx_desc_s. | |
bd3980cc | 231 | */ |
000889cd NI |
232 | port_info->tx_desc_alloc = |
233 | memalign(sizeof(struct tx_desc_s), alloc_desc_size); | |
234 | if (!port_info->tx_desc_alloc) { | |
235 | printf(SHETHER_NAME ": memalign failed\n"); | |
bd3980cc NI |
236 | ret = -ENOMEM; |
237 | goto err; | |
9751ee09 | 238 | } |
bd3980cc | 239 | |
aae5d237 | 240 | flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size); |
000889cd | 241 | |
9751ee09 | 242 | /* Make sure we use a P2 address (non-cacheable) */ |
000889cd NI |
243 | port_info->tx_desc_base = |
244 | (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc); | |
9751ee09 NI |
245 | port_info->tx_desc_cur = port_info->tx_desc_base; |
246 | ||
247 | /* Initialize all descriptors */ | |
248 | for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; | |
249 | cur_tx_desc++, i++) { | |
250 | cur_tx_desc->td0 = 0x00; | |
251 | cur_tx_desc->td1 = 0x00; | |
252 | cur_tx_desc->td2 = 0x00; | |
253 | } | |
254 | ||
255 | /* Mark the end of the descriptors */ | |
256 | cur_tx_desc--; | |
257 | cur_tx_desc->td0 |= TD_TDLE; | |
258 | ||
dc14867d NI |
259 | /* |
260 | * Point the controller to the tx descriptor list. Must use physical | |
261 | * addresses | |
262 | */ | |
fbfb5115 | 263 | sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); |
62cbddc4 | 264 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) |
fbfb5115 NI |
265 | sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); |
266 | sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR); | |
267 | sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */ | |
903de461 | 268 | #endif |
9751ee09 | 269 | |
bd3980cc NI |
270 | err: |
271 | return ret; | |
9751ee09 NI |
272 | } |
273 | ||
bd3980cc | 274 | static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) |
9751ee09 | 275 | { |
dc14867d | 276 | int port = eth->port, i, ret = 0; |
000889cd | 277 | u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s); |
bd3980cc | 278 | struct sh_eth_info *port_info = ð->port_info[port]; |
9751ee09 NI |
279 | struct rx_desc_s *cur_rx_desc; |
280 | u8 *rx_buf; | |
9751ee09 | 281 | |
bd3980cc | 282 | /* |
703949e4 NI |
283 | * Allocate rx descriptors. They must be aligned to size of struct |
284 | * rx_desc_s. | |
bd3980cc | 285 | */ |
000889cd NI |
286 | port_info->rx_desc_alloc = |
287 | memalign(sizeof(struct rx_desc_s), alloc_desc_size); | |
288 | if (!port_info->rx_desc_alloc) { | |
289 | printf(SHETHER_NAME ": memalign failed\n"); | |
bd3980cc NI |
290 | ret = -ENOMEM; |
291 | goto err; | |
9751ee09 | 292 | } |
bd3980cc | 293 | |
000889cd NI |
294 | flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size); |
295 | ||
9751ee09 | 296 | /* Make sure we use a P2 address (non-cacheable) */ |
000889cd NI |
297 | port_info->rx_desc_base = |
298 | (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc); | |
9751ee09 NI |
299 | |
300 | port_info->rx_desc_cur = port_info->rx_desc_base; | |
301 | ||
bd3980cc | 302 | /* |
000889cd NI |
303 | * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes |
304 | * aligned and in P2 area. | |
bd3980cc | 305 | */ |
000889cd NI |
306 | port_info->rx_buf_alloc = |
307 | memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE); | |
308 | if (!port_info->rx_buf_alloc) { | |
309 | printf(SHETHER_NAME ": alloc failed\n"); | |
bd3980cc | 310 | ret = -ENOMEM; |
000889cd | 311 | goto err_buf_alloc; |
9751ee09 | 312 | } |
bd3980cc | 313 | |
000889cd | 314 | port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc); |
9751ee09 NI |
315 | |
316 | /* Initialize all descriptors */ | |
317 | for (cur_rx_desc = port_info->rx_desc_base, | |
318 | rx_buf = port_info->rx_buf_base, i = 0; | |
319 | i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { | |
320 | cur_rx_desc->rd0 = RD_RACT; | |
321 | cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; | |
dc14867d | 322 | cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf); |
9751ee09 NI |
323 | } |
324 | ||
325 | /* Mark the end of the descriptors */ | |
326 | cur_rx_desc--; | |
327 | cur_rx_desc->rd0 |= RD_RDLE; | |
328 | ||
329 | /* Point the controller to the rx descriptor list */ | |
fbfb5115 | 330 | sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); |
62cbddc4 | 331 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) |
fbfb5115 NI |
332 | sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); |
333 | sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR); | |
334 | sh_eth_write(port_info, RDFFR_RDLF, RDFFR); | |
903de461 | 335 | #endif |
9751ee09 | 336 | |
bd3980cc NI |
337 | return ret; |
338 | ||
000889cd NI |
339 | err_buf_alloc: |
340 | free(port_info->rx_desc_alloc); | |
341 | port_info->rx_desc_alloc = NULL; | |
bd3980cc NI |
342 | |
343 | err: | |
344 | return ret; | |
9751ee09 NI |
345 | } |
346 | ||
bd3980cc | 347 | static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) |
9751ee09 | 348 | { |
bd3980cc NI |
349 | int port = eth->port; |
350 | struct sh_eth_info *port_info = ð->port_info[port]; | |
9751ee09 | 351 | |
000889cd NI |
352 | if (port_info->tx_desc_alloc) { |
353 | free(port_info->tx_desc_alloc); | |
354 | port_info->tx_desc_alloc = NULL; | |
9751ee09 | 355 | } |
bd3980cc NI |
356 | } |
357 | ||
358 | static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) | |
359 | { | |
360 | int port = eth->port; | |
361 | struct sh_eth_info *port_info = ð->port_info[port]; | |
9751ee09 | 362 | |
000889cd NI |
363 | if (port_info->rx_desc_alloc) { |
364 | free(port_info->rx_desc_alloc); | |
365 | port_info->rx_desc_alloc = NULL; | |
9751ee09 NI |
366 | } |
367 | ||
000889cd NI |
368 | if (port_info->rx_buf_alloc) { |
369 | free(port_info->rx_buf_alloc); | |
370 | port_info->rx_buf_alloc = NULL; | |
9751ee09 NI |
371 | } |
372 | } | |
373 | ||
bd3980cc | 374 | static int sh_eth_desc_init(struct sh_eth_dev *eth) |
9751ee09 | 375 | { |
bd3980cc | 376 | int ret = 0; |
9751ee09 | 377 | |
bd3980cc NI |
378 | ret = sh_eth_tx_desc_init(eth); |
379 | if (ret) | |
380 | goto err_tx_init; | |
9751ee09 | 381 | |
bd3980cc NI |
382 | ret = sh_eth_rx_desc_init(eth); |
383 | if (ret) | |
384 | goto err_rx_init; | |
385 | ||
386 | return ret; | |
387 | err_rx_init: | |
388 | sh_eth_tx_desc_free(eth); | |
389 | ||
390 | err_tx_init: | |
391 | return ret; | |
9751ee09 NI |
392 | } |
393 | ||
68ac92e9 MV |
394 | static void sh_eth_write_hwaddr(struct sh_eth_info *port_info, |
395 | unsigned char *mac) | |
396 | { | |
397 | u32 val; | |
398 | ||
399 | val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; | |
400 | sh_eth_write(port_info, val, MAHR); | |
401 | ||
402 | val = (mac[4] << 8) | mac[5]; | |
403 | sh_eth_write(port_info, val, MALR); | |
404 | } | |
405 | ||
bd3980cc | 406 | static int sh_eth_phy_config(struct sh_eth_dev *eth) |
9751ee09 | 407 | { |
bd1024b0 | 408 | int port = eth->port, ret = 0; |
bd3980cc | 409 | struct sh_eth_info *port_info = ð->port_info[port]; |
bd1024b0 YS |
410 | struct eth_device *dev = port_info->dev; |
411 | struct phy_device *phydev; | |
9751ee09 | 412 | |
ee6ec5d4 NI |
413 | phydev = phy_connect( |
414 | miiphy_get_dev_by_name(dev->name), | |
4398d559 | 415 | port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE); |
bd1024b0 YS |
416 | port_info->phydev = phydev; |
417 | phy_config(phydev); | |
bd3980cc | 418 | |
bd3980cc | 419 | return ret; |
9751ee09 NI |
420 | } |
421 | ||
9b5f9ecf | 422 | static int sh_eth_config(struct sh_eth_dev *eth) |
9751ee09 | 423 | { |
bd3980cc | 424 | int port = eth->port, ret = 0; |
bd1024b0 | 425 | u32 val; |
bd3980cc | 426 | struct sh_eth_info *port_info = ð->port_info[port]; |
c527ce92 | 427 | struct eth_device *dev = port_info->dev; |
bd1024b0 | 428 | struct phy_device *phy; |
9751ee09 NI |
429 | |
430 | /* Configure e-dmac registers */ | |
fbfb5115 | 431 | sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) | |
f8b7507d NI |
432 | (EMDR_DESC | EDMR_EL), EDMR); |
433 | ||
fbfb5115 NI |
434 | sh_eth_write(port_info, 0, EESIPR); |
435 | sh_eth_write(port_info, 0, TRSCER); | |
436 | sh_eth_write(port_info, 0, TFTR); | |
437 | sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); | |
438 | sh_eth_write(port_info, RMCR_RST, RMCR); | |
62cbddc4 | 439 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) |
fbfb5115 | 440 | sh_eth_write(port_info, 0, RPADIR); |
903de461 | 441 | #endif |
fbfb5115 | 442 | sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); |
9751ee09 NI |
443 | |
444 | /* Configure e-mac registers */ | |
fbfb5115 | 445 | sh_eth_write(port_info, 0, ECSIPR); |
9751ee09 NI |
446 | |
447 | /* Set Mac address */ | |
68ac92e9 | 448 | sh_eth_write_hwaddr(port_info, dev->enetaddr); |
9751ee09 | 449 | |
fbfb5115 | 450 | sh_eth_write(port_info, RFLR_RFL_MIN, RFLR); |
26235093 | 451 | #if defined(SH_ETH_TYPE_GETHER) |
fbfb5115 | 452 | sh_eth_write(port_info, 0, PIPR); |
62cbddc4 NI |
453 | #endif |
454 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) | |
fbfb5115 NI |
455 | sh_eth_write(port_info, APR_AP, APR); |
456 | sh_eth_write(port_info, MPR_MP, MPR); | |
457 | sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER); | |
903de461 | 458 | #endif |
3bb4cc31 | 459 | |
dcd5a593 | 460 | #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) |
fbfb5115 | 461 | sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); |
effb7902 | 462 | #elif defined(CONFIG_RCAR_GEN2) |
fbfb5115 | 463 | sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR); |
4398d559 | 464 | #endif |
9751ee09 | 465 | /* Configure phy */ |
bd3980cc NI |
466 | ret = sh_eth_phy_config(eth); |
467 | if (ret) { | |
88a4c2e7 | 468 | printf(SHETHER_NAME ": phy config timeout\n"); |
bd3980cc NI |
469 | goto err_phy_cfg; |
470 | } | |
bd1024b0 | 471 | phy = port_info->phydev; |
11af8d65 TT |
472 | ret = phy_startup(phy); |
473 | if (ret) { | |
474 | printf(SHETHER_NAME ": phy startup failure\n"); | |
475 | return ret; | |
476 | } | |
9751ee09 | 477 | |
3bb4cc31 NI |
478 | val = 0; |
479 | ||
9751ee09 | 480 | /* Set the transfer speed */ |
bd1024b0 | 481 | if (phy->speed == 100) { |
bd3980cc | 482 | printf(SHETHER_NAME ": 100Base/"); |
26235093 | 483 | #if defined(SH_ETH_TYPE_GETHER) |
fbfb5115 | 484 | sh_eth_write(port_info, GECMR_100B, GECMR); |
e3bb3254 | 485 | #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) |
fbfb5115 | 486 | sh_eth_write(port_info, 1, RTRATE); |
effb7902 | 487 | #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2) |
3bb4cc31 NI |
488 | val = ECMR_RTM; |
489 | #endif | |
bd1024b0 | 490 | } else if (phy->speed == 10) { |
bd3980cc | 491 | printf(SHETHER_NAME ": 10Base/"); |
26235093 | 492 | #if defined(SH_ETH_TYPE_GETHER) |
fbfb5115 | 493 | sh_eth_write(port_info, GECMR_10B, GECMR); |
e3bb3254 | 494 | #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) |
fbfb5115 | 495 | sh_eth_write(port_info, 0, RTRATE); |
903de461 | 496 | #endif |
3bb4cc31 | 497 | } |
26235093 | 498 | #if defined(SH_ETH_TYPE_GETHER) |
4398d559 NI |
499 | else if (phy->speed == 1000) { |
500 | printf(SHETHER_NAME ": 1000Base/"); | |
fbfb5115 | 501 | sh_eth_write(port_info, GECMR_1000B, GECMR); |
4398d559 NI |
502 | } |
503 | #endif | |
9751ee09 NI |
504 | |
505 | /* Check if full duplex mode is supported by the phy */ | |
bd1024b0 | 506 | if (phy->duplex) { |
9751ee09 | 507 | printf("Full\n"); |
fbfb5115 | 508 | sh_eth_write(port_info, |
dc14867d | 509 | val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM), |
49afb8ca | 510 | ECMR); |
9751ee09 NI |
511 | } else { |
512 | printf("Half\n"); | |
fbfb5115 | 513 | sh_eth_write(port_info, |
dc14867d NI |
514 | val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE), |
515 | ECMR); | |
9751ee09 | 516 | } |
bd3980cc NI |
517 | |
518 | return ret; | |
519 | ||
520 | err_phy_cfg: | |
521 | return ret; | |
9751ee09 NI |
522 | } |
523 | ||
bd3980cc | 524 | static void sh_eth_start(struct sh_eth_dev *eth) |
9751ee09 | 525 | { |
fbfb5115 NI |
526 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
527 | ||
9751ee09 NI |
528 | /* |
529 | * Enable the e-dmac receiver only. The transmitter will be enabled when | |
530 | * we have something to transmit | |
531 | */ | |
fbfb5115 | 532 | sh_eth_write(port_info, EDRRR_R, EDRRR); |
bd3980cc | 533 | } |
9751ee09 | 534 | |
bd3980cc NI |
535 | static void sh_eth_stop(struct sh_eth_dev *eth) |
536 | { | |
fbfb5115 NI |
537 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
538 | ||
539 | sh_eth_write(port_info, ~EDRRR_R, EDRRR); | |
9751ee09 NI |
540 | } |
541 | ||
bd3980cc | 542 | int sh_eth_init(struct eth_device *dev, bd_t *bd) |
9751ee09 | 543 | { |
bd3980cc NI |
544 | int ret = 0; |
545 | struct sh_eth_dev *eth = dev->priv; | |
9751ee09 | 546 | |
bd3980cc NI |
547 | ret = sh_eth_reset(eth); |
548 | if (ret) | |
549 | goto err; | |
9751ee09 | 550 | |
bd3980cc NI |
551 | ret = sh_eth_desc_init(eth); |
552 | if (ret) | |
553 | goto err; | |
9751ee09 | 554 | |
9b5f9ecf | 555 | ret = sh_eth_config(eth); |
bd3980cc NI |
556 | if (ret) |
557 | goto err_config; | |
558 | ||
559 | sh_eth_start(eth); | |
560 | ||
561 | return ret; | |
9751ee09 | 562 | |
bd3980cc NI |
563 | err_config: |
564 | sh_eth_tx_desc_free(eth); | |
565 | sh_eth_rx_desc_free(eth); | |
566 | ||
567 | err: | |
568 | return ret; | |
569 | } | |
570 | ||
571 | void sh_eth_halt(struct eth_device *dev) | |
572 | { | |
573 | struct sh_eth_dev *eth = dev->priv; | |
dc14867d | 574 | |
bd3980cc NI |
575 | sh_eth_stop(eth); |
576 | } | |
577 | ||
578 | int sh_eth_initialize(bd_t *bd) | |
579 | { | |
e2752db0 | 580 | int ret = 0; |
bd3980cc | 581 | struct sh_eth_dev *eth = NULL; |
e2752db0 | 582 | struct eth_device *dev = NULL; |
dc14867d | 583 | struct mii_dev *mdiodev; |
bd3980cc | 584 | |
e2752db0 | 585 | eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); |
bd3980cc NI |
586 | if (!eth) { |
587 | printf(SHETHER_NAME ": %s: malloc failed\n", __func__); | |
588 | ret = -ENOMEM; | |
9751ee09 | 589 | goto err; |
bd3980cc | 590 | } |
9751ee09 | 591 | |
e2752db0 | 592 | dev = (struct eth_device *)malloc(sizeof(struct eth_device)); |
bd3980cc NI |
593 | if (!dev) { |
594 | printf(SHETHER_NAME ": %s: malloc failed\n", __func__); | |
595 | ret = -ENOMEM; | |
596 | goto err; | |
597 | } | |
e2752db0 NI |
598 | memset(dev, 0, sizeof(struct eth_device)); |
599 | memset(eth, 0, sizeof(struct sh_eth_dev)); | |
9751ee09 | 600 | |
bd3980cc NI |
601 | eth->port = CONFIG_SH_ETHER_USE_PORT; |
602 | eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; | |
fbfb5115 NI |
603 | eth->port_info[eth->port].iobase = |
604 | (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port); | |
bd3980cc | 605 | |
e2752db0 NI |
606 | dev->priv = (void *)eth; |
607 | dev->iobase = 0; | |
608 | dev->init = sh_eth_init; | |
609 | dev->halt = sh_eth_halt; | |
dca221bd MV |
610 | dev->send = sh_eth_send_legacy; |
611 | dev->recv = sh_eth_recv_legacy; | |
e2752db0 | 612 | eth->port_info[eth->port].dev = dev; |
bd3980cc | 613 | |
192bc694 | 614 | strcpy(dev->name, SHETHER_NAME); |
bd3980cc | 615 | |
e2752db0 NI |
616 | /* Register Device to EtherNet subsystem */ |
617 | eth_register(dev); | |
bd3980cc | 618 | |
bd1024b0 | 619 | bb_miiphy_buses[0].priv = eth; |
dc14867d | 620 | mdiodev = mdio_alloc(); |
5a49f174 JH |
621 | if (!mdiodev) |
622 | return -ENOMEM; | |
623 | strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); | |
624 | mdiodev->read = bb_miiphy_read; | |
625 | mdiodev->write = bb_miiphy_write; | |
626 | ||
dc14867d NI |
627 | ret = mdio_register(mdiodev); |
628 | if (ret < 0) | |
629 | return ret; | |
bd1024b0 | 630 | |
35affd7a | 631 | if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr)) |
c527ce92 | 632 | puts("Please set MAC address\n"); |
bd3980cc NI |
633 | |
634 | return ret; | |
9751ee09 | 635 | |
9751ee09 | 636 | err: |
bd3980cc NI |
637 | if (dev) |
638 | free(dev); | |
639 | ||
640 | if (eth) | |
641 | free(eth); | |
642 | ||
643 | printf(SHETHER_NAME ": Failed\n"); | |
644 | return ret; | |
9751ee09 | 645 | } |
bd1024b0 YS |
646 | |
647 | /******* for bb_miiphy *******/ | |
648 | static int sh_eth_bb_init(struct bb_miiphy_bus *bus) | |
649 | { | |
650 | return 0; | |
651 | } | |
652 | ||
653 | static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) | |
654 | { | |
655 | struct sh_eth_dev *eth = bus->priv; | |
fbfb5115 | 656 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
bd1024b0 | 657 | |
fbfb5115 | 658 | sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR); |
bd1024b0 YS |
659 | |
660 | return 0; | |
661 | } | |
662 | ||
663 | static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) | |
664 | { | |
665 | struct sh_eth_dev *eth = bus->priv; | |
fbfb5115 | 666 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
bd1024b0 | 667 | |
fbfb5115 | 668 | sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR); |
bd1024b0 YS |
669 | |
670 | return 0; | |
671 | } | |
672 | ||
673 | static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) | |
674 | { | |
675 | struct sh_eth_dev *eth = bus->priv; | |
fbfb5115 | 676 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
bd1024b0 YS |
677 | |
678 | if (v) | |
fbfb5115 NI |
679 | sh_eth_write(port_info, |
680 | sh_eth_read(port_info, PIR) | PIR_MDO, PIR); | |
bd1024b0 | 681 | else |
fbfb5115 NI |
682 | sh_eth_write(port_info, |
683 | sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR); | |
bd1024b0 YS |
684 | |
685 | return 0; | |
686 | } | |
687 | ||
688 | static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) | |
689 | { | |
690 | struct sh_eth_dev *eth = bus->priv; | |
fbfb5115 | 691 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
bd1024b0 | 692 | |
fbfb5115 | 693 | *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3; |
bd1024b0 YS |
694 | |
695 | return 0; | |
696 | } | |
697 | ||
698 | static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) | |
699 | { | |
700 | struct sh_eth_dev *eth = bus->priv; | |
fbfb5115 | 701 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
bd1024b0 YS |
702 | |
703 | if (v) | |
fbfb5115 NI |
704 | sh_eth_write(port_info, |
705 | sh_eth_read(port_info, PIR) | PIR_MDC, PIR); | |
bd1024b0 | 706 | else |
fbfb5115 NI |
707 | sh_eth_write(port_info, |
708 | sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR); | |
bd1024b0 YS |
709 | |
710 | return 0; | |
711 | } | |
712 | ||
713 | static int sh_eth_bb_delay(struct bb_miiphy_bus *bus) | |
714 | { | |
715 | udelay(10); | |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
720 | struct bb_miiphy_bus bb_miiphy_buses[] = { | |
721 | { | |
722 | .name = "sh_eth", | |
723 | .init = sh_eth_bb_init, | |
724 | .mdio_active = sh_eth_bb_mdio_active, | |
725 | .mdio_tristate = sh_eth_bb_mdio_tristate, | |
726 | .set_mdio = sh_eth_bb_set_mdio, | |
727 | .get_mdio = sh_eth_bb_get_mdio, | |
728 | .set_mdc = sh_eth_bb_set_mdc, | |
729 | .delay = sh_eth_bb_delay, | |
730 | } | |
731 | }; | |
dc14867d | 732 | |
bd1024b0 | 733 | int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); |