[people/ms/u-boot.git] / drivers / net / sh_eth.c

/*
 * sh_eth.c - Driver for Renesas SH7763's ethernet controler.
 *
 * Copyright (C) 2008 Renesas Solutions Corp.
 * Copyright (c) 2008 Nobuhiro Iwamatsu
 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <config.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/errno.h>
#include <asm/io.h>

#include "sh_eth.h"

#ifndef CONFIG_SH_ETHER_USE_PORT
# error "Please define CONFIG_SH_ETHER_USE_PORT"
#endif
#ifndef CONFIG_SH_ETHER_PHY_ADDR
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#endif

#define SH_ETH_PHY_DELAY 50000

/*
 * Bits are written to the PHY serially using the
 * PIR register, just like a bit banger.
 */
static void sh_eth_mii_write_phy_bits(int port, u32 val, int len)
{
	int i;
	u32 pir;

	/* Bit positions is 1 less than the number of bits */
	for (i = len - 1; i >= 0; i--) {
		/* Write direction, bit to write, clock is low */
		pir = 2 | ((val & 1 << i) ? 1 << 2 : 0);
		outl(pir, PIR(port));
		udelay(1);
		/* Write direction, bit to write, clock is high */
		pir = 3 | ((val & 1 << i) ? 1 << 2 : 0);
		outl(pir, PIR(port));
		udelay(1);
		/* Write direction, bit to write, clock is low */
		pir = 2 | ((val & 1 << i) ? 1 << 2 : 0);
		outl(pir, PIR(port));
		udelay(1);
	}
}

static void sh_eth_mii_bus_release(int port)
{
	/* Read direction, clock is low */
	outl(0, PIR(port));
	udelay(1);
	/* Read direction, clock is high */
	outl(1, PIR(port));
	udelay(1);
	/* Read direction, clock is low */
	outl(0, PIR(port));
	udelay(1);
}

static void sh_eth_mii_ind_bus_release(int port)
{
	/* Read direction, clock is low */
	outl(0, PIR(port));
	udelay(1);
}

static void sh_eth_mii_read_phy_bits(int port, u32 *val, int len)
{
	int i;
	u32 pir;

	*val = 0;
	for (i = len - 1; i >= 0; i--) {
		/* Read direction, clock is high */
		outl(1, PIR(port));
		udelay(1);
		/* Read bit */
		pir = inl(PIR(port));
		*val |= (pir & 8) ? 1 << i : 0;
		/* Read direction, clock is low */
		outl(0, PIR(port));
		udelay(1);
	}
}

#define PHY_INIT	0xFFFFFFFF
#define PHY_READ	0x02
#define PHY_WRITE	0x01
/*
 * To read a phy register, mii managements frames are sent to the phy.
 * The frames look like this:
 * pre (32 bits):	0xffff ffff
 * st (2 bits):		01
 * op (2bits):		10: read 01: write
 * phyad (5 bits):	xxxxx
 * regad (5 bits):	xxxxx
 * ta (Bus release):
 * data (16 bits):	read data
 */
static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg)
{
	u32 val;

	/* Sent mii management frame */
	/* pre */
	sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
	/* st (start of frame) */
	sh_eth_mii_write_phy_bits(port, 0x1, 2);
	/* op (code) */
	sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
	/* phy address */
	sh_eth_mii_write_phy_bits(port, phy_addr, 5);
	/* Register to read */
	sh_eth_mii_write_phy_bits(port, reg, 5);

	/* Bus release */
	sh_eth_mii_bus_release(port);

	/* Read register */
	sh_eth_mii_read_phy_bits(port, &val, 16);

	return val;
}

/*
 * To write a phy register, mii managements frames are sent to the phy.
 * The frames look like this:
 * pre (32 bits):	0xffff ffff
 * st (2 bits):		01
 * op (2bits):		10: read 01: write
 * phyad (5 bits):	xxxxx
 * regad (5 bits):	xxxxx
 * ta (2 bits):		10
 * data (16 bits):	write data
 * idle (Independent bus release)
 */
static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val)
{
	/* Sent mii management frame */
	/* pre */
	sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
	/* st (start of frame) */
	sh_eth_mii_write_phy_bits(port, 0x1, 2);
	/* op (code) */
	sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2);
	/* phy address */
	sh_eth_mii_write_phy_bits(port, phy_addr, 5);
	/* Register to read */
	sh_eth_mii_write_phy_bits(port, reg, 5);
	/* ta */
	sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
	/* Write register data */
	sh_eth_mii_write_phy_bits(port, val, 16);

	/* Independent bus release */
	sh_eth_mii_ind_bus_release(port);
}

int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
{
	struct sh_eth_dev *eth = dev->priv;
	int port = eth->port, ret = 0, timeout;
	struct sh_eth_info *port_info = &eth->port_info[port];

	if (!packet || len > 0xffff) {
		printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
		ret = -EINVAL;
		goto err;
	}

	/* packet must be a 4 byte boundary */
	if ((int)packet & (4 - 1)) {
		printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
		ret = -EFAULT;
		goto err;
	}

	/* Update tx descriptor */
	port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
	port_info->tx_desc_cur->td1 = len << 16;
	/* Must preserve the end of descriptor list indication */
	if (port_info->tx_desc_cur->td0 & TD_TDLE)
		port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
	else
		port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;

	/* Restart the transmitter if disabled */
	if (!(inl(EDTRR(port)) & EDTRR_TRNS))
		outl(EDTRR_TRNS, EDTRR(port));

	/* Wait until packet is transmitted */
	timeout = 1000;
	while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
		udelay(100);

	if (timeout < 0) {
		printf(SHETHER_NAME ": transmit timeout\n");
		ret = -ETIMEDOUT;
		goto err;
	}

	port_info->tx_desc_cur++;
	if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
		port_info->tx_desc_cur = port_info->tx_desc_base;

	return ret;
err:
	return ret;
}

int sh_eth_recv(struct eth_device *dev)
{
	struct sh_eth_dev *eth = dev->priv;
	int port = eth->port, len = 0;
	struct sh_eth_info *port_info = &eth->port_info[port];
	volatile u8 *packet;

	/* Check if the rx descriptor is ready */
	if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
		/* Check for errors */
		if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
			len = port_info->rx_desc_cur->rd1 & 0xffff;
			packet = (volatile u8 *)
			    ADDR_TO_P2(port_info->rx_desc_cur->rd2);
			NetReceive(packet, len);
		}

		/* Make current descriptor available again */
		if (port_info->rx_desc_cur->rd0 & RD_RDLE)
			port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
		else
			port_info->rx_desc_cur->rd0 = RD_RACT;

		/* Point to the next descriptor */
		port_info->rx_desc_cur++;
		if (port_info->rx_desc_cur >=
		    port_info->rx_desc_base + NUM_RX_DESC)
			port_info->rx_desc_cur = port_info->rx_desc_base;
	}

	/* Restart the receiver if disabled */
	if (!(inl(EDRRR(port)) & EDRRR_R))
		outl(EDRRR_R, EDRRR(port));

	return len;
}

#define EDMR_INIT_CNT 1000
static int sh_eth_reset(struct sh_eth_dev *eth)
{
	int port = eth->port;
	int ret = 0, i;

	/* Start e-dmac transmitter and receiver */
	outl(EDSR_ENALL, EDSR(port));

	/* Perform a software reset and wait for it to complete */
	outl(EDMR_SRST, EDMR(port));
	for (i = 0; i < EDMR_INIT_CNT; i++) {
		if (!(inl(EDMR(port)) & EDMR_SRST))
			break;
		udelay(1000);
	}

	if (i == EDMR_INIT_CNT) {
		printf(SHETHER_NAME  ": Software reset timeout\n");
		ret = -EIO;
	}

	return ret;
}

static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
{
	int port = eth->port, i, ret = 0;
	u32 tmp_addr;
	struct sh_eth_info *port_info = &eth->port_info[port];
	struct tx_desc_s *cur_tx_desc;

	/*
	 * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
	 */
	port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
						 sizeof(struct tx_desc_s) +
						 TX_DESC_SIZE - 1);
	if (!port_info->tx_desc_malloc) {
		printf(SHETHER_NAME ": malloc failed\n");
		ret = -ENOMEM;
		goto err;
	}

	tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
			  ~(TX_DESC_SIZE - 1));
	/* Make sure we use a P2 address (non-cacheable) */
	port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
	port_info->tx_desc_cur = port_info->tx_desc_base;

	/* Initialize all descriptors */
	for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
	     cur_tx_desc++, i++) {
		cur_tx_desc->td0 = 0x00;
		cur_tx_desc->td1 = 0x00;
		cur_tx_desc->td2 = 0x00;
	}

	/* Mark the end of the descriptors */
	cur_tx_desc--;
	cur_tx_desc->td0 |= TD_TDLE;

	/* Point the controller to the tx descriptor list. Must use physical
	   addresses */
	outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
	outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
	outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
	outl(0x01, TDFFR(port));/* Last discriptor bit */

err:
	return ret;
}

static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
{
	int port = eth->port, i , ret = 0;
	struct sh_eth_info *port_info = &eth->port_info[port];
	struct rx_desc_s *cur_rx_desc;
	u32 tmp_addr;
	u8 *rx_buf;

	/*
	 * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
	 */
	port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
						 sizeof(struct rx_desc_s) +
						 RX_DESC_SIZE - 1);
	if (!port_info->rx_desc_malloc) {
		printf(SHETHER_NAME ": malloc failed\n");
		ret = -ENOMEM;
		goto err;
	}

	tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
			  ~(RX_DESC_SIZE - 1));
	/* Make sure we use a P2 address (non-cacheable) */
	port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);

	port_info->rx_desc_cur = port_info->rx_desc_base;

	/*
	 * Allocate rx data buffers. They must be 32 bytes aligned  and in
	 * P2 area
	 */
	port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31);
	if (!port_info->rx_buf_malloc) {
		printf(SHETHER_NAME ": malloc failed\n");
		ret = -ENOMEM;
		goto err_buf_malloc;
	}

	tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) &
			  ~(32 - 1));
	port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);

	/* Initialize all descriptors */
	for (cur_rx_desc = port_info->rx_desc_base,
	     rx_buf = port_info->rx_buf_base, i = 0;
	     i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
		cur_rx_desc->rd0 = RD_RACT;
		cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
		cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
	}

	/* Mark the end of the descriptors */
	cur_rx_desc--;
	cur_rx_desc->rd0 |= RD_RDLE;

	/* Point the controller to the rx descriptor list */
	outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
	outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
	outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
	outl(RDFFR_RDLF, RDFFR(port));

	return ret;

err_buf_malloc:
	free(port_info->rx_desc_malloc);
	port_info->rx_desc_malloc = NULL;

err:
	return ret;
}

static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
{
	int port = eth->port;
	struct sh_eth_info *port_info = &eth->port_info[port];

	if (port_info->tx_desc_malloc) {
		free(port_info->tx_desc_malloc);
		port_info->tx_desc_malloc = NULL;
	}
}

static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
{
	int port = eth->port;
	struct sh_eth_info *port_info = &eth->port_info[port];

	if (port_info->rx_desc_malloc) {
		free(port_info->rx_desc_malloc);
		port_info->rx_desc_malloc = NULL;
	}

	if (port_info->rx_buf_malloc) {
		free(port_info->rx_buf_malloc);
		port_info->rx_buf_malloc = NULL;
	}
}

static int sh_eth_desc_init(struct sh_eth_dev *eth)
{
	int ret = 0;

	ret = sh_eth_tx_desc_init(eth);
	if (ret)
		goto err_tx_init;

	ret = sh_eth_rx_desc_init(eth);
	if (ret)
		goto err_rx_init;

	return ret;
err_rx_init:
	sh_eth_tx_desc_free(eth);

err_tx_init:
	return ret;
}

static int sh_eth_phy_config(struct sh_eth_dev *eth)
{
	int port = eth->port, timeout, ret = 0;
	struct sh_eth_info *port_info = &eth->port_info[port];
	u32 val;

	/* Reset phy */
	sh_eth_mii_write_phy_reg
		(port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET);
	timeout = 10;
	while (timeout--) {
		val = sh_eth_mii_read_phy_reg(port,
				port_info->phy_addr, PHY_CTRL);
		if (!(val & PHY_C_RESET))
			break;
		udelay(SH_ETH_PHY_DELAY);
	}

	if (timeout < 0) {
		printf(SHETHER_NAME ": phy reset timeout\n");
		ret = -EIO;
		goto err_tout;
	}

	/* Advertise 100/10 baseT full/half duplex */
	sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA,
		(PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT));
	/* Autonegotiation, normal operation, full duplex, enable tx */
	sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL,
		(PHY_C_ANEGEN|PHY_C_RANEG));
	/* Wait for autonegotiation to complete */
	timeout = 100;
	while (timeout--) {
		val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);
		if (val & PHY_S_ANEGC)
			break;

		udelay(SH_ETH_PHY_DELAY);
	}

	if (timeout < 0) {
		printf(SHETHER_NAME ": phy auto-negotiation failed\n");
		ret = -ETIMEDOUT;
		goto err_tout;
	}

	return ret;

err_tout:
	return ret;
}

static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
{
	int port = eth->port, ret = 0;
	u32 val,  phy_status;
	struct sh_eth_info *port_info = &eth->port_info[port];

	/* Configure e-dmac registers */
	outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port));
	outl(0, EESIPR(port));
	outl(0, TRSCER(port));
	outl(0, TFTR(port));
	outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
	outl(RMCR_RST, RMCR(port));
	outl(0, RPADIR(port));
	outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));

	/* Configure e-mac registers */
	outl(0, ECSIPR(port));

	/* Set Mac address */
	val = bd->bi_enetaddr[0] << 24 | bd->bi_enetaddr[1] << 16 |
	    bd->bi_enetaddr[2] << 8 | bd->bi_enetaddr[3];
	outl(val, MAHR(port));

	val = bd->bi_enetaddr[4] << 8 | bd->bi_enetaddr[5];
	outl(val, MALR(port));

	outl(RFLR_RFL_MIN, RFLR(port));
	outl(0, PIPR(port));
	outl(APR_AP, APR(port));
	outl(MPR_MP, MPR(port));
	outl(TPAUSER_TPAUSE, TPAUSER(port));

	/* Configure phy */
	ret = sh_eth_phy_config(eth);
	if (ret) {
		printf(SHETHER_NAME ":i phy config timeout\n");
		goto err_phy_cfg;
	}
	/* Read phy status to finish configuring the e-mac */
	phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);

	/* Set the transfer speed */
	if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) {
		printf(SHETHER_NAME ": 100Base/");
		outl(GECMR_100B, GECMR(port));
	} else {
		printf(SHETHER_NAME ": 10Base/");
		outl(GECMR_10B, GECMR(port));
	}

	/* Check if full duplex mode is supported by the phy */
	if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) {
		printf("Full\n");
		outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
	} else {
		printf("Half\n");
		outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE),  ECMR(port));
	}

	return ret;

err_phy_cfg:
	return ret;
}

static void sh_eth_start(struct sh_eth_dev *eth)
{
	/*
	 * Enable the e-dmac receiver only. The transmitter will be enabled when
	 * we have something to transmit
	 */
	outl(EDRRR_R, EDRRR(eth->port));
}

static void sh_eth_stop(struct sh_eth_dev *eth)
{
	outl(~EDRRR_R, EDRRR(eth->port));
}

static int sh_eth_get_mac(bd_t *bd)
{
	char *s, *e;

	s = getenv("ethaddr");
	if (s != NULL) {
		int i;
		for (i = 0; i < 6; ++i) {
			bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
			if (s)
				s = (*e) ? e + 1 : e;
		}
	} else {
		puts("Please set MAC address\n");
	}
	return 0;
}

int sh_eth_init(struct eth_device *dev, bd_t *bd)
{
	int ret = 0;
	struct sh_eth_dev *eth = dev->priv;

	ret = sh_eth_reset(eth);
	if (ret)
		goto err;

	ret = sh_eth_desc_init(eth);
	if (ret)
		goto err;

	ret = sh_eth_config(eth, bd);
	if (ret)
		goto err_config;

	sh_eth_start(eth);

	return ret;

err_config:
	sh_eth_tx_desc_free(eth);
	sh_eth_rx_desc_free(eth);

err:
	return ret;
}

void sh_eth_halt(struct eth_device *dev)
{
	struct sh_eth_dev *eth = dev->priv;

	sh_eth_reset(eth);
	sh_eth_stop(eth);
}

int sh_eth_initialize(bd_t *bd)
{
    int ret = 0;
	struct sh_eth_dev *eth = NULL;
    struct eth_device *dev = NULL;

    eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
	if (!eth) {
		printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
		ret = -ENOMEM;
		goto err;
	}

    dev = (struct eth_device *)malloc(sizeof(struct eth_device));
	if (!dev) {
		printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
		ret = -ENOMEM;
		goto err;
	}
    memset(dev, 0, sizeof(struct eth_device));
    memset(eth, 0, sizeof(struct sh_eth_dev));

	eth->port = CONFIG_SH_ETHER_USE_PORT;
	eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;

    dev->priv = (void *)eth;
    dev->iobase = 0;
    dev->init = sh_eth_init;
    dev->halt = sh_eth_halt;
    dev->send = sh_eth_send;
    dev->recv = sh_eth_recv;
    eth->port_info[eth->port].dev = dev;

	sprintf(dev->name, SHETHER_NAME);

    /* Register Device to EtherNet subsystem  */
    eth_register(dev);

	sh_eth_get_mac(bd);

	return ret;

err:
	if (dev)
		free(dev);

	if (eth)
		free(eth);

	printf(SHETHER_NAME ": Failed\n");
	return ret;
}
Commit	Line	Data
9751ee09 NI	1	/*
	2	* sh_eth.c - Driver for Renesas SH7763's ethernet controler.
	3	*
	4	* Copyright (C) 2008 Renesas Solutions Corp.
	5	* Copyright (c) 2008 Nobuhiro Iwamatsu
	6	* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	21	*/
	22
	23	#include <config.h>
	24	#include <common.h>
	25	#include <malloc.h>
	26	#include <net.h>
bd3980cc	27	#include <netdev.h>
9751ee09 NI	28	#include <asm/errno.h>
	29	#include <asm/io.h>
	30
	31	#include "sh_eth.h"
	32
	33	#ifndef CONFIG_SH_ETHER_USE_PORT
	34	# error "Please define CONFIG_SH_ETHER_USE_PORT"
	35	#endif
	36	#ifndef CONFIG_SH_ETHER_PHY_ADDR
	37	# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
	38	#endif
	39
bd3980cc	40	#define SH_ETH_PHY_DELAY 50000
9751ee09 NI	41
	42	/*
	43	* Bits are written to the PHY serially using the
	44	* PIR register, just like a bit banger.
	45	*/
	46	static void sh_eth_mii_write_phy_bits(int port, u32 val, int len)
	47	{
	48	int i;
	49	u32 pir;
	50
	51	/* Bit positions is 1 less than the number of bits */
	52	for (i = len - 1; i >= 0; i--) {
	53	/* Write direction, bit to write, clock is low */
	54	pir = 2 \| ((val & 1 << i) ? 1 << 2 : 0);
	55	outl(pir, PIR(port));
	56	udelay(1);
	57	/* Write direction, bit to write, clock is high */
	58	pir = 3 \| ((val & 1 << i) ? 1 << 2 : 0);
	59	outl(pir, PIR(port));
	60	udelay(1);
	61	/* Write direction, bit to write, clock is low */
	62	pir = 2 \| ((val & 1 << i) ? 1 << 2 : 0);
	63	outl(pir, PIR(port));
	64	udelay(1);
	65	}
	66	}
	67
	68	static void sh_eth_mii_bus_release(int port)
	69	{
	70	/* Read direction, clock is low */
	71	outl(0, PIR(port));
	72	udelay(1);
	73	/* Read direction, clock is high */
	74	outl(1, PIR(port));
	75	udelay(1);
	76	/* Read direction, clock is low */
	77	outl(0, PIR(port));
	78	udelay(1);
	79	}
	80
	81	static void sh_eth_mii_ind_bus_release(int port)
	82	{
	83	/* Read direction, clock is low */
	84	outl(0, PIR(port));
	85	udelay(1);
	86	}
	87
bd3980cc	88	static void sh_eth_mii_read_phy_bits(int port, u32 *val, int len)
9751ee09 NI	89	{
	90	int i;
	91	u32 pir;
	92
	93	*val = 0;
	94	for (i = len - 1; i >= 0; i--) {
	95	/* Read direction, clock is high */
	96	outl(1, PIR(port));
	97	udelay(1);
	98	/* Read bit */
	99	pir = inl(PIR(port));
	100	*val \|= (pir & 8) ? 1 << i : 0;
	101	/* Read direction, clock is low */
	102	outl(0, PIR(port));
	103	udelay(1);
	104	}
9751ee09 NI	105	}
	106
	107	#define PHY_INIT 0xFFFFFFFF
	108	#define PHY_READ 0x02
	109	#define PHY_WRITE 0x01
	110	/*
	111	* To read a phy register, mii managements frames are sent to the phy.
	112	* The frames look like this:
	113	* pre (32 bits): 0xffff ffff
	114	* st (2 bits): 01
	115	* op (2bits): 10: read 01: write
	116	* phyad (5 bits): xxxxx
	117	* regad (5 bits): xxxxx
	118	* ta (Bus release):
	119	* data (16 bits): read data
	120	*/
	121	static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg)
	122	{
	123	u32 val;
	124
	125	/* Sent mii management frame */
	126	/* pre */
	127	sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
	128	/* st (start of frame) */
	129	sh_eth_mii_write_phy_bits(port, 0x1, 2);
	130	/* op (code) */
	131	sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
	132	/* phy address */
	133	sh_eth_mii_write_phy_bits(port, phy_addr, 5);
	134	/* Register to read */
	135	sh_eth_mii_write_phy_bits(port, reg, 5);
	136
	137	/* Bus release */
	138	sh_eth_mii_bus_release(port);
	139
	140	/* Read register */
	141	sh_eth_mii_read_phy_bits(port, &val, 16);
	142
	143	return val;
	144	}
	145
	146	/*
	147	* To write a phy register, mii managements frames are sent to the phy.
	148	* The frames look like this:
	149	* pre (32 bits): 0xffff ffff
	150	* st (2 bits): 01
	151	* op (2bits): 10: read 01: write
	152	* phyad (5 bits): xxxxx
	153	* regad (5 bits): xxxxx
	154	* ta (2 bits): 10
	155	* data (16 bits): write data
	156	* idle (Independent bus release)
	157	*/
	158	static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val)
	159	{
	160	/* Sent mii management frame */
	161	/* pre */
	162	sh_eth_mii_write_phy_bits(port, PHY_INIT, 32);
	163	/* st (start of frame) */
	164	sh_eth_mii_write_phy_bits(port, 0x1, 2);
	165	/* op (code) */
	166	sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2);
	167	/* phy address */
	168	sh_eth_mii_write_phy_bits(port, phy_addr, 5);
169	/* Register to read */
170	sh_eth_mii_write_phy_bits(port, reg, 5);
171	/* ta */
172	sh_eth_mii_write_phy_bits(port, PHY_READ, 2);
173	/* Write register data */
174	sh_eth_mii_write_phy_bits(port, val, 16);
175
176	/* Independent bus release */
177	sh_eth_mii_ind_bus_release(port);
178	}
179
bd3980cc	180	int sh_eth_send(struct eth_device dev, volatile void packet, int len)
9751ee09	181	{
bd3980cc NI	182	struct sh_eth_dev *eth = dev->priv;
	183	int port = eth->port, ret = 0, timeout;
	184	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09 NI	185
9751ee09 NI	186	if (!packet \|\| len > 0xffff) {
bd3980cc NI	187	printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
	188	ret = -EINVAL;
	189	goto err;
9751ee09 NI	190	}
	191
	192	/* packet must be a 4 byte boundary */
	193	if ((int)packet & (4 - 1)) {
bd3980cc NI	194	printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
	195	ret = -EFAULT;
	196	goto err;
9751ee09 NI	197	}
	198
	199	/* Update tx descriptor */
	200	port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
	201	port_info->tx_desc_cur->td1 = len << 16;
	202	/* Must preserve the end of descriptor list indication */
	203	if (port_info->tx_desc_cur->td0 & TD_TDLE)
	204	port_info->tx_desc_cur->td0 = TD_TACT \| TD_TFP \| TD_TDLE;
	205	else
	206	port_info->tx_desc_cur->td0 = TD_TACT \| TD_TFP;
	207
	208	/* Restart the transmitter if disabled */
	209	if (!(inl(EDTRR(port)) & EDTRR_TRNS))
	210	outl(EDTRR_TRNS, EDTRR(port));
	211
	212	/* Wait until packet is transmitted */
	213	timeout = 1000;
	214	while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
	215	udelay(100);
	216
	217	if (timeout < 0) {
bd3980cc NI	218	printf(SHETHER_NAME ": transmit timeout\n");
bd3980cc NI	219	ret = -ETIMEDOUT;
9751ee09 NI	220	goto err;
	221	}
	222
9751ee09 NI	223	port_info->tx_desc_cur++;
	224	if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
	225	port_info->tx_desc_cur = port_info->tx_desc_base;
	226
bd3980cc NI	227	return ret;
	228	err:
	229	return ret;
9751ee09 NI	230	}
9751ee09 NI	231
bd3980cc	232	int sh_eth_recv(struct eth_device *dev)
9751ee09	233	{
bd3980cc NI	234	struct sh_eth_dev *eth = dev->priv;
	235	int port = eth->port, len = 0;
	236	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09 NI	237	volatile u8 *packet;
	238
	239	/* Check if the rx descriptor is ready */
	240	if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
	241	/* Check for errors */
	242	if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
	243	len = port_info->rx_desc_cur->rd1 & 0xffff;
	244	packet = (volatile u8 *)
	245	ADDR_TO_P2(port_info->rx_desc_cur->rd2);
	246	NetReceive(packet, len);
	247	}
	248
	249	/* Make current descriptor available again */
	250	if (port_info->rx_desc_cur->rd0 & RD_RDLE)
	251	port_info->rx_desc_cur->rd0 = RD_RACT \| RD_RDLE;
	252	else
	253	port_info->rx_desc_cur->rd0 = RD_RACT;
	254
	255	/* Point to the next descriptor */
	256	port_info->rx_desc_cur++;
	257	if (port_info->rx_desc_cur >=
	258	port_info->rx_desc_base + NUM_RX_DESC)
	259	port_info->rx_desc_cur = port_info->rx_desc_base;
	260	}
	261
	262	/* Restart the receiver if disabled */
	263	if (!(inl(EDRRR(port)) & EDRRR_R))
	264	outl(EDRRR_R, EDRRR(port));
	265
	266	return len;
	267	}
	268
	269	#define EDMR_INIT_CNT 1000
bd3980cc	270	static int sh_eth_reset(struct sh_eth_dev *eth)
9751ee09	271	{
bd3980cc NI	272	int port = eth->port;
bd3980cc NI	273	int ret = 0, i;
9751ee09 NI	274
	275	/* Start e-dmac transmitter and receiver */
	276	outl(EDSR_ENALL, EDSR(port));
	277
	278	/* Perform a software reset and wait for it to complete */
	279	outl(EDMR_SRST, EDMR(port));
	280	for (i = 0; i < EDMR_INIT_CNT; i++) {
	281	if (!(inl(EDMR(port)) & EDMR_SRST))
	282	break;
	283	udelay(1000);
	284	}
	285
	286	if (i == EDMR_INIT_CNT) {
bd3980cc NI	287	printf(SHETHER_NAME ": Software reset timeout\n");
bd3980cc NI	288	ret = -EIO;
9751ee09	289	}
bd3980cc NI	290
bd3980cc NI	291	return ret;
9751ee09 NI	292	}
9751ee09 NI	293
bd3980cc	294	static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
9751ee09	295	{
bd3980cc	296	int port = eth->port, i, ret = 0;
9751ee09	297	u32 tmp_addr;
bd3980cc	298	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09	299	struct tx_desc_s *cur_tx_desc;
9751ee09	300
bd3980cc NI	301	/*
	302	* Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
	303	*/
	304	port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
9751ee09	305	sizeof(struct tx_desc_s) +
bd3980cc NI	306	TX_DESC_SIZE - 1);
	307	if (!port_info->tx_desc_malloc) {
	308	printf(SHETHER_NAME ": malloc failed\n");
	309	ret = -ENOMEM;
	310	goto err;
9751ee09	311	}
bd3980cc	312
9751ee09 NI	313	tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
	314	~(TX_DESC_SIZE - 1));
	315	/* Make sure we use a P2 address (non-cacheable) */
	316	port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
9751ee09 NI	317	port_info->tx_desc_cur = port_info->tx_desc_base;
	318
	319	/* Initialize all descriptors */
	320	for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
	321	cur_tx_desc++, i++) {
	322	cur_tx_desc->td0 = 0x00;
	323	cur_tx_desc->td1 = 0x00;
	324	cur_tx_desc->td2 = 0x00;
	325	}
	326
	327	/* Mark the end of the descriptors */
	328	cur_tx_desc--;
	329	cur_tx_desc->td0 \|= TD_TDLE;
	330
	331	/* Point the controller to the tx descriptor list. Must use physical
	332	addresses */
	333	outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
	334	outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
	335	outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
	336	outl(0x01, TDFFR(port));/* Last discriptor bit */
	337
bd3980cc NI	338	err:
bd3980cc NI	339	return ret;
9751ee09 NI	340	}
9751ee09 NI	341
bd3980cc	342	static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
9751ee09	343	{
bd3980cc NI	344	int port = eth->port, i , ret = 0;
bd3980cc NI	345	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09	346	struct rx_desc_s *cur_rx_desc;
bd3980cc	347	u32 tmp_addr;
9751ee09	348	u8 *rx_buf;
9751ee09	349
bd3980cc NI	350	/*
	351	* Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
	352	*/
	353	port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
9751ee09	354	sizeof(struct rx_desc_s) +
bd3980cc NI	355	RX_DESC_SIZE - 1);
	356	if (!port_info->rx_desc_malloc) {
	357	printf(SHETHER_NAME ": malloc failed\n");
	358	ret = -ENOMEM;
	359	goto err;
9751ee09	360	}
bd3980cc	361
9751ee09 NI	362	tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
	363	~(RX_DESC_SIZE - 1));
	364	/* Make sure we use a P2 address (non-cacheable) */
	365	port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
	366
	367	port_info->rx_desc_cur = port_info->rx_desc_base;
	368
bd3980cc NI	369	/*
	370	* Allocate rx data buffers. They must be 32 bytes aligned and in
	371	* P2 area
	372	*/
	373	port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31);
	374	if (!port_info->rx_buf_malloc) {
	375	printf(SHETHER_NAME ": malloc failed\n");
	376	ret = -ENOMEM;
	377	goto err_buf_malloc;
9751ee09	378	}
bd3980cc	379
9751ee09 NI	380	tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) &
	381	~(32 - 1));
	382	port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
	383
	384	/* Initialize all descriptors */
	385	for (cur_rx_desc = port_info->rx_desc_base,
	386	rx_buf = port_info->rx_buf_base, i = 0;
	387	i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
	388	cur_rx_desc->rd0 = RD_RACT;
	389	cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
	390	cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
	391	}
	392
	393	/* Mark the end of the descriptors */
	394	cur_rx_desc--;
	395	cur_rx_desc->rd0 \|= RD_RDLE;
	396
	397	/* Point the controller to the rx descriptor list */
	398	outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
	399	outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
	400	outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
	401	outl(RDFFR_RDLF, RDFFR(port));
	402
bd3980cc NI	403	return ret;
	404
	405	err_buf_malloc:
	406	free(port_info->rx_desc_malloc);
	407	port_info->rx_desc_malloc = NULL;
	408
	409	err:
	410	return ret;
9751ee09 NI	411	}
9751ee09 NI	412
bd3980cc	413	static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
9751ee09	414	{
bd3980cc NI	415	int port = eth->port;
bd3980cc NI	416	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09 NI	417
	418	if (port_info->tx_desc_malloc) {
	419	free(port_info->tx_desc_malloc);
	420	port_info->tx_desc_malloc = NULL;
	421	}
bd3980cc NI	422	}
	423
	424	static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
	425	{
	426	int port = eth->port;
	427	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09 NI	428
	429	if (port_info->rx_desc_malloc) {
	430	free(port_info->rx_desc_malloc);
	431	port_info->rx_desc_malloc = NULL;
	432	}
	433
	434	if (port_info->rx_buf_malloc) {
	435	free(port_info->rx_buf_malloc);
	436	port_info->rx_buf_malloc = NULL;
	437	}
	438	}
	439
bd3980cc	440	static int sh_eth_desc_init(struct sh_eth_dev *eth)
9751ee09	441	{
bd3980cc	442	int ret = 0;
9751ee09	443
bd3980cc NI	444	ret = sh_eth_tx_desc_init(eth);
	445	if (ret)
	446	goto err_tx_init;
9751ee09	447
bd3980cc NI	448	ret = sh_eth_rx_desc_init(eth);
	449	if (ret)
	450	goto err_rx_init;
	451
	452	return ret;
	453	err_rx_init:
	454	sh_eth_tx_desc_free(eth);
	455
	456	err_tx_init:
	457	return ret;
9751ee09 NI	458	}
9751ee09 NI	459
bd3980cc	460	static int sh_eth_phy_config(struct sh_eth_dev *eth)
9751ee09	461	{
bd3980cc NI	462	int port = eth->port, timeout, ret = 0;
bd3980cc NI	463	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09	464	u32 val;
bd3980cc	465
9751ee09	466	/* Reset phy */
bd3980cc NI	467	sh_eth_mii_write_phy_reg
bd3980cc NI	468	(port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET);
9751ee09 NI	469	timeout = 10;
9751ee09 NI	470	while (timeout--) {
bd3980cc NI	471	val = sh_eth_mii_read_phy_reg(port,
bd3980cc NI	472	port_info->phy_addr, PHY_CTRL);
9751ee09 NI	473	if (!(val & PHY_C_RESET))
9751ee09 NI	474	break;
bd3980cc	475	udelay(SH_ETH_PHY_DELAY);
9751ee09	476	}
bd3980cc	477
9751ee09	478	if (timeout < 0) {
bd3980cc NI	479	printf(SHETHER_NAME ": phy reset timeout\n");
	480	ret = -EIO;
	481	goto err_tout;
9751ee09 NI	482	}
	483
	484	/* Advertise 100/10 baseT full/half duplex */
	485	sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA,
	486	(PHY_A_FDX\|PHY_A_HDX\|PHY_A_10FDX\|PHY_A_10HDX\|PHY_A_EXT));
	487	/* Autonegotiation, normal operation, full duplex, enable tx */
	488	sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL,
	489	(PHY_C_ANEGEN\|PHY_C_RANEG));
	490	/* Wait for autonegotiation to complete */
	491	timeout = 100;
	492	while (timeout--) {
	493	val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);
	494	if (val & PHY_S_ANEGC)
	495	break;
bd3980cc NI	496
bd3980cc NI	497	udelay(SH_ETH_PHY_DELAY);
9751ee09	498	}
bd3980cc	499
9751ee09	500	if (timeout < 0) {
bd3980cc NI	501	printf(SHETHER_NAME ": phy auto-negotiation failed\n");
	502	ret = -ETIMEDOUT;
	503	goto err_tout;
9751ee09 NI	504	}
9751ee09 NI	505
bd3980cc NI	506	return ret;
	507
	508	err_tout:
	509	return ret;
9751ee09 NI	510	}
9751ee09 NI	511
bd3980cc	512	static int sh_eth_config(struct sh_eth_dev eth, bd_t bd)
9751ee09	513	{
bd3980cc NI	514	int port = eth->port, ret = 0;
	515	u32 val, phy_status;
	516	struct sh_eth_info *port_info = &eth->port_info[port];
9751ee09 NI	517
	518	/* Configure e-dmac registers */
	519	outl((inl(EDMR(port)) & ~EMDR_DESC_R) \| EDMR_EL, EDMR(port));
	520	outl(0, EESIPR(port));
	521	outl(0, TRSCER(port));
	522	outl(0, TFTR(port));
	523	outl((FIFO_SIZE_T \| FIFO_SIZE_R), FDR(port));
	524	outl(RMCR_RST, RMCR(port));
	525	outl(0, RPADIR(port));
	526	outl((FIFO_F_D_RFF \| FIFO_F_D_RFD), FCFTR(port));
	527
	528	/* Configure e-mac registers */
	529	outl(0, ECSIPR(port));
	530
	531	/* Set Mac address */
	532	val = bd->bi_enetaddr[0] << 24 \| bd->bi_enetaddr[1] << 16 \|
	533	bd->bi_enetaddr[2] << 8 \| bd->bi_enetaddr[3];
	534	outl(val, MAHR(port));
	535
	536	val = bd->bi_enetaddr[4] << 8 \| bd->bi_enetaddr[5];
	537	outl(val, MALR(port));
	538
	539	outl(RFLR_RFL_MIN, RFLR(port));
	540	outl(0, PIPR(port));
	541	outl(APR_AP, APR(port));
	542	outl(MPR_MP, MPR(port));
	543	outl(TPAUSER_TPAUSE, TPAUSER(port));
	544
	545	/* Configure phy */
bd3980cc NI	546	ret = sh_eth_phy_config(eth);
	547	if (ret) {
	548	printf(SHETHER_NAME ":i phy config timeout\n");
	549	goto err_phy_cfg;
	550	}
9751ee09	551	/* Read phy status to finish configuring the e-mac */
bd3980cc	552	phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);
9751ee09 NI	553
	554	/* Set the transfer speed */
	555	if (phy_status & (PHY_S_100X_F\|PHY_S_100X_H)) {
bd3980cc	556	printf(SHETHER_NAME ": 100Base/");
9751ee09 NI	557	outl(GECMR_100B, GECMR(port));
9751ee09 NI	558	} else {
bd3980cc	559	printf(SHETHER_NAME ": 10Base/");
9751ee09 NI	560	outl(GECMR_10B, GECMR(port));
	561	}
	562
	563	/* Check if full duplex mode is supported by the phy */
	564	if (phy_status & (PHY_S_100X_F\|PHY_S_10T_F)) {
	565	printf("Full\n");
	566	outl((ECMR_CHG_DM\|ECMR_RE\|ECMR_TE\|ECMR_DM), ECMR(port));
	567	} else {
	568	printf("Half\n");
	569	outl((ECMR_CHG_DM\|ECMR_RE\|ECMR_TE), ECMR(port));
	570	}
bd3980cc NI	571
	572	return ret;
	573
	574	err_phy_cfg:
	575	return ret;
9751ee09 NI	576	}
9751ee09 NI	577
bd3980cc	578	static void sh_eth_start(struct sh_eth_dev *eth)
9751ee09 NI	579	{
	580	/*
	581	* Enable the e-dmac receiver only. The transmitter will be enabled when
	582	* we have something to transmit
	583	*/
bd3980cc NI	584	outl(EDRRR_R, EDRRR(eth->port));
bd3980cc NI	585	}
9751ee09	586
bd3980cc NI	587	static void sh_eth_stop(struct sh_eth_dev *eth)
	588	{
	589	outl(~EDRRR_R, EDRRR(eth->port));
9751ee09 NI	590	}
	591
	592	static int sh_eth_get_mac(bd_t *bd)
	593	{
	594	char s, e;
9751ee09 NI	595
	596	s = getenv("ethaddr");
	597	if (s != NULL) {
bd3980cc	598	int i;
9751ee09 NI	599	for (i = 0; i < 6; ++i) {
	600	bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
	601	if (s)
	602	s = (*e) ? e + 1 : e;
	603	}
	604	} else {
	605	puts("Please set MAC address\n");
	606	}
	607	return 0;
	608	}
	609
bd3980cc	610	int sh_eth_init(struct eth_device dev, bd_t bd)
9751ee09	611	{
bd3980cc NI	612	int ret = 0;
bd3980cc NI	613	struct sh_eth_dev *eth = dev->priv;
9751ee09	614
bd3980cc NI	615	ret = sh_eth_reset(eth);
	616	if (ret)
	617	goto err;
9751ee09	618
bd3980cc NI	619	ret = sh_eth_desc_init(eth);
	620	if (ret)
	621	goto err;
9751ee09	622
bd3980cc NI	623	ret = sh_eth_config(eth, bd);
	624	if (ret)
	625	goto err_config;
	626
	627	sh_eth_start(eth);
	628
	629	return ret;
9751ee09	630
bd3980cc NI	631	err_config:
	632	sh_eth_tx_desc_free(eth);
	633	sh_eth_rx_desc_free(eth);
	634
	635	err:
	636	return ret;
	637	}
	638
	639	void sh_eth_halt(struct eth_device *dev)
	640	{
	641	struct sh_eth_dev *eth = dev->priv;
	642
	643	sh_eth_reset(eth);
	644	sh_eth_stop(eth);
	645	}
	646
	647	int sh_eth_initialize(bd_t *bd)
	648	{
	649	int ret = 0;
	650	struct sh_eth_dev *eth = NULL;
	651	struct eth_device *dev = NULL;
	652
	653	eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
	654	if (!eth) {
	655	printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
	656	ret = -ENOMEM;
9751ee09	657	goto err;
bd3980cc	658	}
9751ee09	659
bd3980cc NI	660	dev = (struct eth_device *)malloc(sizeof(struct eth_device));
	661	if (!dev) {
	662	printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
	663	ret = -ENOMEM;
	664	goto err;
	665	}
	666	memset(dev, 0, sizeof(struct eth_device));
	667	memset(eth, 0, sizeof(struct sh_eth_dev));
9751ee09	668
bd3980cc NI	669	eth->port = CONFIG_SH_ETHER_USE_PORT;
	670	eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
	671
	672	dev->priv = (void *)eth;
	673	dev->iobase = 0;
	674	dev->init = sh_eth_init;
	675	dev->halt = sh_eth_halt;
	676	dev->send = sh_eth_send;
	677	dev->recv = sh_eth_recv;
	678	eth->port_info[eth->port].dev = dev;
	679
	680	sprintf(dev->name, SHETHER_NAME);
	681
	682	/* Register Device to EtherNet subsystem */
	683	eth_register(dev);
	684
	685	sh_eth_get_mac(bd);
	686
	687	return ret;
9751ee09	688
9751ee09	689	err:
bd3980cc NI	690	if (dev)
	691	free(dev);
	692
	693	if (eth)
	694	free(eth);
	695
	696	printf(SHETHER_NAME ": Failed\n");
	697	return ret;
9751ee09	698	}