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Commit | Line | Data |
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9751ee09 | 1 | /* |
1cc0a9f4 | 2 | * sh_eth.c - Driver for Renesas ethernet controller. |
9751ee09 | 3 | * |
3bb4cc31 | 4 | * Copyright (C) 2008, 2011 Renesas Solutions Corp. |
f7ca1f76 | 5 | * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu |
9751ee09 | 6 | * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com> |
f7ca1f76 | 7 | * Copyright (C) 2013, 2014 Renesas Electronics Corporation |
9751ee09 | 8 | * |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
9751ee09 NI |
10 | */ |
11 | ||
12 | #include <config.h> | |
13 | #include <common.h> | |
14 | #include <malloc.h> | |
15 | #include <net.h> | |
bd3980cc | 16 | #include <netdev.h> |
bd1024b0 | 17 | #include <miiphy.h> |
1221ce45 | 18 | #include <linux/errno.h> |
9751ee09 NI |
19 | #include <asm/io.h> |
20 | ||
21 | #include "sh_eth.h" | |
22 | ||
23 | #ifndef CONFIG_SH_ETHER_USE_PORT | |
24 | # error "Please define CONFIG_SH_ETHER_USE_PORT" | |
25 | #endif | |
26 | #ifndef CONFIG_SH_ETHER_PHY_ADDR | |
27 | # error "Please define CONFIG_SH_ETHER_PHY_ADDR" | |
28 | #endif | |
870cc23f | 29 | |
92f07134 NI |
30 | #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF) |
31 | #define flush_cache_wback(addr, len) \ | |
aae5d237 NI |
32 | flush_dcache_range((u32)addr, \ |
33 | (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE))) | |
68260aab YS |
34 | #else |
35 | #define flush_cache_wback(...) | |
36 | #endif | |
9751ee09 | 37 | |
92f07134 NI |
38 | #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) |
39 | #define invalidate_cache(addr, len) \ | |
40 | { \ | |
41 | u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \ | |
42 | u32 start, end; \ | |
43 | \ | |
44 | start = (u32)addr; \ | |
45 | end = start + len; \ | |
46 | start &= ~(line_size - 1); \ | |
47 | end = ((end + line_size - 1) & ~(line_size - 1)); \ | |
48 | \ | |
49 | invalidate_dcache_range(start, end); \ | |
50 | } | |
51 | #else | |
52 | #define invalidate_cache(...) | |
53 | #endif | |
54 | ||
4ba62c72 NI |
55 | #define TIMEOUT_CNT 1000 |
56 | ||
dca221bd | 57 | static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len) |
9751ee09 | 58 | { |
bd3980cc NI |
59 | int port = eth->port, ret = 0, timeout; |
60 | struct sh_eth_info *port_info = ð->port_info[port]; | |
9751ee09 NI |
61 | |
62 | if (!packet || len > 0xffff) { | |
bd3980cc NI |
63 | printf(SHETHER_NAME ": %s: Invalid argument\n", __func__); |
64 | ret = -EINVAL; | |
65 | goto err; | |
9751ee09 NI |
66 | } |
67 | ||
68 | /* packet must be a 4 byte boundary */ | |
ee6ec5d4 | 69 | if ((int)packet & 3) { |
dc14867d | 70 | printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n" |
e2752db0 | 71 | , __func__); |
bd3980cc NI |
72 | ret = -EFAULT; |
73 | goto err; | |
9751ee09 NI |
74 | } |
75 | ||
76 | /* Update tx descriptor */ | |
68260aab | 77 | flush_cache_wback(packet, len); |
9751ee09 NI |
78 | port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); |
79 | port_info->tx_desc_cur->td1 = len << 16; | |
80 | /* Must preserve the end of descriptor list indication */ | |
81 | if (port_info->tx_desc_cur->td0 & TD_TDLE) | |
82 | port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE; | |
83 | else | |
84 | port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP; | |
85 | ||
f7ca1f76 NI |
86 | flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s)); |
87 | ||
9751ee09 | 88 | /* Restart the transmitter if disabled */ |
fbfb5115 NI |
89 | if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS)) |
90 | sh_eth_write(port_info, EDTRR_TRNS, EDTRR); | |
9751ee09 NI |
91 | |
92 | /* Wait until packet is transmitted */ | |
4ba62c72 | 93 | timeout = TIMEOUT_CNT; |
92f07134 NI |
94 | do { |
95 | invalidate_cache(port_info->tx_desc_cur, | |
96 | sizeof(struct tx_desc_s)); | |
9751ee09 | 97 | udelay(100); |
92f07134 | 98 | } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--); |
9751ee09 NI |
99 | |
100 | if (timeout < 0) { | |
bd3980cc NI |
101 | printf(SHETHER_NAME ": transmit timeout\n"); |
102 | ret = -ETIMEDOUT; | |
9751ee09 NI |
103 | goto err; |
104 | } | |
105 | ||
9751ee09 NI |
106 | port_info->tx_desc_cur++; |
107 | if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC) | |
108 | port_info->tx_desc_cur = port_info->tx_desc_base; | |
109 | ||
bd3980cc NI |
110 | err: |
111 | return ret; | |
9751ee09 NI |
112 | } |
113 | ||
dca221bd | 114 | static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len) |
9751ee09 | 115 | { |
bd3980cc | 116 | struct sh_eth_dev *eth = dev->priv; |
dca221bd MV |
117 | |
118 | return sh_eth_send_common(eth, packet, len); | |
119 | } | |
120 | ||
121 | static int sh_eth_recv_common(struct sh_eth_dev *eth) | |
122 | { | |
bd3980cc NI |
123 | int port = eth->port, len = 0; |
124 | struct sh_eth_info *port_info = ð->port_info[port]; | |
10cbe3b6 | 125 | uchar *packet; |
9751ee09 NI |
126 | |
127 | /* Check if the rx descriptor is ready */ | |
92f07134 | 128 | invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); |
9751ee09 NI |
129 | if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { |
130 | /* Check for errors */ | |
131 | if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { | |
132 | len = port_info->rx_desc_cur->rd1 & 0xffff; | |
10cbe3b6 JH |
133 | packet = (uchar *) |
134 | ADDR_TO_P2(port_info->rx_desc_cur->rd2); | |
92f07134 | 135 | invalidate_cache(packet, len); |
1fd92db8 | 136 | net_process_received_packet(packet, len); |
9751ee09 NI |
137 | } |
138 | ||
139 | /* Make current descriptor available again */ | |
140 | if (port_info->rx_desc_cur->rd0 & RD_RDLE) | |
141 | port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; | |
142 | else | |
143 | port_info->rx_desc_cur->rd0 = RD_RACT; | |
f7ca1f76 NI |
144 | |
145 | flush_cache_wback(port_info->rx_desc_cur, | |
146 | sizeof(struct rx_desc_s)); | |
147 | ||
9751ee09 NI |
148 | /* Point to the next descriptor */ |
149 | port_info->rx_desc_cur++; | |
150 | if (port_info->rx_desc_cur >= | |
151 | port_info->rx_desc_base + NUM_RX_DESC) | |
152 | port_info->rx_desc_cur = port_info->rx_desc_base; | |
153 | } | |
154 | ||
155 | /* Restart the receiver if disabled */ | |
fbfb5115 NI |
156 | if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R)) |
157 | sh_eth_write(port_info, EDRRR_R, EDRRR); | |
9751ee09 NI |
158 | |
159 | return len; | |
160 | } | |
161 | ||
dca221bd MV |
162 | static int sh_eth_recv_legacy(struct eth_device *dev) |
163 | { | |
164 | struct sh_eth_dev *eth = dev->priv; | |
165 | ||
166 | return sh_eth_recv_common(eth); | |
167 | } | |
168 | ||
bd3980cc | 169 | static int sh_eth_reset(struct sh_eth_dev *eth) |
9751ee09 | 170 | { |
fbfb5115 | 171 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
62cbddc4 | 172 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) |
bd3980cc | 173 | int ret = 0, i; |
9751ee09 NI |
174 | |
175 | /* Start e-dmac transmitter and receiver */ | |
fbfb5115 | 176 | sh_eth_write(port_info, EDSR_ENALL, EDSR); |
9751ee09 NI |
177 | |
178 | /* Perform a software reset and wait for it to complete */ | |
fbfb5115 | 179 | sh_eth_write(port_info, EDMR_SRST, EDMR); |
e2752db0 | 180 | for (i = 0; i < TIMEOUT_CNT; i++) { |
fbfb5115 | 181 | if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST)) |
9751ee09 NI |
182 | break; |
183 | udelay(1000); | |
184 | } | |
185 | ||
4ba62c72 | 186 | if (i == TIMEOUT_CNT) { |
bd3980cc NI |
187 | printf(SHETHER_NAME ": Software reset timeout\n"); |
188 | ret = -EIO; | |
9751ee09 | 189 | } |
bd3980cc NI |
190 | |
191 | return ret; | |
903de461 | 192 | #else |
fbfb5115 | 193 | sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR); |
903de461 | 194 | udelay(3000); |
fbfb5115 NI |
195 | sh_eth_write(port_info, |
196 | sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR); | |
903de461 YS |
197 | |
198 | return 0; | |
199 | #endif | |
9751ee09 NI |
200 | } |
201 | ||
bd3980cc | 202 | static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) |
9751ee09 | 203 | { |
bd3980cc | 204 | int port = eth->port, i, ret = 0; |
000889cd | 205 | u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s); |
bd3980cc | 206 | struct sh_eth_info *port_info = ð->port_info[port]; |
9751ee09 | 207 | struct tx_desc_s *cur_tx_desc; |
9751ee09 | 208 | |
bd3980cc | 209 | /* |
703949e4 NI |
210 | * Allocate rx descriptors. They must be aligned to size of struct |
211 | * tx_desc_s. | |
bd3980cc | 212 | */ |
000889cd NI |
213 | port_info->tx_desc_alloc = |
214 | memalign(sizeof(struct tx_desc_s), alloc_desc_size); | |
215 | if (!port_info->tx_desc_alloc) { | |
216 | printf(SHETHER_NAME ": memalign failed\n"); | |
bd3980cc NI |
217 | ret = -ENOMEM; |
218 | goto err; | |
9751ee09 | 219 | } |
bd3980cc | 220 | |
aae5d237 | 221 | flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size); |
000889cd | 222 | |
9751ee09 | 223 | /* Make sure we use a P2 address (non-cacheable) */ |
000889cd NI |
224 | port_info->tx_desc_base = |
225 | (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc); | |
9751ee09 NI |
226 | port_info->tx_desc_cur = port_info->tx_desc_base; |
227 | ||
228 | /* Initialize all descriptors */ | |
229 | for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC; | |
230 | cur_tx_desc++, i++) { | |
231 | cur_tx_desc->td0 = 0x00; | |
232 | cur_tx_desc->td1 = 0x00; | |
233 | cur_tx_desc->td2 = 0x00; | |
234 | } | |
235 | ||
236 | /* Mark the end of the descriptors */ | |
237 | cur_tx_desc--; | |
238 | cur_tx_desc->td0 |= TD_TDLE; | |
239 | ||
dc14867d NI |
240 | /* |
241 | * Point the controller to the tx descriptor list. Must use physical | |
242 | * addresses | |
243 | */ | |
fbfb5115 | 244 | sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR); |
62cbddc4 | 245 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) |
fbfb5115 NI |
246 | sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR); |
247 | sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR); | |
248 | sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */ | |
903de461 | 249 | #endif |
9751ee09 | 250 | |
bd3980cc NI |
251 | err: |
252 | return ret; | |
9751ee09 NI |
253 | } |
254 | ||
bd3980cc | 255 | static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) |
9751ee09 | 256 | { |
dc14867d | 257 | int port = eth->port, i, ret = 0; |
000889cd | 258 | u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s); |
bd3980cc | 259 | struct sh_eth_info *port_info = ð->port_info[port]; |
9751ee09 NI |
260 | struct rx_desc_s *cur_rx_desc; |
261 | u8 *rx_buf; | |
9751ee09 | 262 | |
bd3980cc | 263 | /* |
703949e4 NI |
264 | * Allocate rx descriptors. They must be aligned to size of struct |
265 | * rx_desc_s. | |
bd3980cc | 266 | */ |
000889cd NI |
267 | port_info->rx_desc_alloc = |
268 | memalign(sizeof(struct rx_desc_s), alloc_desc_size); | |
269 | if (!port_info->rx_desc_alloc) { | |
270 | printf(SHETHER_NAME ": memalign failed\n"); | |
bd3980cc NI |
271 | ret = -ENOMEM; |
272 | goto err; | |
9751ee09 | 273 | } |
bd3980cc | 274 | |
000889cd NI |
275 | flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size); |
276 | ||
9751ee09 | 277 | /* Make sure we use a P2 address (non-cacheable) */ |
000889cd NI |
278 | port_info->rx_desc_base = |
279 | (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc); | |
9751ee09 NI |
280 | |
281 | port_info->rx_desc_cur = port_info->rx_desc_base; | |
282 | ||
bd3980cc | 283 | /* |
000889cd NI |
284 | * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes |
285 | * aligned and in P2 area. | |
bd3980cc | 286 | */ |
000889cd NI |
287 | port_info->rx_buf_alloc = |
288 | memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE); | |
289 | if (!port_info->rx_buf_alloc) { | |
290 | printf(SHETHER_NAME ": alloc failed\n"); | |
bd3980cc | 291 | ret = -ENOMEM; |
000889cd | 292 | goto err_buf_alloc; |
9751ee09 | 293 | } |
bd3980cc | 294 | |
000889cd | 295 | port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc); |
9751ee09 NI |
296 | |
297 | /* Initialize all descriptors */ | |
298 | for (cur_rx_desc = port_info->rx_desc_base, | |
299 | rx_buf = port_info->rx_buf_base, i = 0; | |
300 | i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) { | |
301 | cur_rx_desc->rd0 = RD_RACT; | |
302 | cur_rx_desc->rd1 = MAX_BUF_SIZE << 16; | |
dc14867d | 303 | cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf); |
9751ee09 NI |
304 | } |
305 | ||
306 | /* Mark the end of the descriptors */ | |
307 | cur_rx_desc--; | |
308 | cur_rx_desc->rd0 |= RD_RDLE; | |
309 | ||
310 | /* Point the controller to the rx descriptor list */ | |
fbfb5115 | 311 | sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); |
62cbddc4 | 312 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) |
fbfb5115 NI |
313 | sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR); |
314 | sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR); | |
315 | sh_eth_write(port_info, RDFFR_RDLF, RDFFR); | |
903de461 | 316 | #endif |
9751ee09 | 317 | |
bd3980cc NI |
318 | return ret; |
319 | ||
000889cd NI |
320 | err_buf_alloc: |
321 | free(port_info->rx_desc_alloc); | |
322 | port_info->rx_desc_alloc = NULL; | |
bd3980cc NI |
323 | |
324 | err: | |
325 | return ret; | |
9751ee09 NI |
326 | } |
327 | ||
bd3980cc | 328 | static void sh_eth_tx_desc_free(struct sh_eth_dev *eth) |
9751ee09 | 329 | { |
bd3980cc NI |
330 | int port = eth->port; |
331 | struct sh_eth_info *port_info = ð->port_info[port]; | |
9751ee09 | 332 | |
000889cd NI |
333 | if (port_info->tx_desc_alloc) { |
334 | free(port_info->tx_desc_alloc); | |
335 | port_info->tx_desc_alloc = NULL; | |
9751ee09 | 336 | } |
bd3980cc NI |
337 | } |
338 | ||
339 | static void sh_eth_rx_desc_free(struct sh_eth_dev *eth) | |
340 | { | |
341 | int port = eth->port; | |
342 | struct sh_eth_info *port_info = ð->port_info[port]; | |
9751ee09 | 343 | |
000889cd NI |
344 | if (port_info->rx_desc_alloc) { |
345 | free(port_info->rx_desc_alloc); | |
346 | port_info->rx_desc_alloc = NULL; | |
9751ee09 NI |
347 | } |
348 | ||
000889cd NI |
349 | if (port_info->rx_buf_alloc) { |
350 | free(port_info->rx_buf_alloc); | |
351 | port_info->rx_buf_alloc = NULL; | |
9751ee09 NI |
352 | } |
353 | } | |
354 | ||
bd3980cc | 355 | static int sh_eth_desc_init(struct sh_eth_dev *eth) |
9751ee09 | 356 | { |
bd3980cc | 357 | int ret = 0; |
9751ee09 | 358 | |
bd3980cc NI |
359 | ret = sh_eth_tx_desc_init(eth); |
360 | if (ret) | |
361 | goto err_tx_init; | |
9751ee09 | 362 | |
bd3980cc NI |
363 | ret = sh_eth_rx_desc_init(eth); |
364 | if (ret) | |
365 | goto err_rx_init; | |
366 | ||
367 | return ret; | |
368 | err_rx_init: | |
369 | sh_eth_tx_desc_free(eth); | |
370 | ||
371 | err_tx_init: | |
372 | return ret; | |
9751ee09 NI |
373 | } |
374 | ||
bd3980cc | 375 | static int sh_eth_phy_config(struct sh_eth_dev *eth) |
9751ee09 | 376 | { |
bd1024b0 | 377 | int port = eth->port, ret = 0; |
bd3980cc | 378 | struct sh_eth_info *port_info = ð->port_info[port]; |
bd1024b0 YS |
379 | struct eth_device *dev = port_info->dev; |
380 | struct phy_device *phydev; | |
9751ee09 | 381 | |
ee6ec5d4 NI |
382 | phydev = phy_connect( |
383 | miiphy_get_dev_by_name(dev->name), | |
4398d559 | 384 | port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE); |
bd1024b0 YS |
385 | port_info->phydev = phydev; |
386 | phy_config(phydev); | |
bd3980cc | 387 | |
bd3980cc | 388 | return ret; |
9751ee09 NI |
389 | } |
390 | ||
9b5f9ecf | 391 | static int sh_eth_config(struct sh_eth_dev *eth) |
9751ee09 | 392 | { |
bd3980cc | 393 | int port = eth->port, ret = 0; |
bd1024b0 | 394 | u32 val; |
bd3980cc | 395 | struct sh_eth_info *port_info = ð->port_info[port]; |
c527ce92 | 396 | struct eth_device *dev = port_info->dev; |
bd1024b0 | 397 | struct phy_device *phy; |
9751ee09 NI |
398 | |
399 | /* Configure e-dmac registers */ | |
fbfb5115 | 400 | sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) | |
f8b7507d NI |
401 | (EMDR_DESC | EDMR_EL), EDMR); |
402 | ||
fbfb5115 NI |
403 | sh_eth_write(port_info, 0, EESIPR); |
404 | sh_eth_write(port_info, 0, TRSCER); | |
405 | sh_eth_write(port_info, 0, TFTR); | |
406 | sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); | |
407 | sh_eth_write(port_info, RMCR_RST, RMCR); | |
62cbddc4 | 408 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) |
fbfb5115 | 409 | sh_eth_write(port_info, 0, RPADIR); |
903de461 | 410 | #endif |
fbfb5115 | 411 | sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); |
9751ee09 NI |
412 | |
413 | /* Configure e-mac registers */ | |
fbfb5115 | 414 | sh_eth_write(port_info, 0, ECSIPR); |
9751ee09 NI |
415 | |
416 | /* Set Mac address */ | |
c527ce92 MF |
417 | val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | |
418 | dev->enetaddr[2] << 8 | dev->enetaddr[3]; | |
fbfb5115 | 419 | sh_eth_write(port_info, val, MAHR); |
9751ee09 | 420 | |
c527ce92 | 421 | val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; |
fbfb5115 | 422 | sh_eth_write(port_info, val, MALR); |
9751ee09 | 423 | |
fbfb5115 | 424 | sh_eth_write(port_info, RFLR_RFL_MIN, RFLR); |
26235093 | 425 | #if defined(SH_ETH_TYPE_GETHER) |
fbfb5115 | 426 | sh_eth_write(port_info, 0, PIPR); |
62cbddc4 NI |
427 | #endif |
428 | #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) | |
fbfb5115 NI |
429 | sh_eth_write(port_info, APR_AP, APR); |
430 | sh_eth_write(port_info, MPR_MP, MPR); | |
431 | sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER); | |
903de461 | 432 | #endif |
3bb4cc31 | 433 | |
dcd5a593 | 434 | #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) |
fbfb5115 | 435 | sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); |
effb7902 | 436 | #elif defined(CONFIG_RCAR_GEN2) |
fbfb5115 | 437 | sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR); |
4398d559 | 438 | #endif |
9751ee09 | 439 | /* Configure phy */ |
bd3980cc NI |
440 | ret = sh_eth_phy_config(eth); |
441 | if (ret) { | |
88a4c2e7 | 442 | printf(SHETHER_NAME ": phy config timeout\n"); |
bd3980cc NI |
443 | goto err_phy_cfg; |
444 | } | |
bd1024b0 | 445 | phy = port_info->phydev; |
11af8d65 TT |
446 | ret = phy_startup(phy); |
447 | if (ret) { | |
448 | printf(SHETHER_NAME ": phy startup failure\n"); | |
449 | return ret; | |
450 | } | |
9751ee09 | 451 | |
3bb4cc31 NI |
452 | val = 0; |
453 | ||
9751ee09 | 454 | /* Set the transfer speed */ |
bd1024b0 | 455 | if (phy->speed == 100) { |
bd3980cc | 456 | printf(SHETHER_NAME ": 100Base/"); |
26235093 | 457 | #if defined(SH_ETH_TYPE_GETHER) |
fbfb5115 | 458 | sh_eth_write(port_info, GECMR_100B, GECMR); |
e3bb3254 | 459 | #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) |
fbfb5115 | 460 | sh_eth_write(port_info, 1, RTRATE); |
effb7902 | 461 | #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2) |
3bb4cc31 NI |
462 | val = ECMR_RTM; |
463 | #endif | |
bd1024b0 | 464 | } else if (phy->speed == 10) { |
bd3980cc | 465 | printf(SHETHER_NAME ": 10Base/"); |
26235093 | 466 | #if defined(SH_ETH_TYPE_GETHER) |
fbfb5115 | 467 | sh_eth_write(port_info, GECMR_10B, GECMR); |
e3bb3254 | 468 | #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) |
fbfb5115 | 469 | sh_eth_write(port_info, 0, RTRATE); |
903de461 | 470 | #endif |
3bb4cc31 | 471 | } |
26235093 | 472 | #if defined(SH_ETH_TYPE_GETHER) |
4398d559 NI |
473 | else if (phy->speed == 1000) { |
474 | printf(SHETHER_NAME ": 1000Base/"); | |
fbfb5115 | 475 | sh_eth_write(port_info, GECMR_1000B, GECMR); |
4398d559 NI |
476 | } |
477 | #endif | |
9751ee09 NI |
478 | |
479 | /* Check if full duplex mode is supported by the phy */ | |
bd1024b0 | 480 | if (phy->duplex) { |
9751ee09 | 481 | printf("Full\n"); |
fbfb5115 | 482 | sh_eth_write(port_info, |
dc14867d | 483 | val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM), |
49afb8ca | 484 | ECMR); |
9751ee09 NI |
485 | } else { |
486 | printf("Half\n"); | |
fbfb5115 | 487 | sh_eth_write(port_info, |
dc14867d NI |
488 | val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE), |
489 | ECMR); | |
9751ee09 | 490 | } |
bd3980cc NI |
491 | |
492 | return ret; | |
493 | ||
494 | err_phy_cfg: | |
495 | return ret; | |
9751ee09 NI |
496 | } |
497 | ||
bd3980cc | 498 | static void sh_eth_start(struct sh_eth_dev *eth) |
9751ee09 | 499 | { |
fbfb5115 NI |
500 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
501 | ||
9751ee09 NI |
502 | /* |
503 | * Enable the e-dmac receiver only. The transmitter will be enabled when | |
504 | * we have something to transmit | |
505 | */ | |
fbfb5115 | 506 | sh_eth_write(port_info, EDRRR_R, EDRRR); |
bd3980cc | 507 | } |
9751ee09 | 508 | |
bd3980cc NI |
509 | static void sh_eth_stop(struct sh_eth_dev *eth) |
510 | { | |
fbfb5115 NI |
511 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
512 | ||
513 | sh_eth_write(port_info, ~EDRRR_R, EDRRR); | |
9751ee09 NI |
514 | } |
515 | ||
bd3980cc | 516 | int sh_eth_init(struct eth_device *dev, bd_t *bd) |
9751ee09 | 517 | { |
bd3980cc NI |
518 | int ret = 0; |
519 | struct sh_eth_dev *eth = dev->priv; | |
9751ee09 | 520 | |
bd3980cc NI |
521 | ret = sh_eth_reset(eth); |
522 | if (ret) | |
523 | goto err; | |
9751ee09 | 524 | |
bd3980cc NI |
525 | ret = sh_eth_desc_init(eth); |
526 | if (ret) | |
527 | goto err; | |
9751ee09 | 528 | |
9b5f9ecf | 529 | ret = sh_eth_config(eth); |
bd3980cc NI |
530 | if (ret) |
531 | goto err_config; | |
532 | ||
533 | sh_eth_start(eth); | |
534 | ||
535 | return ret; | |
9751ee09 | 536 | |
bd3980cc NI |
537 | err_config: |
538 | sh_eth_tx_desc_free(eth); | |
539 | sh_eth_rx_desc_free(eth); | |
540 | ||
541 | err: | |
542 | return ret; | |
543 | } | |
544 | ||
545 | void sh_eth_halt(struct eth_device *dev) | |
546 | { | |
547 | struct sh_eth_dev *eth = dev->priv; | |
dc14867d | 548 | |
bd3980cc NI |
549 | sh_eth_stop(eth); |
550 | } | |
551 | ||
552 | int sh_eth_initialize(bd_t *bd) | |
553 | { | |
e2752db0 | 554 | int ret = 0; |
bd3980cc | 555 | struct sh_eth_dev *eth = NULL; |
e2752db0 | 556 | struct eth_device *dev = NULL; |
dc14867d | 557 | struct mii_dev *mdiodev; |
bd3980cc | 558 | |
e2752db0 | 559 | eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev)); |
bd3980cc NI |
560 | if (!eth) { |
561 | printf(SHETHER_NAME ": %s: malloc failed\n", __func__); | |
562 | ret = -ENOMEM; | |
9751ee09 | 563 | goto err; |
bd3980cc | 564 | } |
9751ee09 | 565 | |
e2752db0 | 566 | dev = (struct eth_device *)malloc(sizeof(struct eth_device)); |
bd3980cc NI |
567 | if (!dev) { |
568 | printf(SHETHER_NAME ": %s: malloc failed\n", __func__); | |
569 | ret = -ENOMEM; | |
570 | goto err; | |
571 | } | |
e2752db0 NI |
572 | memset(dev, 0, sizeof(struct eth_device)); |
573 | memset(eth, 0, sizeof(struct sh_eth_dev)); | |
9751ee09 | 574 | |
bd3980cc NI |
575 | eth->port = CONFIG_SH_ETHER_USE_PORT; |
576 | eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR; | |
fbfb5115 NI |
577 | eth->port_info[eth->port].iobase = |
578 | (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port); | |
bd3980cc | 579 | |
e2752db0 NI |
580 | dev->priv = (void *)eth; |
581 | dev->iobase = 0; | |
582 | dev->init = sh_eth_init; | |
583 | dev->halt = sh_eth_halt; | |
dca221bd MV |
584 | dev->send = sh_eth_send_legacy; |
585 | dev->recv = sh_eth_recv_legacy; | |
e2752db0 | 586 | eth->port_info[eth->port].dev = dev; |
bd3980cc | 587 | |
192bc694 | 588 | strcpy(dev->name, SHETHER_NAME); |
bd3980cc | 589 | |
e2752db0 NI |
590 | /* Register Device to EtherNet subsystem */ |
591 | eth_register(dev); | |
bd3980cc | 592 | |
bd1024b0 | 593 | bb_miiphy_buses[0].priv = eth; |
dc14867d | 594 | mdiodev = mdio_alloc(); |
5a49f174 JH |
595 | if (!mdiodev) |
596 | return -ENOMEM; | |
597 | strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); | |
598 | mdiodev->read = bb_miiphy_read; | |
599 | mdiodev->write = bb_miiphy_write; | |
600 | ||
dc14867d NI |
601 | ret = mdio_register(mdiodev); |
602 | if (ret < 0) | |
603 | return ret; | |
bd1024b0 | 604 | |
35affd7a | 605 | if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr)) |
c527ce92 | 606 | puts("Please set MAC address\n"); |
bd3980cc NI |
607 | |
608 | return ret; | |
9751ee09 | 609 | |
9751ee09 | 610 | err: |
bd3980cc NI |
611 | if (dev) |
612 | free(dev); | |
613 | ||
614 | if (eth) | |
615 | free(eth); | |
616 | ||
617 | printf(SHETHER_NAME ": Failed\n"); | |
618 | return ret; | |
9751ee09 | 619 | } |
bd1024b0 YS |
620 | |
621 | /******* for bb_miiphy *******/ | |
622 | static int sh_eth_bb_init(struct bb_miiphy_bus *bus) | |
623 | { | |
624 | return 0; | |
625 | } | |
626 | ||
627 | static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) | |
628 | { | |
629 | struct sh_eth_dev *eth = bus->priv; | |
fbfb5115 | 630 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
bd1024b0 | 631 | |
fbfb5115 | 632 | sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR); |
bd1024b0 YS |
633 | |
634 | return 0; | |
635 | } | |
636 | ||
637 | static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) | |
638 | { | |
639 | struct sh_eth_dev *eth = bus->priv; | |
fbfb5115 | 640 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
bd1024b0 | 641 | |
fbfb5115 | 642 | sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR); |
bd1024b0 YS |
643 | |
644 | return 0; | |
645 | } | |
646 | ||
647 | static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) | |
648 | { | |
649 | struct sh_eth_dev *eth = bus->priv; | |
fbfb5115 | 650 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
bd1024b0 YS |
651 | |
652 | if (v) | |
fbfb5115 NI |
653 | sh_eth_write(port_info, |
654 | sh_eth_read(port_info, PIR) | PIR_MDO, PIR); | |
bd1024b0 | 655 | else |
fbfb5115 NI |
656 | sh_eth_write(port_info, |
657 | sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR); | |
bd1024b0 YS |
658 | |
659 | return 0; | |
660 | } | |
661 | ||
662 | static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) | |
663 | { | |
664 | struct sh_eth_dev *eth = bus->priv; | |
fbfb5115 | 665 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
bd1024b0 | 666 | |
fbfb5115 | 667 | *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3; |
bd1024b0 YS |
668 | |
669 | return 0; | |
670 | } | |
671 | ||
672 | static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) | |
673 | { | |
674 | struct sh_eth_dev *eth = bus->priv; | |
fbfb5115 | 675 | struct sh_eth_info *port_info = ð->port_info[eth->port]; |
bd1024b0 YS |
676 | |
677 | if (v) | |
fbfb5115 NI |
678 | sh_eth_write(port_info, |
679 | sh_eth_read(port_info, PIR) | PIR_MDC, PIR); | |
bd1024b0 | 680 | else |
fbfb5115 NI |
681 | sh_eth_write(port_info, |
682 | sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR); | |
bd1024b0 YS |
683 | |
684 | return 0; | |
685 | } | |
686 | ||
687 | static int sh_eth_bb_delay(struct bb_miiphy_bus *bus) | |
688 | { | |
689 | udelay(10); | |
690 | ||
691 | return 0; | |
692 | } | |
693 | ||
694 | struct bb_miiphy_bus bb_miiphy_buses[] = { | |
695 | { | |
696 | .name = "sh_eth", | |
697 | .init = sh_eth_bb_init, | |
698 | .mdio_active = sh_eth_bb_mdio_active, | |
699 | .mdio_tristate = sh_eth_bb_mdio_tristate, | |
700 | .set_mdio = sh_eth_bb_set_mdio, | |
701 | .get_mdio = sh_eth_bb_get_mdio, | |
702 | .set_mdc = sh_eth_bb_set_mdc, | |
703 | .delay = sh_eth_bb_delay, | |
704 | } | |
705 | }; | |
dc14867d | 706 | |
bd1024b0 | 707 | int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); |