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fe8c2806 WD |
1 | /*------------------------------------------------------------------------ |
2 | . smc91111.c | |
3 | . This is a driver for SMSC's 91C111 single-chip Ethernet device. | |
4 | . | |
5 | . (C) Copyright 2002 | |
6 | . Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | . Rolf Offermanns <rof@sysgo.de> | |
8 | . | |
9 | . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) | |
42dfe7a1 | 10 | . Developed by Simple Network Magic Corporation (SNMC) |
fe8c2806 WD |
11 | . Copyright (C) 1996 by Erik Stahlman (ES) |
12 | . | |
13 | . This program is free software; you can redistribute it and/or modify | |
14 | . it under the terms of the GNU General Public License as published by | |
15 | . the Free Software Foundation; either version 2 of the License, or | |
16 | . (at your option) any later version. | |
17 | . | |
18 | . This program is distributed in the hope that it will be useful, | |
19 | . but WITHOUT ANY WARRANTY; without even the implied warranty of | |
42dfe7a1 | 20 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
fe8c2806 WD |
21 | . GNU General Public License for more details. |
22 | . | |
23 | . You should have received a copy of the GNU General Public License | |
24 | . along with this program; if not, write to the Free Software | |
42dfe7a1 | 25 | . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
fe8c2806 WD |
26 | . |
27 | . Information contained in this file was obtained from the LAN91C111 | |
28 | . manual from SMC. To get a copy, if you really want one, you can find | |
29 | . information under www.smsc.com. | |
30 | . | |
31 | . | |
32 | . "Features" of the SMC chip: | |
33 | . Integrated PHY/MAC for 10/100BaseT Operation | |
34 | . Supports internal and external MII | |
35 | . Integrated 8K packet memory | |
36 | . EEPROM interface for configuration | |
37 | . | |
38 | . Arguments: | |
42dfe7a1 | 39 | . io = for the base address |
fe8c2806 WD |
40 | . irq = for the IRQ |
41 | . | |
42 | . author: | |
42dfe7a1 WD |
43 | . Erik Stahlman ( erik@vt.edu ) |
44 | . Daris A Nevil ( dnevil@snmc.com ) | |
fe8c2806 WD |
45 | . |
46 | . | |
47 | . Hardware multicast code from Peter Cammaert ( pc@denkart.be ) | |
48 | . | |
49 | . Sources: | |
42dfe7a1 WD |
50 | . o SMSC LAN91C111 databook (www.smsc.com) |
51 | . o smc9194.c by Erik Stahlman | |
52 | . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov ) | |
fe8c2806 WD |
53 | . |
54 | . History: | |
42dfe7a1 | 55 | . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks. |
fe8c2806 | 56 | . 10/17/01 Marco Hasewinkel Modify for DNP/1110 |
42dfe7a1 WD |
57 | . 07/25/01 Woojung Huh Modify for ADS Bitsy |
58 | . 04/25/01 Daris A Nevil Initial public release through SMSC | |
59 | . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111 | |
fe8c2806 WD |
60 | ----------------------------------------------------------------------------*/ |
61 | ||
62 | #include <common.h> | |
63 | #include <command.h> | |
f39748ae | 64 | #include <config.h> |
fe8c2806 WD |
65 | #include "smc91111.h" |
66 | #include <net.h> | |
67 | ||
fe8c2806 WD |
68 | /* Use power-down feature of the chip */ |
69 | #define POWER_DOWN 0 | |
70 | ||
71 | #define NO_AUTOPROBE | |
72 | ||
0be248fa | 73 | #define SMC_DEBUG 0 |
8bf3b005 WD |
74 | |
75 | #if SMC_DEBUG > 1 | |
fe8c2806 WD |
76 | static const char version[] = |
77 | "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n"; | |
8bf3b005 | 78 | #endif |
fe8c2806 | 79 | |
f39748ae WD |
80 | /* Autonegotiation timeout in seconds */ |
81 | #ifndef CONFIG_SMC_AUTONEG_TIMEOUT | |
82 | #define CONFIG_SMC_AUTONEG_TIMEOUT 10 | |
83 | #endif | |
84 | ||
fe8c2806 WD |
85 | /*------------------------------------------------------------------------ |
86 | . | |
87 | . Configuration options, for the experienced user to change. | |
88 | . | |
89 | -------------------------------------------------------------------------*/ | |
90 | ||
91 | /* | |
92 | . Wait time for memory to be free. This probably shouldn't be | |
93 | . tuned that much, as waiting for this means nothing else happens | |
94 | . in the system | |
95 | */ | |
96 | #define MEMORY_WAIT_TIME 16 | |
97 | ||
98 | ||
99 | #if (SMC_DEBUG > 2 ) | |
100 | #define PRINTK3(args...) printf(args) | |
101 | #else | |
102 | #define PRINTK3(args...) | |
103 | #endif | |
104 | ||
105 | #if SMC_DEBUG > 1 | |
106 | #define PRINTK2(args...) printf(args) | |
107 | #else | |
108 | #define PRINTK2(args...) | |
109 | #endif | |
110 | ||
111 | #ifdef SMC_DEBUG | |
112 | #define PRINTK(args...) printf(args) | |
113 | #else | |
114 | #define PRINTK(args...) | |
115 | #endif | |
116 | ||
117 | ||
118 | /*------------------------------------------------------------------------ | |
119 | . | |
42dfe7a1 | 120 | . The internal workings of the driver. If you are changing anything |
fe8c2806 WD |
121 | . here with the SMC stuff, you should have the datasheet and know |
122 | . what you are doing. | |
123 | . | |
124 | -------------------------------------------------------------------------*/ | |
125 | #define CARDNAME "LAN91C111" | |
126 | ||
127 | /* Memory sizing constant */ | |
128 | #define LAN91C111_MEMORY_MULTIPLIER (1024*2) | |
129 | ||
130 | #ifndef CONFIG_SMC91111_BASE | |
131 | #define CONFIG_SMC91111_BASE 0x20000300 | |
132 | #endif | |
133 | ||
134 | #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE | |
135 | ||
136 | #define SMC_DEV_NAME "SMC91111" | |
137 | #define SMC_PHY_ADDR 0x0000 | |
138 | #define SMC_ALLOC_MAX_TRY 5 | |
139 | #define SMC_TX_TIMEOUT 30 | |
140 | ||
141 | #define SMC_PHY_CLOCK_DELAY 1000 | |
142 | ||
143 | #define ETH_ZLEN 60 | |
144 | ||
42dfe7a1 | 145 | #ifdef CONFIG_SMC_USE_32_BIT |
fe8c2806 WD |
146 | #define USE_32_BIT 1 |
147 | #else | |
148 | #undef USE_32_BIT | |
149 | #endif | |
150 | /*----------------------------------------------------------------- | |
151 | . | |
152 | . The driver can be entered at any of the following entry points. | |
153 | . | |
154 | .------------------------------------------------------------------ */ | |
155 | ||
156 | extern int eth_init(bd_t *bd); | |
157 | extern void eth_halt(void); | |
158 | extern int eth_rx(void); | |
159 | extern int eth_send(volatile void *packet, int length); | |
160 | ||
0afe519a WD |
161 | #ifdef SHARED_RESOURCES |
162 | extern void swap_to(int device_id); | |
163 | #endif | |
fe8c2806 | 164 | |
fe8c2806 WD |
165 | /* |
166 | . This is called by register_netdev(). It is responsible for | |
167 | . checking the portlist for the SMC9000 series chipset. If it finds | |
168 | . one, then it will initialize the device, find the hardware information, | |
169 | . and sets up the appropriate device parameters. | |
170 | . NOTE: Interrupts are *OFF* when this procedure is called. | |
171 | . | |
172 | . NB:This shouldn't be static since it is referred to externally. | |
173 | */ | |
174 | int smc_init(void); | |
175 | ||
176 | /* | |
177 | . This is called by unregister_netdev(). It is responsible for | |
178 | . cleaning up before the driver is finally unregistered and discarded. | |
179 | */ | |
180 | void smc_destructor(void); | |
181 | ||
182 | /* | |
183 | . The kernel calls this function when someone wants to use the device, | |
184 | . typically 'ifconfig ethX up'. | |
185 | */ | |
0b97ab14 | 186 | static int smc_open(bd_t *bd); |
fe8c2806 WD |
187 | |
188 | ||
189 | /* | |
190 | . This is called by the kernel in response to 'ifconfig ethX down'. It | |
191 | . is responsible for cleaning up everything that the open routine | |
192 | . does, and maybe putting the card into a powerdown state. | |
193 | */ | |
194 | static int smc_close(void); | |
195 | ||
196 | /* | |
197 | . Configures the PHY through the MII Management interface | |
198 | */ | |
199 | #ifndef CONFIG_SMC91111_EXT_PHY | |
200 | static void smc_phy_configure(void); | |
201 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
202 | ||
203 | /* | |
204 | . This is a separate procedure to handle the receipt of a packet, to | |
205 | . leave the interrupt code looking slightly cleaner | |
206 | */ | |
207 | static int smc_rcv(void); | |
208 | ||
0b97ab14 | 209 | /* See if a MAC address is defined in the current environment. If so use it. If not |
8bde7f77 | 210 | . print a warning and set the environment and other globals with the default. |
0b97ab14 WD |
211 | . If an EEPROM is present it really should be consulted. |
212 | */ | |
213 | int smc_get_ethaddr(bd_t *bd); | |
d52fb7e3 | 214 | int get_rom_mac(uchar *v_rom_mac); |
fe8c2806 WD |
215 | |
216 | /* | |
217 | ------------------------------------------------------------ | |
218 | . | |
219 | . Internal routines | |
220 | . | |
221 | ------------------------------------------------------------ | |
222 | */ | |
223 | ||
c3c7f861 WD |
224 | #ifdef CONFIG_SMC_USE_IOFUNCS |
225 | /* | |
226 | * input and output functions | |
227 | * | |
228 | * Implemented due to inx,outx macros accessing the device improperly | |
229 | * and putting the device into an unkown state. | |
230 | * | |
231 | * For instance, on Sharp LPD7A400 SDK, affects were chip memory | |
232 | * could not be free'd (hence the alloc failures), duplicate packets, | |
233 | * packets being corrupt (shifted) on the wire, etc. Switching to the | |
234 | * inx,outx functions fixed this problem. | |
235 | */ | |
236 | static inline word SMC_inw(dword offset); | |
237 | static inline void SMC_outw(word value, dword offset); | |
238 | static inline byte SMC_inb(dword offset); | |
239 | static inline void SMC_outb(byte value, dword offset); | |
240 | static inline void SMC_insw(dword offset, volatile uchar* buf, dword len); | |
241 | static inline void SMC_outsw(dword offset, uchar* buf, dword len); | |
242 | ||
243 | #define barrier() __asm__ __volatile__("": : :"memory") | |
244 | ||
245 | static inline word SMC_inw(dword offset) | |
246 | { | |
247 | word v; | |
248 | v = *((volatile word*)(SMC_BASE_ADDRESS+offset)); | |
249 | barrier(); *(volatile u32*)(0xc0000000); | |
250 | return v; | |
251 | } | |
252 | ||
253 | static inline void SMC_outw(word value, dword offset) | |
254 | { | |
255 | *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value; | |
256 | barrier(); *(volatile u32*)(0xc0000000); | |
257 | } | |
258 | ||
259 | static inline byte SMC_inb(dword offset) | |
260 | { | |
261 | word _w; | |
262 | ||
263 | _w = SMC_inw(offset & ~((dword)1)); | |
264 | return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w); | |
265 | } | |
266 | ||
267 | static inline void SMC_outb(byte value, dword offset) | |
268 | { | |
269 | word _w; | |
270 | ||
271 | _w = SMC_inw(offset & ~((dword)1)); | |
272 | if (offset & 1) | |
273 | *((volatile word*)(SMC_BASE_ADDRESS+(offset & ~((dword)1)))) = (value<<8) | (_w & 0x00ff); | |
274 | else | |
275 | *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value | (_w & 0xff00); | |
276 | } | |
277 | ||
278 | static inline void SMC_insw(dword offset, volatile uchar* buf, dword len) | |
279 | { | |
d52fb7e3 WD |
280 | volatile word *p = (volatile word *)buf; |
281 | ||
c3c7f861 | 282 | while (len-- > 0) { |
d52fb7e3 WD |
283 | *p++ = SMC_inw(offset); |
284 | barrier(); | |
285 | *((volatile u32*)(0xc0000000)); | |
c3c7f861 WD |
286 | } |
287 | } | |
288 | ||
289 | static inline void SMC_outsw(dword offset, uchar* buf, dword len) | |
290 | { | |
d52fb7e3 WD |
291 | volatile word *p = (volatile word *)buf; |
292 | ||
c3c7f861 | 293 | while (len-- > 0) { |
d52fb7e3 WD |
294 | SMC_outw(*p++, offset); |
295 | barrier(); | |
296 | *(volatile u32*)(0xc0000000); | |
c3c7f861 WD |
297 | } |
298 | } | |
299 | #endif /* CONFIG_SMC_USE_IOFUNCS */ | |
300 | ||
8bf3b005 | 301 | static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8}; |
fe8c2806 WD |
302 | |
303 | /* | |
304 | * This function must be called before smc_open() if you want to override | |
305 | * the default mac address. | |
306 | */ | |
307 | ||
d52fb7e3 | 308 | void smc_set_mac_addr(const unsigned char *addr) { |
fe8c2806 WD |
309 | int i; |
310 | ||
311 | for (i=0; i < sizeof(smc_mac_addr); i++){ | |
312 | smc_mac_addr[i] = addr[i]; | |
313 | } | |
314 | } | |
315 | ||
316 | /* | |
317 | * smc_get_macaddr is no longer used. If you want to override the default | |
0b97ab14 | 318 | * mac address, call smc_get_mac_addr as a part of the board initialization. |
fe8c2806 WD |
319 | */ |
320 | ||
321 | #if 0 | |
322 | void smc_get_macaddr( byte *addr ) { | |
323 | /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */ | |
8bde7f77 | 324 | unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010); |
fe8c2806 WD |
325 | int i; |
326 | ||
327 | ||
8bde7f77 WD |
328 | for (i=0; i<6; i++) { |
329 | addr[0] = *(dnp1110_mac+0); | |
330 | addr[1] = *(dnp1110_mac+1); | |
331 | addr[2] = *(dnp1110_mac+2); | |
332 | addr[3] = *(dnp1110_mac+3); | |
333 | addr[4] = *(dnp1110_mac+4); | |
334 | addr[5] = *(dnp1110_mac+5); | |
335 | } | |
fe8c2806 WD |
336 | } |
337 | #endif /* 0 */ | |
338 | ||
339 | /*********************************************** | |
42dfe7a1 | 340 | * Show available memory * |
fe8c2806 WD |
341 | ***********************************************/ |
342 | void dump_memory_info(void) | |
343 | { | |
8bde7f77 WD |
344 | word mem_info; |
345 | word old_bank; | |
fe8c2806 | 346 | |
8bde7f77 | 347 | old_bank = SMC_inw(BANK_SELECT)&0xF; |
fe8c2806 | 348 | |
8bde7f77 WD |
349 | SMC_SELECT_BANK(0); |
350 | mem_info = SMC_inw( MIR_REG ); | |
351 | PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048); | |
fe8c2806 | 352 | |
8bde7f77 | 353 | SMC_SELECT_BANK(old_bank); |
fe8c2806 WD |
354 | } |
355 | /* | |
356 | . A rather simple routine to print out a packet for debugging purposes. | |
357 | */ | |
358 | #if SMC_DEBUG > 2 | |
359 | static void print_packet( byte *, int ); | |
360 | #endif | |
361 | ||
362 | #define tx_done(dev) 1 | |
363 | ||
364 | ||
fe8c2806 WD |
365 | /* this does a soft reset on the device */ |
366 | static void smc_reset( void ); | |
367 | ||
368 | /* Enable Interrupts, Receive, and Transmit */ | |
369 | static void smc_enable( void ); | |
370 | ||
371 | /* this puts the device in an inactive state */ | |
372 | static void smc_shutdown( void ); | |
373 | ||
374 | /* Routines to Read and Write the PHY Registers across the | |
375 | MII Management Interface | |
376 | */ | |
377 | ||
378 | #ifndef CONFIG_SMC91111_EXT_PHY | |
379 | static word smc_read_phy_register(byte phyreg); | |
380 | static void smc_write_phy_register(byte phyreg, word phydata); | |
381 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
382 | ||
383 | ||
b56ddc63 WD |
384 | static int poll4int (byte mask, int timeout) |
385 | { | |
6d0f6bcf | 386 | int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; |
b56ddc63 WD |
387 | int is_timeout = 0; |
388 | word old_bank = SMC_inw (BSR_REG); | |
389 | ||
390 | PRINTK2 ("Polling...\n"); | |
391 | SMC_SELECT_BANK (2); | |
392 | while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) { | |
393 | if (get_timer (0) >= tmo) { | |
394 | is_timeout = 1; | |
395 | break; | |
396 | } | |
fe8c2806 | 397 | } |
fe8c2806 | 398 | |
b56ddc63 WD |
399 | /* restore old bank selection */ |
400 | SMC_SELECT_BANK (old_bank); | |
fe8c2806 | 401 | |
b56ddc63 WD |
402 | if (is_timeout) |
403 | return 1; | |
404 | else | |
405 | return 0; | |
fe8c2806 WD |
406 | } |
407 | ||
487778b7 | 408 | /* Only one release command at a time, please */ |
b56ddc63 | 409 | static inline void smc_wait_mmu_release_complete (void) |
487778b7 WD |
410 | { |
411 | int count = 0; | |
b56ddc63 | 412 | |
487778b7 | 413 | /* assume bank 2 selected */ |
b56ddc63 WD |
414 | while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { |
415 | udelay (1); /* Wait until not busy */ | |
416 | if (++count > 200) | |
417 | break; | |
487778b7 WD |
418 | } |
419 | } | |
420 | ||
fe8c2806 WD |
421 | /* |
422 | . Function: smc_reset( void ) | |
423 | . Purpose: | |
42dfe7a1 WD |
424 | . This sets the SMC91111 chip to its normal state, hopefully from whatever |
425 | . mess that any other DOS driver has put it in. | |
fe8c2806 WD |
426 | . |
427 | . Maybe I should reset more registers to defaults in here? SOFTRST should | |
428 | . do that for me. | |
429 | . | |
430 | . Method: | |
431 | . 1. send a SOFT RESET | |
432 | . 2. wait for it to finish | |
433 | . 3. enable autorelease mode | |
434 | . 4. reset the memory management unit | |
435 | . 5. clear all interrupts | |
436 | . | |
437 | */ | |
b56ddc63 | 438 | static void smc_reset (void) |
fe8c2806 | 439 | { |
f39748ae | 440 | PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME); |
fe8c2806 WD |
441 | |
442 | /* This resets the registers mostly to defaults, but doesn't | |
443 | affect EEPROM. That seems unnecessary */ | |
b56ddc63 WD |
444 | SMC_SELECT_BANK (0); |
445 | SMC_outw (RCR_SOFTRST, RCR_REG); | |
fe8c2806 WD |
446 | |
447 | /* Setup the Configuration Register */ | |
448 | /* This is necessary because the CONFIG_REG is not affected */ | |
449 | /* by a soft reset */ | |
450 | ||
b56ddc63 | 451 | SMC_SELECT_BANK (1); |
fe8c2806 | 452 | #if defined(CONFIG_SMC91111_EXT_PHY) |
b56ddc63 | 453 | SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); |
fe8c2806 | 454 | #else |
b56ddc63 | 455 | SMC_outw (CONFIG_DEFAULT, CONFIG_REG); |
fe8c2806 WD |
456 | #endif |
457 | ||
458 | ||
459 | /* Release from possible power-down state */ | |
460 | /* Configuration register is not affected by Soft Reset */ | |
b56ddc63 | 461 | SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG); |
fe8c2806 | 462 | |
b56ddc63 | 463 | SMC_SELECT_BANK (0); |
fe8c2806 WD |
464 | |
465 | /* this should pause enough for the chip to be happy */ | |
b56ddc63 | 466 | udelay (10); |
fe8c2806 WD |
467 | |
468 | /* Disable transmit and receive functionality */ | |
b56ddc63 WD |
469 | SMC_outw (RCR_CLEAR, RCR_REG); |
470 | SMC_outw (TCR_CLEAR, TCR_REG); | |
fe8c2806 WD |
471 | |
472 | /* set the control register */ | |
b56ddc63 WD |
473 | SMC_SELECT_BANK (1); |
474 | SMC_outw (CTL_DEFAULT, CTL_REG); | |
fe8c2806 WD |
475 | |
476 | /* Reset the MMU */ | |
b56ddc63 WD |
477 | SMC_SELECT_BANK (2); |
478 | smc_wait_mmu_release_complete (); | |
479 | SMC_outw (MC_RESET, MMU_CMD_REG); | |
480 | while (SMC_inw (MMU_CMD_REG) & MC_BUSY) | |
481 | udelay (1); /* Wait until not busy */ | |
fe8c2806 WD |
482 | |
483 | /* Note: It doesn't seem that waiting for the MMU busy is needed here, | |
484 | but this is a place where future chipsets _COULD_ break. Be wary | |
8bde7f77 | 485 | of issuing another MMU command right after this */ |
fe8c2806 WD |
486 | |
487 | /* Disable all interrupts */ | |
b56ddc63 | 488 | SMC_outb (0, IM_REG); |
fe8c2806 WD |
489 | } |
490 | ||
491 | /* | |
492 | . Function: smc_enable | |
493 | . Purpose: let the chip talk to the outside work | |
494 | . Method: | |
495 | . 1. Enable the transmitter | |
496 | . 2. Enable the receiver | |
497 | . 3. Enable interrupts | |
498 | */ | |
499 | static void smc_enable() | |
500 | { | |
f39748ae | 501 | PRINTK2("%s: smc_enable\n", SMC_DEV_NAME); |
fe8c2806 WD |
502 | SMC_SELECT_BANK( 0 ); |
503 | /* see the header file for options in TCR/RCR DEFAULT*/ | |
504 | SMC_outw( TCR_DEFAULT, TCR_REG ); | |
505 | SMC_outw( RCR_DEFAULT, RCR_REG ); | |
506 | ||
507 | /* clear MII_DIS */ | |
508 | /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ | |
509 | } | |
510 | ||
511 | /* | |
512 | . Function: smc_shutdown | |
513 | . Purpose: closes down the SMC91xxx chip. | |
514 | . Method: | |
515 | . 1. zero the interrupt mask | |
516 | . 2. clear the enable receive flag | |
517 | . 3. clear the enable xmit flags | |
518 | . | |
519 | . TODO: | |
520 | . (1) maybe utilize power down mode. | |
521 | . Why not yet? Because while the chip will go into power down mode, | |
522 | . the manual says that it will wake up in response to any I/O requests | |
42dfe7a1 | 523 | . in the register space. Empirical results do not show this working. |
fe8c2806 WD |
524 | */ |
525 | static void smc_shutdown() | |
526 | { | |
f39748ae | 527 | PRINTK2(CARDNAME ": smc_shutdown\n"); |
fe8c2806 WD |
528 | |
529 | /* no more interrupts for me */ | |
530 | SMC_SELECT_BANK( 2 ); | |
531 | SMC_outb( 0, IM_REG ); | |
532 | ||
533 | /* and tell the card to stay away from that nasty outside world */ | |
534 | SMC_SELECT_BANK( 0 ); | |
535 | SMC_outb( RCR_CLEAR, RCR_REG ); | |
536 | SMC_outb( TCR_CLEAR, TCR_REG ); | |
0afe519a WD |
537 | #ifdef SHARED_RESOURCES |
538 | swap_to(FLASH); | |
539 | #endif | |
fe8c2806 WD |
540 | } |
541 | ||
542 | ||
543 | /* | |
544 | . Function: smc_hardware_send_packet(struct net_device * ) | |
545 | . Purpose: | |
546 | . This sends the actual packet to the SMC9xxx chip. | |
547 | . | |
548 | . Algorithm: | |
42dfe7a1 | 549 | . First, see if a saved_skb is available. |
fe8c2806 WD |
550 | . ( this should NOT be called if there is no 'saved_skb' |
551 | . Now, find the packet number that the chip allocated | |
552 | . Point the data pointers at it in memory | |
553 | . Set the length word in the chip's memory | |
554 | . Dump the packet to chip memory | |
555 | . Check if a last byte is needed ( odd length packet ) | |
556 | . if so, set the control flag right | |
42dfe7a1 | 557 | . Tell the card to send it |
fe8c2806 | 558 | . Enable the transmit interrupt, so I know if it failed |
42dfe7a1 | 559 | . Free the kernel data if I actually sent it. |
fe8c2806 | 560 | */ |
b56ddc63 | 561 | static int smc_send_packet (volatile void *packet, int packet_length) |
fe8c2806 | 562 | { |
b56ddc63 WD |
563 | byte packet_no; |
564 | unsigned long ioaddr; | |
565 | byte *buf; | |
566 | int length; | |
567 | int numPages; | |
568 | int try = 0; | |
569 | int time_out; | |
570 | byte status; | |
518e2e1a WD |
571 | byte saved_pnr; |
572 | word saved_ptr; | |
fe8c2806 | 573 | |
518e2e1a | 574 | /* save PTR and PNR registers before manipulation */ |
b79a11cc | 575 | SMC_SELECT_BANK (2); |
518e2e1a WD |
576 | saved_pnr = SMC_inb( PN_REG ); |
577 | saved_ptr = SMC_inw( PTR_REG ); | |
fe8c2806 | 578 | |
f39748ae | 579 | PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME); |
fe8c2806 WD |
580 | |
581 | length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN; | |
582 | ||
583 | /* allocate memory | |
b56ddc63 WD |
584 | ** The MMU wants the number of pages to be the number of 256 bytes |
585 | ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) ) | |
586 | ** | |
587 | ** The 91C111 ignores the size bits, but the code is left intact | |
588 | ** for backwards and future compatibility. | |
589 | ** | |
590 | ** Pkt size for allocating is data length +6 (for additional status | |
591 | ** words, length and ctl!) | |
592 | ** | |
593 | ** If odd size then last byte is included in this header. | |
594 | */ | |
595 | numPages = ((length & 0xfffe) + 6); | |
596 | numPages >>= 8; /* Divide by 256 */ | |
597 | ||
598 | if (numPages > 7) { | |
599 | printf ("%s: Far too big packet error. \n", SMC_DEV_NAME); | |
fe8c2806 WD |
600 | return 0; |
601 | } | |
602 | ||
603 | /* now, try to allocate the memory */ | |
b56ddc63 WD |
604 | SMC_SELECT_BANK (2); |
605 | SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG); | |
fe8c2806 | 606 | |
dc7c9a1a | 607 | /* FIXME: the ALLOC_INT bit never gets set * |
42dfe7a1 WD |
608 | * so the following will always give a * |
609 | * memory allocation error. * | |
610 | * same code works in armboot though * | |
dc7c9a1a WD |
611 | * -ro |
612 | */ | |
613 | ||
fe8c2806 WD |
614 | again: |
615 | try++; | |
616 | time_out = MEMORY_WAIT_TIME; | |
617 | do { | |
b56ddc63 WD |
618 | status = SMC_inb (SMC91111_INT_REG); |
619 | if (status & IM_ALLOC_INT) { | |
fe8c2806 | 620 | /* acknowledge the interrupt */ |
b56ddc63 | 621 | SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG); |
8bde7f77 | 622 | break; |
fe8c2806 | 623 | } |
b56ddc63 WD |
624 | } while (--time_out); |
625 | ||
626 | if (!time_out) { | |
627 | PRINTK2 ("%s: memory allocation, try %d failed ...\n", | |
628 | SMC_DEV_NAME, try); | |
629 | if (try < SMC_ALLOC_MAX_TRY) | |
630 | goto again; | |
631 | else | |
632 | return 0; | |
fe8c2806 WD |
633 | } |
634 | ||
b56ddc63 WD |
635 | PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", |
636 | SMC_DEV_NAME, try); | |
fe8c2806 WD |
637 | |
638 | /* I can send the packet now.. */ | |
639 | ||
640 | ioaddr = SMC_BASE_ADDRESS; | |
641 | ||
b56ddc63 | 642 | buf = (byte *) packet; |
fe8c2806 WD |
643 | |
644 | /* If I get here, I _know_ there is a packet slot waiting for me */ | |
b56ddc63 WD |
645 | packet_no = SMC_inb (AR_REG); |
646 | if (packet_no & AR_FAILED) { | |
fe8c2806 | 647 | /* or isn't there? BAD CHIP! */ |
b56ddc63 | 648 | printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); |
fe8c2806 WD |
649 | return 0; |
650 | } | |
651 | ||
652 | /* we have a packet address, so tell the card to use it */ | |
1f6d4258 | 653 | #ifndef CONFIG_XAENIAX |
b56ddc63 | 654 | SMC_outb (packet_no, PN_REG); |
1f6d4258 WD |
655 | #else |
656 | /* On Xaeniax board, we can't use SMC_outb here because that way | |
657 | * the Allocate MMU command will end up written to the command register | |
658 | * as well, which will lead to a problem. | |
659 | */ | |
660 | SMC_outl (packet_no << 16, 0); | |
661 | #endif | |
b79a11cc WD |
662 | /* do not write new ptr value if Write data fifo not empty */ |
663 | while ( saved_ptr & PTR_NOTEMPTY ) | |
518e2e1a WD |
664 | printf ("Write data fifo not empty!\n"); |
665 | ||
fe8c2806 | 666 | /* point to the beginning of the packet */ |
b56ddc63 | 667 | SMC_outw (PTR_AUTOINC, PTR_REG); |
fe8c2806 | 668 | |
b56ddc63 WD |
669 | PRINTK3 ("%s: Trying to xmit packet of length %x\n", |
670 | SMC_DEV_NAME, length); | |
fe8c2806 WD |
671 | |
672 | #if SMC_DEBUG > 2 | |
b56ddc63 WD |
673 | printf ("Transmitting Packet\n"); |
674 | print_packet (buf, length); | |
fe8c2806 WD |
675 | #endif |
676 | ||
677 | /* send the packet length ( +6 for status, length and ctl byte ) | |
8bde7f77 | 678 | and the status word ( set to zeros ) */ |
fe8c2806 | 679 | #ifdef USE_32_BIT |
b56ddc63 | 680 | SMC_outl ((length + 6) << 16, SMC91111_DATA_REG); |
fe8c2806 | 681 | #else |
b56ddc63 WD |
682 | SMC_outw (0, SMC91111_DATA_REG); |
683 | /* send the packet length ( +6 for status words, length, and ctl */ | |
684 | SMC_outw ((length + 6), SMC91111_DATA_REG); | |
fe8c2806 WD |
685 | #endif |
686 | ||
687 | /* send the actual data | |
b56ddc63 WD |
688 | . I _think_ it's faster to send the longs first, and then |
689 | . mop up by sending the last word. It depends heavily | |
42dfe7a1 | 690 | . on alignment, at least on the 486. Maybe it would be |
b56ddc63 WD |
691 | . a good idea to check which is optimal? But that could take |
692 | . almost as much time as is saved? | |
693 | */ | |
fe8c2806 | 694 | #ifdef USE_32_BIT |
b56ddc63 | 695 | SMC_outsl (SMC91111_DATA_REG, buf, length >> 2); |
bb310d46 | 696 | #ifndef CONFIG_XAENIAX |
b56ddc63 WD |
697 | if (length & 0x2) |
698 | SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))), | |
699 | SMC91111_DATA_REG); | |
bb310d46 WD |
700 | #else |
701 | /* On XANEIAX, we can only use 32-bit writes, so we need to handle | |
702 | * unaligned tail part specially. The standard code doesn't work. | |
703 | */ | |
704 | if ((length & 3) == 3) { | |
705 | u16 * ptr = (u16*) &buf[length-3]; | |
706 | SMC_outl((*ptr) | ((0x2000 | buf[length-1]) << 16), | |
707 | SMC91111_DATA_REG); | |
708 | } else if ((length & 2) == 2) { | |
709 | u16 * ptr = (u16*) &buf[length-2]; | |
710 | SMC_outl(*ptr, SMC91111_DATA_REG); | |
711 | } else if (length & 1) { | |
712 | SMC_outl((0x2000 | buf[length-1]), SMC91111_DATA_REG); | |
713 | } else { | |
714 | SMC_outl(0, SMC91111_DATA_REG); | |
715 | } | |
716 | #endif | |
fe8c2806 | 717 | #else |
b56ddc63 | 718 | SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1); |
fe8c2806 WD |
719 | #endif /* USE_32_BIT */ |
720 | ||
bb310d46 | 721 | #ifndef CONFIG_XAENIAX |
42dfe7a1 | 722 | /* Send the last byte, if there is one. */ |
b56ddc63 WD |
723 | if ((length & 1) == 0) { |
724 | SMC_outw (0, SMC91111_DATA_REG); | |
fe8c2806 | 725 | } else { |
b56ddc63 | 726 | SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG); |
fe8c2806 | 727 | } |
bb310d46 | 728 | #endif |
fe8c2806 WD |
729 | |
730 | /* and let the chipset deal with it */ | |
b56ddc63 | 731 | SMC_outw (MC_ENQUEUE, MMU_CMD_REG); |
fe8c2806 WD |
732 | |
733 | /* poll for TX INT */ | |
518e2e1a WD |
734 | /* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */ |
735 | /* poll for TX_EMPTY INT - autorelease enabled */ | |
736 | if (poll4int(IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { | |
fe8c2806 | 737 | /* sending failed */ |
b56ddc63 | 738 | PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); |
fe8c2806 WD |
739 | |
740 | /* release packet */ | |
518e2e1a | 741 | /* no need to release, MMU does that now */ |
1f6d4258 WD |
742 | #ifdef CONFIG_XAENIAX |
743 | SMC_outw (MC_FREEPKT, MMU_CMD_REG); | |
744 | #endif | |
fe8c2806 | 745 | |
8bde7f77 | 746 | /* wait for MMU getting ready (low) */ |
b56ddc63 WD |
747 | while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { |
748 | udelay (10); | |
8bde7f77 | 749 | } |
fe8c2806 | 750 | |
b56ddc63 | 751 | PRINTK2 ("MMU ready\n"); |
fe8c2806 WD |
752 | |
753 | ||
754 | return 0; | |
755 | } else { | |
756 | /* ack. int */ | |
518e2e1a WD |
757 | SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG); |
758 | /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ | |
b56ddc63 WD |
759 | PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, |
760 | length); | |
fe8c2806 WD |
761 | |
762 | /* release packet */ | |
518e2e1a | 763 | /* no need to release, MMU does that now */ |
1f6d4258 WD |
764 | #ifdef CONFIG_XAENIAX |
765 | SMC_outw (MC_FREEPKT, MMU_CMD_REG); | |
766 | #endif | |
fe8c2806 | 767 | |
8bde7f77 | 768 | /* wait for MMU getting ready (low) */ |
b56ddc63 WD |
769 | while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { |
770 | udelay (10); | |
8bde7f77 | 771 | } |
fe8c2806 | 772 | |
b56ddc63 | 773 | PRINTK2 ("MMU ready\n"); |
fe8c2806 WD |
774 | |
775 | ||
776 | } | |
777 | ||
518e2e1a | 778 | /* restore previously saved registers */ |
1f6d4258 | 779 | #ifndef CONFIG_XAENIAX |
518e2e1a | 780 | SMC_outb( saved_pnr, PN_REG ); |
1f6d4258 WD |
781 | #else |
782 | /* On Xaeniax board, we can't use SMC_outb here because that way | |
783 | * the Allocate MMU command will end up written to the command register | |
784 | * as well, which will lead to a problem. | |
785 | */ | |
786 | SMC_outl(saved_pnr << 16, 0); | |
787 | #endif | |
518e2e1a WD |
788 | SMC_outw( saved_ptr, PTR_REG ); |
789 | ||
fe8c2806 WD |
790 | return length; |
791 | } | |
792 | ||
793 | /*------------------------------------------------------------------------- | |
794 | | | |
795 | | smc_destructor( struct net_device * dev ) | |
796 | | Input parameters: | |
797 | | dev, pointer to the device structure | |
798 | | | |
799 | | Output: | |
800 | | None. | |
801 | | | |
802 | --------------------------------------------------------------------------- | |
803 | */ | |
804 | void smc_destructor() | |
805 | { | |
f39748ae | 806 | PRINTK2(CARDNAME ": smc_destructor\n"); |
fe8c2806 WD |
807 | } |
808 | ||
809 | ||
810 | /* | |
811 | * Open and Initialize the board | |
812 | * | |
813 | * Set up everything, reset the card, etc .. | |
814 | * | |
815 | */ | |
b56ddc63 | 816 | static int smc_open (bd_t * bd) |
fe8c2806 | 817 | { |
b56ddc63 | 818 | int i, err; |
fe8c2806 | 819 | |
f39748ae | 820 | PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME); |
fe8c2806 WD |
821 | |
822 | /* reset the hardware */ | |
b56ddc63 WD |
823 | smc_reset (); |
824 | smc_enable (); | |
fe8c2806 WD |
825 | |
826 | /* Configure the PHY */ | |
827 | #ifndef CONFIG_SMC91111_EXT_PHY | |
b56ddc63 | 828 | smc_phy_configure (); |
fe8c2806 WD |
829 | #endif |
830 | ||
fe8c2806 WD |
831 | /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ |
832 | /* SMC_SELECT_BANK(0); */ | |
833 | /* SMC_outw(0, RPC_REG); */ | |
b56ddc63 | 834 | SMC_SELECT_BANK (1); |
487778b7 | 835 | |
b56ddc63 WD |
836 | err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */ |
837 | if (err < 0) { | |
42dfe7a1 | 838 | memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set */ |
b56ddc63 WD |
839 | return (-1); /* upper code ignores this, but NOT bi_enetaddr */ |
840 | } | |
fe8c2806 | 841 | #ifdef USE_32_BIT |
b56ddc63 | 842 | for (i = 0; i < 6; i += 2) { |
fe8c2806 WD |
843 | word address; |
844 | ||
b56ddc63 WD |
845 | address = smc_mac_addr[i + 1] << 8; |
846 | address |= smc_mac_addr[i]; | |
39539887 | 847 | SMC_outw (address, (ADDR0_REG + i)); |
fe8c2806 WD |
848 | } |
849 | #else | |
b56ddc63 | 850 | for (i = 0; i < 6; i++) |
39539887 | 851 | SMC_outb (smc_mac_addr[i], (ADDR0_REG + i)); |
fe8c2806 WD |
852 | #endif |
853 | ||
854 | return 0; | |
855 | } | |
856 | ||
fe8c2806 WD |
857 | /*------------------------------------------------------------- |
858 | . | |
859 | . smc_rcv - receive a packet from the card | |
860 | . | |
861 | . There is ( at least ) a packet waiting to be read from | |
862 | . chip-memory. | |
863 | . | |
864 | . o Read the status | |
865 | . o If an error, record it | |
866 | . o otherwise, read in the packet | |
867 | -------------------------------------------------------------- | |
868 | */ | |
869 | static int smc_rcv() | |
870 | { | |
42dfe7a1 | 871 | int packet_number; |
fe8c2806 WD |
872 | word status; |
873 | word packet_length; | |
42dfe7a1 | 874 | int is_error = 0; |
fe8c2806 WD |
875 | #ifdef USE_32_BIT |
876 | dword stat_len; | |
877 | #endif | |
518e2e1a WD |
878 | byte saved_pnr; |
879 | word saved_ptr; | |
fe8c2806 | 880 | |
fe8c2806 | 881 | SMC_SELECT_BANK(2); |
518e2e1a WD |
882 | /* save PTR and PTR registers */ |
883 | saved_pnr = SMC_inb( PN_REG ); | |
884 | saved_ptr = SMC_inw( PTR_REG ); | |
885 | ||
fe8c2806 WD |
886 | packet_number = SMC_inw( RXFIFO_REG ); |
887 | ||
888 | if ( packet_number & RXFIFO_REMPTY ) { | |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
f39748ae | 893 | PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); |
fe8c2806 WD |
894 | /* start reading from the start of the packet */ |
895 | SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); | |
896 | ||
897 | /* First two words are status and packet_length */ | |
898 | #ifdef USE_32_BIT | |
899 | stat_len = SMC_inl(SMC91111_DATA_REG); | |
900 | status = stat_len & 0xffff; | |
901 | packet_length = stat_len >> 16; | |
902 | #else | |
42dfe7a1 WD |
903 | status = SMC_inw( SMC91111_DATA_REG ); |
904 | packet_length = SMC_inw( SMC91111_DATA_REG ); | |
fe8c2806 WD |
905 | #endif |
906 | ||
907 | packet_length &= 0x07ff; /* mask off top bits */ | |
908 | ||
909 | PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length ); | |
910 | ||
911 | if ( !(status & RS_ERRORS ) ){ | |
912 | /* Adjust for having already read the first two words */ | |
913 | packet_length -= 4; /*4; */ | |
914 | ||
915 | ||
fe8c2806 WD |
916 | /* set odd length for bug in LAN91C111, */ |
917 | /* which never sets RS_ODDFRAME */ | |
918 | /* TODO ? */ | |
919 | ||
920 | ||
921 | #ifdef USE_32_BIT | |
922 | PRINTK3(" Reading %d dwords (and %d bytes) \n", | |
923 | packet_length >> 2, packet_length & 3 ); | |
924 | /* QUESTION: Like in the TX routine, do I want | |
925 | to send the DWORDs or the bytes first, or some | |
926 | mixture. A mixture might improve already slow PIO | |
42dfe7a1 | 927 | performance */ |
fe8c2806 WD |
928 | SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 ); |
929 | /* read the left over bytes */ | |
930 | if (packet_length & 3) { | |
931 | int i; | |
932 | ||
699b13a6 | 933 | byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3)); |
fe8c2806 WD |
934 | dword leftover = SMC_inl(SMC91111_DATA_REG); |
935 | for (i=0; i<(packet_length & 3); i++) | |
936 | *tail++ = (byte) (leftover >> (8*i)) & 0xff; | |
937 | } | |
938 | #else | |
939 | PRINTK3(" Reading %d words and %d byte(s) \n", | |
940 | (packet_length >> 1 ), packet_length & 1 ); | |
941 | SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1); | |
942 | ||
943 | #endif /* USE_32_BIT */ | |
944 | ||
945 | #if SMC_DEBUG > 2 | |
946 | printf("Receiving Packet\n"); | |
947 | print_packet( NetRxPackets[0], packet_length ); | |
948 | #endif | |
949 | } else { | |
950 | /* error ... */ | |
951 | /* TODO ? */ | |
952 | is_error = 1; | |
953 | } | |
954 | ||
955 | while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY ) | |
956 | udelay(1); /* Wait until not busy */ | |
957 | ||
958 | /* error or good, tell the card to get rid of this packet */ | |
959 | SMC_outw( MC_RELEASE, MMU_CMD_REG ); | |
960 | ||
961 | while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY ) | |
962 | udelay(1); /* Wait until not busy */ | |
963 | ||
518e2e1a | 964 | /* restore saved registers */ |
1f6d4258 | 965 | #ifndef CONFIG_XAENIAX |
518e2e1a | 966 | SMC_outb( saved_pnr, PN_REG ); |
1f6d4258 WD |
967 | #else |
968 | /* On Xaeniax board, we can't use SMC_outb here because that way | |
969 | * the Allocate MMU command will end up written to the command register | |
970 | * as well, which will lead to a problem. | |
971 | */ | |
972 | SMC_outl( saved_pnr << 16, 0); | |
973 | #endif | |
518e2e1a WD |
974 | SMC_outw( saved_ptr, PTR_REG ); |
975 | ||
fe8c2806 WD |
976 | if (!is_error) { |
977 | /* Pass the packet up to the protocol layers. */ | |
978 | NetReceive(NetRxPackets[0], packet_length); | |
979 | return packet_length; | |
980 | } else { | |
981 | return 0; | |
982 | } | |
983 | ||
984 | } | |
985 | ||
986 | ||
fe8c2806 WD |
987 | /*---------------------------------------------------- |
988 | . smc_close | |
989 | . | |
990 | . this makes the board clean up everything that it can | |
42dfe7a1 | 991 | . and not talk to the outside world. Caused by |
fe8c2806 WD |
992 | . an 'ifconfig ethX down' |
993 | . | |
994 | -----------------------------------------------------*/ | |
995 | static int smc_close() | |
996 | { | |
f39748ae | 997 | PRINTK2("%s: smc_close\n", SMC_DEV_NAME); |
fe8c2806 WD |
998 | |
999 | /* clear everything */ | |
1000 | smc_shutdown(); | |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
1005 | ||
1006 | #if 0 | |
1007 | /*------------------------------------------------------------ | |
1008 | . Modify a bit in the LAN91C111 register set | |
1009 | .-------------------------------------------------------------*/ | |
1010 | static word smc_modify_regbit(int bank, int ioaddr, int reg, | |
1011 | unsigned int bit, int val) | |
1012 | { | |
1013 | word regval; | |
1014 | ||
1015 | SMC_SELECT_BANK( bank ); | |
1016 | ||
1017 | regval = SMC_inw( reg ); | |
1018 | if (val) | |
1019 | regval |= bit; | |
1020 | else | |
1021 | regval &= ~bit; | |
1022 | ||
1023 | SMC_outw( regval, 0 ); | |
1024 | return(regval); | |
1025 | } | |
1026 | ||
1027 | ||
1028 | /*------------------------------------------------------------ | |
1029 | . Retrieve a bit in the LAN91C111 register set | |
1030 | .-------------------------------------------------------------*/ | |
1031 | static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit) | |
1032 | { | |
1033 | SMC_SELECT_BANK( bank ); | |
1034 | if ( SMC_inw( reg ) & bit) | |
1035 | return(1); | |
1036 | else | |
1037 | return(0); | |
1038 | } | |
1039 | ||
1040 | ||
1041 | /*------------------------------------------------------------ | |
1042 | . Modify a LAN91C111 register (word access only) | |
1043 | .-------------------------------------------------------------*/ | |
1044 | static void smc_modify_reg(int bank, int ioaddr, int reg, word val) | |
1045 | { | |
1046 | SMC_SELECT_BANK( bank ); | |
1047 | SMC_outw( val, reg ); | |
1048 | } | |
1049 | ||
1050 | ||
1051 | /*------------------------------------------------------------ | |
1052 | . Retrieve a LAN91C111 register (word access only) | |
1053 | .-------------------------------------------------------------*/ | |
1054 | static int smc_get_reg(int bank, int ioaddr, int reg) | |
1055 | { | |
1056 | SMC_SELECT_BANK( bank ); | |
1057 | return(SMC_inw( reg )); | |
1058 | } | |
1059 | ||
1060 | #endif /* 0 */ | |
1061 | ||
1062 | /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */ | |
1063 | ||
1064 | #if (SMC_DEBUG > 2 ) | |
1065 | ||
1066 | /*------------------------------------------------------------ | |
1067 | . Debugging function for viewing MII Management serial bitstream | |
1068 | .-------------------------------------------------------------*/ | |
b56ddc63 | 1069 | static void smc_dump_mii_stream (byte * bits, int size) |
fe8c2806 WD |
1070 | { |
1071 | int i; | |
1072 | ||
b56ddc63 WD |
1073 | printf ("BIT#:"); |
1074 | for (i = 0; i < size; ++i) { | |
1075 | printf ("%d", i % 10); | |
1076 | } | |
fe8c2806 | 1077 | |
b56ddc63 WD |
1078 | printf ("\nMDOE:"); |
1079 | for (i = 0; i < size; ++i) { | |
fe8c2806 | 1080 | if (bits[i] & MII_MDOE) |
b56ddc63 | 1081 | printf ("1"); |
fe8c2806 | 1082 | else |
b56ddc63 WD |
1083 | printf ("0"); |
1084 | } | |
fe8c2806 | 1085 | |
b56ddc63 WD |
1086 | printf ("\nMDO :"); |
1087 | for (i = 0; i < size; ++i) { | |
fe8c2806 | 1088 | if (bits[i] & MII_MDO) |
b56ddc63 | 1089 | printf ("1"); |
fe8c2806 | 1090 | else |
b56ddc63 WD |
1091 | printf ("0"); |
1092 | } | |
fe8c2806 | 1093 | |
b56ddc63 WD |
1094 | printf ("\nMDI :"); |
1095 | for (i = 0; i < size; ++i) { | |
fe8c2806 | 1096 | if (bits[i] & MII_MDI) |
b56ddc63 | 1097 | printf ("1"); |
fe8c2806 | 1098 | else |
b56ddc63 WD |
1099 | printf ("0"); |
1100 | } | |
fe8c2806 | 1101 | |
b56ddc63 | 1102 | printf ("\n"); |
fe8c2806 WD |
1103 | } |
1104 | #endif | |
1105 | ||
1106 | /*------------------------------------------------------------ | |
1107 | . Reads a register from the MII Management serial interface | |
1108 | .-------------------------------------------------------------*/ | |
1109 | #ifndef CONFIG_SMC91111_EXT_PHY | |
b56ddc63 | 1110 | static word smc_read_phy_register (byte phyreg) |
fe8c2806 WD |
1111 | { |
1112 | int oldBank; | |
1113 | int i; | |
1114 | byte mask; | |
1115 | word mii_reg; | |
1116 | byte bits[64]; | |
1117 | int clk_idx = 0; | |
1118 | int input_idx; | |
1119 | word phydata; | |
1120 | byte phyaddr = SMC_PHY_ADDR; | |
1121 | ||
1122 | /* 32 consecutive ones on MDO to establish sync */ | |
1123 | for (i = 0; i < 32; ++i) | |
1124 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1125 | ||
1126 | /* Start code <01> */ | |
1127 | bits[clk_idx++] = MII_MDOE; | |
1128 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1129 | ||
1130 | /* Read command <10> */ | |
1131 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1132 | bits[clk_idx++] = MII_MDOE; | |
1133 | ||
1134 | /* Output the PHY address, msb first */ | |
b56ddc63 WD |
1135 | mask = (byte) 0x10; |
1136 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
1137 | if (phyaddr & mask) |
1138 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1139 | else | |
1140 | bits[clk_idx++] = MII_MDOE; | |
1141 | ||
1142 | /* Shift to next lowest bit */ | |
1143 | mask >>= 1; | |
b56ddc63 | 1144 | } |
fe8c2806 WD |
1145 | |
1146 | /* Output the phy register number, msb first */ | |
b56ddc63 WD |
1147 | mask = (byte) 0x10; |
1148 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
1149 | if (phyreg & mask) |
1150 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1151 | else | |
1152 | bits[clk_idx++] = MII_MDOE; | |
1153 | ||
1154 | /* Shift to next lowest bit */ | |
1155 | mask >>= 1; | |
b56ddc63 | 1156 | } |
fe8c2806 WD |
1157 | |
1158 | /* Tristate and turnaround (2 bit times) */ | |
1159 | bits[clk_idx++] = 0; | |
1160 | /*bits[clk_idx++] = 0; */ | |
1161 | ||
1162 | /* Input starts at this bit time */ | |
1163 | input_idx = clk_idx; | |
1164 | ||
1165 | /* Will input 16 bits */ | |
1166 | for (i = 0; i < 16; ++i) | |
1167 | bits[clk_idx++] = 0; | |
1168 | ||
1169 | /* Final clock bit */ | |
1170 | bits[clk_idx++] = 0; | |
1171 | ||
1172 | /* Save the current bank */ | |
b56ddc63 | 1173 | oldBank = SMC_inw (BANK_SELECT); |
fe8c2806 WD |
1174 | |
1175 | /* Select bank 3 */ | |
b56ddc63 | 1176 | SMC_SELECT_BANK (3); |
fe8c2806 WD |
1177 | |
1178 | /* Get the current MII register value */ | |
b56ddc63 | 1179 | mii_reg = SMC_inw (MII_REG); |
fe8c2806 WD |
1180 | |
1181 | /* Turn off all MII Interface bits */ | |
b56ddc63 | 1182 | mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); |
fe8c2806 WD |
1183 | |
1184 | /* Clock all 64 cycles */ | |
b56ddc63 | 1185 | for (i = 0; i < sizeof bits; ++i) { |
fe8c2806 | 1186 | /* Clock Low - output data */ |
b56ddc63 WD |
1187 | SMC_outw (mii_reg | bits[i], MII_REG); |
1188 | udelay (SMC_PHY_CLOCK_DELAY); | |
fe8c2806 WD |
1189 | |
1190 | ||
1191 | /* Clock Hi - input data */ | |
b56ddc63 WD |
1192 | SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG); |
1193 | udelay (SMC_PHY_CLOCK_DELAY); | |
1194 | bits[i] |= SMC_inw (MII_REG) & MII_MDI; | |
1195 | } | |
fe8c2806 WD |
1196 | |
1197 | /* Return to idle state */ | |
1198 | /* Set clock to low, data to low, and output tristated */ | |
b56ddc63 WD |
1199 | SMC_outw (mii_reg, MII_REG); |
1200 | udelay (SMC_PHY_CLOCK_DELAY); | |
fe8c2806 WD |
1201 | |
1202 | /* Restore original bank select */ | |
b56ddc63 | 1203 | SMC_SELECT_BANK (oldBank); |
fe8c2806 WD |
1204 | |
1205 | /* Recover input data */ | |
1206 | phydata = 0; | |
b56ddc63 | 1207 | for (i = 0; i < 16; ++i) { |
fe8c2806 WD |
1208 | phydata <<= 1; |
1209 | ||
1210 | if (bits[input_idx++] & MII_MDI) | |
1211 | phydata |= 0x0001; | |
b56ddc63 | 1212 | } |
fe8c2806 WD |
1213 | |
1214 | #if (SMC_DEBUG > 2 ) | |
b56ddc63 | 1215 | printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", |
fe8c2806 | 1216 | phyaddr, phyreg, phydata); |
b56ddc63 | 1217 | smc_dump_mii_stream (bits, sizeof bits); |
fe8c2806 WD |
1218 | #endif |
1219 | ||
b56ddc63 | 1220 | return (phydata); |
fe8c2806 WD |
1221 | } |
1222 | ||
1223 | ||
1224 | /*------------------------------------------------------------ | |
1225 | . Writes a register to the MII Management serial interface | |
1226 | .-------------------------------------------------------------*/ | |
b56ddc63 | 1227 | static void smc_write_phy_register (byte phyreg, word phydata) |
fe8c2806 WD |
1228 | { |
1229 | int oldBank; | |
1230 | int i; | |
1231 | word mask; | |
1232 | word mii_reg; | |
1233 | byte bits[65]; | |
1234 | int clk_idx = 0; | |
1235 | byte phyaddr = SMC_PHY_ADDR; | |
1236 | ||
1237 | /* 32 consecutive ones on MDO to establish sync */ | |
1238 | for (i = 0; i < 32; ++i) | |
1239 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1240 | ||
1241 | /* Start code <01> */ | |
1242 | bits[clk_idx++] = MII_MDOE; | |
1243 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1244 | ||
1245 | /* Write command <01> */ | |
1246 | bits[clk_idx++] = MII_MDOE; | |
1247 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1248 | ||
1249 | /* Output the PHY address, msb first */ | |
b56ddc63 WD |
1250 | mask = (byte) 0x10; |
1251 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
1252 | if (phyaddr & mask) |
1253 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1254 | else | |
1255 | bits[clk_idx++] = MII_MDOE; | |
1256 | ||
1257 | /* Shift to next lowest bit */ | |
1258 | mask >>= 1; | |
b56ddc63 | 1259 | } |
fe8c2806 WD |
1260 | |
1261 | /* Output the phy register number, msb first */ | |
b56ddc63 WD |
1262 | mask = (byte) 0x10; |
1263 | for (i = 0; i < 5; ++i) { | |
fe8c2806 WD |
1264 | if (phyreg & mask) |
1265 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1266 | else | |
1267 | bits[clk_idx++] = MII_MDOE; | |
1268 | ||
1269 | /* Shift to next lowest bit */ | |
1270 | mask >>= 1; | |
b56ddc63 | 1271 | } |
fe8c2806 WD |
1272 | |
1273 | /* Tristate and turnaround (2 bit times) */ | |
1274 | bits[clk_idx++] = 0; | |
1275 | bits[clk_idx++] = 0; | |
1276 | ||
1277 | /* Write out 16 bits of data, msb first */ | |
1278 | mask = 0x8000; | |
b56ddc63 | 1279 | for (i = 0; i < 16; ++i) { |
fe8c2806 WD |
1280 | if (phydata & mask) |
1281 | bits[clk_idx++] = MII_MDOE | MII_MDO; | |
1282 | else | |
1283 | bits[clk_idx++] = MII_MDOE; | |
1284 | ||
1285 | /* Shift to next lowest bit */ | |
1286 | mask >>= 1; | |
b56ddc63 | 1287 | } |
fe8c2806 WD |
1288 | |
1289 | /* Final clock bit (tristate) */ | |
1290 | bits[clk_idx++] = 0; | |
1291 | ||
1292 | /* Save the current bank */ | |
b56ddc63 | 1293 | oldBank = SMC_inw (BANK_SELECT); |
fe8c2806 WD |
1294 | |
1295 | /* Select bank 3 */ | |
b56ddc63 | 1296 | SMC_SELECT_BANK (3); |
fe8c2806 WD |
1297 | |
1298 | /* Get the current MII register value */ | |
b56ddc63 | 1299 | mii_reg = SMC_inw (MII_REG); |
fe8c2806 WD |
1300 | |
1301 | /* Turn off all MII Interface bits */ | |
b56ddc63 | 1302 | mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); |
fe8c2806 WD |
1303 | |
1304 | /* Clock all cycles */ | |
b56ddc63 | 1305 | for (i = 0; i < sizeof bits; ++i) { |
fe8c2806 | 1306 | /* Clock Low - output data */ |
b56ddc63 WD |
1307 | SMC_outw (mii_reg | bits[i], MII_REG); |
1308 | udelay (SMC_PHY_CLOCK_DELAY); | |
fe8c2806 WD |
1309 | |
1310 | ||
1311 | /* Clock Hi - input data */ | |
b56ddc63 WD |
1312 | SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG); |
1313 | udelay (SMC_PHY_CLOCK_DELAY); | |
1314 | bits[i] |= SMC_inw (MII_REG) & MII_MDI; | |
1315 | } | |
fe8c2806 WD |
1316 | |
1317 | /* Return to idle state */ | |
1318 | /* Set clock to low, data to low, and output tristated */ | |
b56ddc63 WD |
1319 | SMC_outw (mii_reg, MII_REG); |
1320 | udelay (SMC_PHY_CLOCK_DELAY); | |
fe8c2806 WD |
1321 | |
1322 | /* Restore original bank select */ | |
b56ddc63 | 1323 | SMC_SELECT_BANK (oldBank); |
fe8c2806 WD |
1324 | |
1325 | #if (SMC_DEBUG > 2 ) | |
b56ddc63 | 1326 | printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", |
fe8c2806 | 1327 | phyaddr, phyreg, phydata); |
b56ddc63 | 1328 | smc_dump_mii_stream (bits, sizeof bits); |
fe8c2806 WD |
1329 | #endif |
1330 | } | |
1331 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
1332 | ||
1333 | ||
fe8c2806 WD |
1334 | /*------------------------------------------------------------ |
1335 | . Waits the specified number of milliseconds - kernel friendly | |
1336 | .-------------------------------------------------------------*/ | |
1337 | #ifndef CONFIG_SMC91111_EXT_PHY | |
1338 | static void smc_wait_ms(unsigned int ms) | |
1339 | { | |
1340 | udelay(ms*1000); | |
1341 | } | |
1342 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
1343 | ||
1344 | ||
fe8c2806 WD |
1345 | /*------------------------------------------------------------ |
1346 | . Configures the specified PHY using Autonegotiation. Calls | |
1347 | . smc_phy_fixed() if the user has requested a certain config. | |
1348 | .-------------------------------------------------------------*/ | |
1349 | #ifndef CONFIG_SMC91111_EXT_PHY | |
b56ddc63 | 1350 | static void smc_phy_configure () |
fe8c2806 WD |
1351 | { |
1352 | int timeout; | |
1353 | byte phyaddr; | |
b56ddc63 WD |
1354 | word my_phy_caps; /* My PHY capabilities */ |
1355 | word my_ad_caps; /* My Advertised capabilities */ | |
1356 | word status = 0; /*;my status = 0 */ | |
fe8c2806 WD |
1357 | int failed = 0; |
1358 | ||
f39748ae | 1359 | PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME); |
fe8c2806 WD |
1360 | |
1361 | ||
fe8c2806 WD |
1362 | /* Get the detected phy address */ |
1363 | phyaddr = SMC_PHY_ADDR; | |
1364 | ||
1365 | /* Reset the PHY, setting all other bits to zero */ | |
b56ddc63 | 1366 | smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST); |
fe8c2806 WD |
1367 | |
1368 | /* Wait for the reset to complete, or time out */ | |
b56ddc63 WD |
1369 | timeout = 6; /* Wait up to 3 seconds */ |
1370 | while (timeout--) { | |
1371 | if (!(smc_read_phy_register (PHY_CNTL_REG) | |
1372 | & PHY_CNTL_RST)) { | |
fe8c2806 WD |
1373 | /* reset complete */ |
1374 | break; | |
fe8c2806 WD |
1375 | } |
1376 | ||
b56ddc63 WD |
1377 | smc_wait_ms (500); /* wait 500 millisecs */ |
1378 | } | |
1379 | ||
1380 | if (timeout < 1) { | |
1381 | printf ("%s:PHY reset timed out\n", SMC_DEV_NAME); | |
fe8c2806 | 1382 | goto smc_phy_configure_exit; |
b56ddc63 | 1383 | } |
fe8c2806 WD |
1384 | |
1385 | /* Read PHY Register 18, Status Output */ | |
1386 | /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */ | |
1387 | ||
1388 | /* Enable PHY Interrupts (for register 18) */ | |
1389 | /* Interrupts listed here are disabled */ | |
8bf3b005 | 1390 | smc_write_phy_register (PHY_MASK_REG, 0xffff); |
fe8c2806 WD |
1391 | |
1392 | /* Configure the Receive/Phy Control register */ | |
b56ddc63 WD |
1393 | SMC_SELECT_BANK (0); |
1394 | SMC_outw (RPC_DEFAULT, RPC_REG); | |
fe8c2806 WD |
1395 | |
1396 | /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ | |
b56ddc63 WD |
1397 | my_phy_caps = smc_read_phy_register (PHY_STAT_REG); |
1398 | my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */ | |
fe8c2806 WD |
1399 | |
1400 | if (my_phy_caps & PHY_STAT_CAP_T4) | |
1401 | my_ad_caps |= PHY_AD_T4; | |
1402 | ||
1403 | if (my_phy_caps & PHY_STAT_CAP_TXF) | |
1404 | my_ad_caps |= PHY_AD_TX_FDX; | |
1405 | ||
1406 | if (my_phy_caps & PHY_STAT_CAP_TXH) | |
1407 | my_ad_caps |= PHY_AD_TX_HDX; | |
1408 | ||
1409 | if (my_phy_caps & PHY_STAT_CAP_TF) | |
1410 | my_ad_caps |= PHY_AD_10_FDX; | |
1411 | ||
1412 | if (my_phy_caps & PHY_STAT_CAP_TH) | |
1413 | my_ad_caps |= PHY_AD_10_HDX; | |
1414 | ||
1415 | /* Update our Auto-Neg Advertisement Register */ | |
b56ddc63 | 1416 | smc_write_phy_register (PHY_AD_REG, my_ad_caps); |
fe8c2806 | 1417 | |
518e2e1a WD |
1418 | /* Read the register back. Without this, it appears that when */ |
1419 | /* auto-negotiation is restarted, sometimes it isn't ready and */ | |
1420 | /* the link does not come up. */ | |
1421 | smc_read_phy_register(PHY_AD_REG); | |
1422 | ||
f39748ae WD |
1423 | PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps); |
1424 | PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps); | |
fe8c2806 WD |
1425 | |
1426 | /* Restart auto-negotiation process in order to advertise my caps */ | |
b56ddc63 WD |
1427 | smc_write_phy_register (PHY_CNTL_REG, |
1428 | PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST); | |
fe8c2806 WD |
1429 | |
1430 | /* Wait for the auto-negotiation to complete. This may take from */ | |
1431 | /* 2 to 3 seconds. */ | |
1432 | /* Wait for the reset to complete, or time out */ | |
f39748ae | 1433 | timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2; |
b56ddc63 | 1434 | while (timeout--) { |
f39748ae | 1435 | |
b56ddc63 WD |
1436 | status = smc_read_phy_register (PHY_STAT_REG); |
1437 | if (status & PHY_STAT_ANEG_ACK) { | |
fe8c2806 WD |
1438 | /* auto-negotiate complete */ |
1439 | break; | |
b56ddc63 | 1440 | } |
fe8c2806 | 1441 | |
b56ddc63 | 1442 | smc_wait_ms (500); /* wait 500 millisecs */ |
fe8c2806 WD |
1443 | |
1444 | /* Restart auto-negotiation if remote fault */ | |
b56ddc63 | 1445 | if (status & PHY_STAT_REM_FLT) { |
f39748ae | 1446 | printf ("%s: PHY remote fault detected\n", |
b56ddc63 | 1447 | SMC_DEV_NAME); |
fe8c2806 WD |
1448 | |
1449 | /* Restart auto-negotiation */ | |
f39748ae | 1450 | printf ("%s: PHY restarting auto-negotiation\n", |
fe8c2806 | 1451 | SMC_DEV_NAME); |
b56ddc63 WD |
1452 | smc_write_phy_register (PHY_CNTL_REG, |
1453 | PHY_CNTL_ANEG_EN | | |
1454 | PHY_CNTL_ANEG_RST | | |
1455 | PHY_CNTL_SPEED | | |
1456 | PHY_CNTL_DPLX); | |
fe8c2806 | 1457 | } |
b56ddc63 | 1458 | } |
fe8c2806 | 1459 | |
b56ddc63 | 1460 | if (timeout < 1) { |
f39748ae | 1461 | printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME); |
fe8c2806 | 1462 | failed = 1; |
b56ddc63 | 1463 | } |
fe8c2806 WD |
1464 | |
1465 | /* Fail if we detected an auto-negotiate remote fault */ | |
b56ddc63 | 1466 | if (status & PHY_STAT_REM_FLT) { |
f39748ae | 1467 | printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME); |
fe8c2806 | 1468 | failed = 1; |
b56ddc63 | 1469 | } |
fe8c2806 WD |
1470 | |
1471 | /* Re-Configure the Receive/Phy Control register */ | |
b56ddc63 | 1472 | SMC_outw (RPC_DEFAULT, RPC_REG); |
fe8c2806 | 1473 | |
26238132 | 1474 | smc_phy_configure_exit: ; |
fe8c2806 WD |
1475 | |
1476 | } | |
1477 | #endif /* !CONFIG_SMC91111_EXT_PHY */ | |
1478 | ||
1479 | ||
1480 | #if SMC_DEBUG > 2 | |
1481 | static void print_packet( byte * buf, int length ) | |
1482 | { | |
8bde7f77 WD |
1483 | int i; |
1484 | int remainder; | |
1485 | int lines; | |
fe8c2806 | 1486 | |
8bde7f77 | 1487 | printf("Packet of length %d \n", length ); |
fe8c2806 WD |
1488 | |
1489 | #if SMC_DEBUG > 3 | |
8bde7f77 WD |
1490 | lines = length / 16; |
1491 | remainder = length % 16; | |
1492 | ||
1493 | for ( i = 0; i < lines ; i ++ ) { | |
1494 | int cur; | |
1495 | ||
1496 | for ( cur = 0; cur < 8; cur ++ ) { | |
1497 | byte a, b; | |
1498 | ||
1499 | a = *(buf ++ ); | |
1500 | b = *(buf ++ ); | |
1501 | printf("%02x%02x ", a, b ); | |
1502 | } | |
1503 | printf("\n"); | |
1504 | } | |
1505 | for ( i = 0; i < remainder/2 ; i++ ) { | |
1506 | byte a, b; | |
1507 | ||
1508 | a = *(buf ++ ); | |
1509 | b = *(buf ++ ); | |
1510 | printf("%02x%02x ", a, b ); | |
1511 | } | |
1512 | printf("\n"); | |
fe8c2806 | 1513 | #endif |
fe8c2806 WD |
1514 | } |
1515 | #endif | |
1516 | ||
1517 | int eth_init(bd_t *bd) { | |
0afe519a WD |
1518 | #ifdef SHARED_RESOURCES |
1519 | swap_to(ETHERNET); | |
1520 | #endif | |
0b97ab14 | 1521 | return (smc_open(bd)); |
fe8c2806 WD |
1522 | } |
1523 | ||
1524 | void eth_halt() { | |
1525 | smc_close(); | |
1526 | } | |
1527 | ||
1528 | int eth_rx() { | |
1529 | return smc_rcv(); | |
1530 | } | |
1531 | ||
1532 | int eth_send(volatile void *packet, int length) { | |
1533 | return smc_send_packet(packet, length); | |
1534 | } | |
1535 | ||
b56ddc63 | 1536 | int smc_get_ethaddr (bd_t * bd) |
0b97ab14 | 1537 | { |
b56ddc63 | 1538 | int env_size, rom_valid, env_present = 0, reg; |
ebd0a0ae | 1539 | char *s = NULL, *e, es[] = "11:22:33:44:55:66"; |
d52fb7e3 | 1540 | char s_env_mac[64]; |
ebd0a0ae | 1541 | uchar v_env_mac[6], v_rom_mac[6], *v_mac; |
b56ddc63 WD |
1542 | |
1543 | env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac)); | |
1544 | if ((env_size > 0) && (env_size < sizeof (es))) { /* exit if env is bad */ | |
1545 | printf ("\n*** ERROR: ethaddr is not set properly!!\n"); | |
1546 | return (-1); | |
1547 | } | |
1548 | ||
1549 | if (env_size > 0) { | |
1550 | env_present = 1; | |
1551 | s = s_env_mac; | |
8bde7f77 | 1552 | } |
8bde7f77 | 1553 | |
42dfe7a1 | 1554 | for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */ |
b56ddc63 WD |
1555 | v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0; |
1556 | if (s) | |
1557 | s = (*e) ? e + 1 : e; | |
8bde7f77 | 1558 | } |
b56ddc63 WD |
1559 | |
1560 | rom_valid = get_rom_mac (v_rom_mac); /* get ROM mac value if any */ | |
1561 | ||
1562 | if (!env_present) { /* if NO env */ | |
1563 | if (rom_valid) { /* but ROM is valid */ | |
ebd0a0ae | 1564 | v_mac = v_rom_mac; |
b56ddc63 WD |
1565 | sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", |
1566 | v_mac[0], v_mac[1], v_mac[2], v_mac[3], | |
1567 | v_mac[4], v_mac[5]); | |
1568 | setenv ("ethaddr", s_env_mac); | |
1569 | } else { /* no env, bad ROM */ | |
1570 | printf ("\n*** ERROR: ethaddr is NOT set !!\n"); | |
1571 | return (-1); | |
1572 | } | |
1573 | } else { /* good env, don't care ROM */ | |
ebd0a0ae | 1574 | v_mac = v_env_mac; /* always use a good env over a ROM */ |
b56ddc63 WD |
1575 | } |
1576 | ||
42dfe7a1 | 1577 | if (env_present && rom_valid) { /* if both env and ROM are good */ |
b56ddc63 | 1578 | if (memcmp (v_env_mac, v_rom_mac, 6) != 0) { |
b56ddc63 WD |
1579 | printf ("\nWarning: MAC addresses don't match:\n"); |
1580 | printf ("\tHW MAC address: " | |
1581 | "%02X:%02X:%02X:%02X:%02X:%02X\n", | |
1582 | v_rom_mac[0], v_rom_mac[1], | |
1583 | v_rom_mac[2], v_rom_mac[3], | |
1584 | v_rom_mac[4], v_rom_mac[5] ); | |
1585 | printf ("\t\"ethaddr\" value: " | |
1586 | "%02X:%02X:%02X:%02X:%02X:%02X\n", | |
1587 | v_env_mac[0], v_env_mac[1], | |
1588 | v_env_mac[2], v_env_mac[3], | |
1589 | v_env_mac[4], v_env_mac[5]) ; | |
1590 | debug ("### Set MAC addr from environment\n"); | |
b56ddc63 WD |
1591 | } |
1592 | } | |
1593 | memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */ | |
d52fb7e3 | 1594 | smc_set_mac_addr ((uchar *)v_mac); /* use old function to update smc default */ |
3d3befa7 | 1595 | PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1], |
42dfe7a1 | 1596 | v_mac[2], v_mac[3], v_mac[4], v_mac[5]); |
b56ddc63 | 1597 | return (0); |
0b97ab14 WD |
1598 | } |
1599 | ||
d52fb7e3 | 1600 | int get_rom_mac (uchar *v_rom_mac) |
0b97ab14 | 1601 | { |
b56ddc63 WD |
1602 | #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ |
1603 | char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 }; | |
0b97ab14 | 1604 | |
b56ddc63 WD |
1605 | memcpy (v_rom_mac, hw_mac_addr, 6); |
1606 | return (1); | |
0b97ab14 | 1607 | #else |
3d3befa7 | 1608 | int i; |
f39748ae WD |
1609 | int valid_mac = 0; |
1610 | ||
3d3befa7 WD |
1611 | SMC_SELECT_BANK (1); |
1612 | for (i=0; i<6; i++) | |
1613 | { | |
39539887 | 1614 | v_rom_mac[i] = SMC_inb ((ADDR0_REG + i)); |
f39748ae | 1615 | valid_mac |= v_rom_mac[i]; |
b56ddc63 | 1616 | } |
f39748ae WD |
1617 | |
1618 | return (valid_mac ? 1 : 0); | |
0b97ab14 WD |
1619 | #endif |
1620 | } |