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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
fc9a8e8d KM |
2 | /* |
3 | * Ethernet driver for TI K2HK EVM. | |
4 | * | |
5 | * (C) Copyright 2012-2014 | |
6 | * Texas Instruments Incorporated, <www.ti.com> | |
fc9a8e8d | 7 | */ |
d678a59d | 8 | #include <common.h> |
fc9a8e8d | 9 | #include <command.h> |
24b852a7 | 10 | #include <console.h> |
401d1c4f | 11 | #include <asm/global_data.h> |
c05ed00a | 12 | #include <linux/delay.h> |
1e94b46f | 13 | #include <linux/printk.h> |
fc9a8e8d | 14 | |
6599f369 | 15 | #include <dm.h> |
a61f6a55 | 16 | #include <dm/lists.h> |
6599f369 | 17 | |
fc9a8e8d | 18 | #include <net.h> |
3fe93623 | 19 | #include <phy.h> |
c05d05e7 | 20 | #include <errno.h> |
fc9a8e8d KM |
21 | #include <miiphy.h> |
22 | #include <malloc.h> | |
ef454717 | 23 | #include <asm/ti-common/keystone_nav.h> |
0935cac6 | 24 | #include <asm/ti-common/keystone_net.h> |
a43febde | 25 | #include <asm/ti-common/keystone_serdes.h> |
6599f369 M |
26 | #include <asm/arch/psc_defs.h> |
27 | ||
79d81271 GS |
28 | #include "cpsw_mdio.h" |
29 | ||
6599f369 | 30 | DECLARE_GLOBAL_DATA_PTR; |
fc9a8e8d | 31 | |
fc9a8e8d KM |
32 | #ifdef KEYSTONE2_EMAC_GIG_ENABLE |
33 | #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) | |
34 | #else | |
35 | #define emac_gigabit_enable(x) /* no gigabit to enable */ | |
36 | #endif | |
37 | ||
38 | #define RX_BUFF_NUMS 24 | |
39 | #define RX_BUFF_LEN 1520 | |
40 | #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN | |
c05d05e7 | 41 | #define SGMII_ANEG_TIMEOUT 4000 |
fc9a8e8d KM |
42 | |
43 | static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16); | |
44 | ||
6599f369 | 45 | enum link_type { |
1de40662 M |
46 | LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0, |
47 | LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1, | |
48 | LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE = 2, | |
49 | LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE = 3, | |
50 | LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4, | |
51 | LINK_TYPE_RGMII_LINK_MAC_PHY = 5, | |
52 | LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6, | |
53 | LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO = 7, | |
54 | LINK_TYPE_10G_MAC_TO_PHY_MODE = 10, | |
55 | LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11, | |
6599f369 | 56 | }; |
fc9a8e8d | 57 | |
6599f369 M |
58 | #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ |
59 | ((mac)[2] << 16) | ((mac)[3] << 24)) | |
60 | #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) | |
fc9a8e8d | 61 | |
6599f369 | 62 | #ifdef CONFIG_KSNET_NETCP_V1_0 |
fc9a8e8d | 63 | |
6599f369 M |
64 | #define EMAC_EMACSW_BASE_OFS 0x90800 |
65 | #define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60) | |
66 | ||
67 | /* CPSW Switch slave registers */ | |
68 | #define CPGMACSL_REG_SA_LO 0x10 | |
69 | #define CPGMACSL_REG_SA_HI 0x14 | |
70 | ||
71 | #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \ | |
72 | (x) * 0x30) | |
73 | ||
af0cf217 | 74 | #elif defined(CONFIG_KSNET_NETCP_V1_5) |
6599f369 M |
75 | |
76 | #define EMAC_EMACSW_PORT_BASE_OFS 0x222000 | |
77 | ||
78 | /* CPSW Switch slave registers */ | |
79 | #define CPGMACSL_REG_SA_LO 0x308 | |
80 | #define CPGMACSL_REG_SA_HI 0x30c | |
81 | ||
82 | #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \ | |
83 | (x) * 0x1000) | |
84 | ||
85 | #endif | |
86 | ||
87 | ||
88 | struct ks2_eth_priv { | |
89 | struct udevice *dev; | |
90 | struct phy_device *phydev; | |
91 | struct mii_dev *mdio_bus; | |
92 | int phy_addr; | |
93 | phy_interface_t phy_if; | |
71b65d82 | 94 | ofnode phy_ofnode; |
6599f369 | 95 | int sgmii_link_type; |
af8b0a8d | 96 | phys_addr_t mdio_base; |
6599f369 M |
97 | struct rx_buff_desc net_rx_buffs; |
98 | struct pktdma_cfg *netcp_pktdma; | |
99 | void *hd; | |
100 | int slave_port; | |
101 | enum link_type link_type; | |
102 | bool emac_open; | |
103 | bool has_mdio; | |
104 | }; | |
fc9a8e8d | 105 | |
6599f369 M |
106 | static void __attribute__((unused)) |
107 | keystone2_eth_gigabit_enable(struct udevice *dev) | |
108 | { | |
109 | struct ks2_eth_priv *priv = dev_get_priv(dev); | |
6599f369 M |
110 | |
111 | /* | |
112 | * Check if link detected is giga-bit | |
113 | * If Gigabit mode detected, enable gigbit in MAC | |
114 | */ | |
79d81271 GS |
115 | if (priv->has_mdio) { |
116 | if (priv->phydev->speed != 1000) | |
117 | return; | |
118 | } | |
119 | ||
6599f369 M |
120 | writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) + |
121 | CPGMACSL_REG_CTL) | | |
122 | EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, | |
123 | DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL); | |
124 | } | |
fc9a8e8d | 125 | |
4657a2d4 VA |
126 | #ifdef CONFIG_SOC_K2G |
127 | int keystone_rgmii_config(struct phy_device *phy_dev) | |
128 | { | |
129 | unsigned int i, status; | |
130 | ||
131 | i = 0; | |
132 | do { | |
133 | if (i > SGMII_ANEG_TIMEOUT) { | |
134 | puts(" TIMEOUT !\n"); | |
135 | phy_dev->link = 0; | |
136 | return 0; | |
137 | } | |
138 | ||
139 | if (ctrlc()) { | |
140 | puts("user interrupt!\n"); | |
141 | phy_dev->link = 0; | |
142 | return -EINTR; | |
143 | } | |
144 | ||
145 | if ((i++ % 500) == 0) | |
146 | printf("."); | |
147 | ||
148 | udelay(1000); /* 1 ms */ | |
149 | status = readl(RGMII_STATUS_REG); | |
150 | } while (!(status & RGMII_REG_STATUS_LINK)); | |
151 | ||
152 | puts(" done\n"); | |
153 | ||
154 | return 0; | |
155 | } | |
156 | #else | |
c05d05e7 | 157 | int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface) |
fc9a8e8d KM |
158 | { |
159 | unsigned int i, status, mask; | |
160 | unsigned int mr_adv_ability, control; | |
161 | ||
162 | switch (interface) { | |
163 | case SGMII_LINK_MAC_MAC_AUTONEG: | |
164 | mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | | |
165 | SGMII_REG_MR_ADV_LINK | | |
166 | SGMII_REG_MR_ADV_FULL_DUPLEX | | |
167 | SGMII_REG_MR_ADV_GIG_MODE); | |
168 | control = (SGMII_REG_CONTROL_MASTER | | |
169 | SGMII_REG_CONTROL_AUTONEG); | |
170 | ||
171 | break; | |
172 | case SGMII_LINK_MAC_PHY: | |
173 | case SGMII_LINK_MAC_PHY_FORCED: | |
174 | mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; | |
175 | control = SGMII_REG_CONTROL_AUTONEG; | |
176 | ||
177 | break; | |
178 | case SGMII_LINK_MAC_MAC_FORCED: | |
179 | mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | | |
180 | SGMII_REG_MR_ADV_LINK | | |
181 | SGMII_REG_MR_ADV_FULL_DUPLEX | | |
182 | SGMII_REG_MR_ADV_GIG_MODE); | |
183 | control = SGMII_REG_CONTROL_MASTER; | |
184 | ||
185 | break; | |
186 | case SGMII_LINK_MAC_FIBER: | |
187 | mr_adv_ability = 0x20; | |
188 | control = SGMII_REG_CONTROL_AUTONEG; | |
189 | ||
190 | break; | |
191 | default: | |
192 | mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; | |
193 | control = SGMII_REG_CONTROL_AUTONEG; | |
194 | } | |
195 | ||
196 | __raw_writel(0, SGMII_CTL_REG(port)); | |
197 | ||
198 | /* | |
199 | * Wait for the SerDes pll to lock, | |
200 | * but don't trap if lock is never read | |
201 | */ | |
202 | for (i = 0; i < 1000; i++) { | |
203 | udelay(2000); | |
204 | status = __raw_readl(SGMII_STATUS_REG(port)); | |
205 | if ((status & SGMII_REG_STATUS_LOCK) != 0) | |
206 | break; | |
207 | } | |
208 | ||
209 | __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port)); | |
210 | __raw_writel(control, SGMII_CTL_REG(port)); | |
211 | ||
212 | ||
213 | mask = SGMII_REG_STATUS_LINK; | |
214 | ||
215 | if (control & SGMII_REG_CONTROL_AUTONEG) | |
216 | mask |= SGMII_REG_STATUS_AUTONEG; | |
217 | ||
c05d05e7 KI |
218 | status = __raw_readl(SGMII_STATUS_REG(port)); |
219 | if ((status & mask) == mask) | |
220 | return 0; | |
221 | ||
222 | printf("\n%s Waiting for SGMII auto negotiation to complete", | |
223 | phy_dev->dev->name); | |
224 | while ((status & mask) != mask) { | |
225 | /* | |
226 | * Timeout reached ? | |
227 | */ | |
228 | if (i > SGMII_ANEG_TIMEOUT) { | |
229 | puts(" TIMEOUT !\n"); | |
230 | phy_dev->link = 0; | |
231 | return 0; | |
232 | } | |
233 | ||
234 | if (ctrlc()) { | |
235 | puts("user interrupt!\n"); | |
236 | phy_dev->link = 0; | |
237 | return -EINTR; | |
238 | } | |
239 | ||
240 | if ((i++ % 500) == 0) | |
241 | printf("."); | |
242 | ||
243 | udelay(1000); /* 1 ms */ | |
fc9a8e8d | 244 | status = __raw_readl(SGMII_STATUS_REG(port)); |
fc9a8e8d | 245 | } |
c05d05e7 | 246 | puts(" done\n"); |
fc9a8e8d KM |
247 | |
248 | return 0; | |
249 | } | |
4657a2d4 | 250 | #endif |
fc9a8e8d KM |
251 | |
252 | int mac_sl_reset(u32 port) | |
253 | { | |
254 | u32 i, v; | |
255 | ||
256 | if (port >= DEVICE_N_GMACSL_PORTS) | |
257 | return GMACSL_RET_INVALID_PORT; | |
258 | ||
259 | /* Set the soft reset bit */ | |
e6c9428a KI |
260 | writel(CPGMAC_REG_RESET_VAL_RESET, |
261 | DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); | |
fc9a8e8d KM |
262 | |
263 | /* Wait for the bit to clear */ | |
264 | for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { | |
e6c9428a | 265 | v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); |
fc9a8e8d KM |
266 | if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != |
267 | CPGMAC_REG_RESET_VAL_RESET) | |
268 | return GMACSL_RET_OK; | |
269 | } | |
270 | ||
271 | /* Timeout on the reset */ | |
272 | return GMACSL_RET_WARN_RESET_INCOMPLETE; | |
273 | } | |
274 | ||
275 | int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) | |
276 | { | |
277 | u32 v, i; | |
278 | int ret = GMACSL_RET_OK; | |
279 | ||
280 | if (port >= DEVICE_N_GMACSL_PORTS) | |
281 | return GMACSL_RET_INVALID_PORT; | |
282 | ||
283 | if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) { | |
284 | cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN; | |
285 | ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG; | |
286 | } | |
287 | ||
288 | /* Must wait if the device is undergoing reset */ | |
289 | for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { | |
e6c9428a | 290 | v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET); |
fc9a8e8d KM |
291 | if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != |
292 | CPGMAC_REG_RESET_VAL_RESET) | |
293 | break; | |
294 | } | |
295 | ||
296 | if (i == DEVICE_EMACSL_RESET_POLL_COUNT) | |
297 | return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE; | |
298 | ||
e6c9428a KI |
299 | writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN); |
300 | writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL); | |
fc9a8e8d | 301 | |
4657a2d4 | 302 | #ifndef CONFIG_SOC_K2HK |
ff11c769 KI |
303 | /* Map RX packet flow priority to 0 */ |
304 | writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP); | |
305 | #endif | |
306 | ||
fc9a8e8d KM |
307 | return ret; |
308 | } | |
309 | ||
310 | int ethss_config(u32 ctl, u32 max_pkt_size) | |
311 | { | |
312 | u32 i; | |
313 | ||
314 | /* Max length register */ | |
e6c9428a | 315 | writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN); |
fc9a8e8d KM |
316 | |
317 | /* Control register */ | |
e6c9428a | 318 | writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL); |
fc9a8e8d KM |
319 | |
320 | /* All statistics enabled by default */ | |
e6c9428a KI |
321 | writel(CPSW_REG_VAL_STAT_ENABLE_ALL, |
322 | DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN); | |
fc9a8e8d KM |
323 | |
324 | /* Reset and enable the ALE */ | |
e6c9428a KI |
325 | writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE | |
326 | CPSW_REG_VAL_ALE_CTL_BYPASS, | |
327 | DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL); | |
fc9a8e8d KM |
328 | |
329 | /* All ports put into forward mode */ | |
330 | for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++) | |
e6c9428a KI |
331 | writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE, |
332 | DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i)); | |
fc9a8e8d KM |
333 | |
334 | return 0; | |
335 | } | |
336 | ||
337 | int ethss_start(void) | |
338 | { | |
339 | int i; | |
340 | struct mac_sl_cfg cfg; | |
341 | ||
342 | cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER; | |
343 | cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL; | |
344 | ||
345 | for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) { | |
346 | mac_sl_reset(i); | |
347 | mac_sl_config(i, &cfg); | |
348 | } | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
353 | int ethss_stop(void) | |
354 | { | |
355 | int i; | |
356 | ||
357 | for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) | |
358 | mac_sl_reset(i); | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
6599f369 M |
363 | struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { |
364 | .clk = SERDES_CLOCK_156P25M, | |
365 | .rate = SERDES_RATE_5G, | |
366 | .rate_mode = SERDES_QUARTER_RATE, | |
367 | .intf = SERDES_PHY_SGMII, | |
368 | .loopback = 0, | |
369 | }; | |
370 | ||
371 | #ifndef CONFIG_SOC_K2G | |
372 | static void keystone2_net_serdes_setup(void) | |
373 | { | |
e9f508cf | 374 | ks2_serdes_init(CFG_KSNET_SERDES_SGMII_BASE, |
6599f369 | 375 | &ks2_serdes_sgmii_156p25mhz, |
d0366061 | 376 | CFG_KSNET_SERDES_LANES_PER_SGMII); |
6599f369 M |
377 | |
378 | #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L) | |
81d239ae | 379 | ks2_serdes_init(CFG_KSNET_SERDES_SGMII2_BASE, |
6599f369 | 380 | &ks2_serdes_sgmii_156p25mhz, |
d0366061 | 381 | CFG_KSNET_SERDES_LANES_PER_SGMII); |
6599f369 M |
382 | #endif |
383 | ||
384 | /* wait till setup */ | |
385 | udelay(5000); | |
386 | } | |
387 | #endif | |
388 | ||
6599f369 | 389 | static int ks2_eth_start(struct udevice *dev) |
fc9a8e8d | 390 | { |
6599f369 | 391 | struct ks2_eth_priv *priv = dev_get_priv(dev); |
92a16c81 | 392 | |
6599f369 M |
393 | #ifdef CONFIG_SOC_K2G |
394 | keystone_rgmii_config(priv->phydev); | |
395 | #else | |
396 | keystone_sgmii_config(priv->phydev, priv->slave_port - 1, | |
397 | priv->sgmii_link_type); | |
3c61502a KI |
398 | #endif |
399 | ||
6599f369 M |
400 | udelay(10000); |
401 | ||
402 | /* On chip switch configuration */ | |
403 | ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE); | |
404 | ||
405 | qm_init(); | |
406 | ||
407 | if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) { | |
9b643e31 | 408 | pr_err("ksnav_init failed\n"); |
6599f369 M |
409 | goto err_knav_init; |
410 | } | |
411 | ||
412 | /* | |
413 | * Streaming switch configuration. If not present this | |
414 | * statement is defined to void in target.h. | |
415 | * If present this is usually defined to a series of register writes | |
416 | */ | |
417 | hw_config_streaming_switch(); | |
418 | ||
419 | if (priv->has_mdio) { | |
420 | phy_startup(priv->phydev); | |
421 | if (priv->phydev->link == 0) { | |
9b643e31 | 422 | pr_err("phy startup failed\n"); |
6599f369 M |
423 | goto err_phy_start; |
424 | } | |
425 | } | |
426 | ||
427 | emac_gigabit_enable(dev); | |
428 | ||
429 | ethss_start(); | |
430 | ||
431 | priv->emac_open = true; | |
432 | ||
433 | return 0; | |
434 | ||
435 | err_phy_start: | |
436 | ksnav_close(priv->netcp_pktdma); | |
437 | err_knav_init: | |
438 | qm_close(); | |
439 | ||
440 | return -EFAULT; | |
441 | } | |
442 | ||
443 | static int ks2_eth_send(struct udevice *dev, void *packet, int length) | |
444 | { | |
445 | struct ks2_eth_priv *priv = dev_get_priv(dev); | |
446 | ||
447 | genphy_update_link(priv->phydev); | |
448 | if (priv->phydev->link == 0) | |
449 | return -1; | |
450 | ||
451 | if (length < EMAC_MIN_ETHERNET_PKT_SIZE) | |
452 | length = EMAC_MIN_ETHERNET_PKT_SIZE; | |
453 | ||
454 | return ksnav_send(priv->netcp_pktdma, (u32 *)packet, | |
455 | length, (priv->slave_port) << 16); | |
456 | } | |
457 | ||
458 | static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp) | |
459 | { | |
460 | struct ks2_eth_priv *priv = dev_get_priv(dev); | |
461 | int pkt_size; | |
462 | u32 *pkt = NULL; | |
463 | ||
464 | priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size); | |
465 | if (priv->hd == NULL) | |
466 | return -EAGAIN; | |
467 | ||
468 | *packetp = (uchar *)pkt; | |
469 | ||
470 | return pkt_size; | |
471 | } | |
472 | ||
473 | static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet, | |
474 | int length) | |
475 | { | |
476 | struct ks2_eth_priv *priv = dev_get_priv(dev); | |
477 | ||
478 | ksnav_release_rxhd(priv->netcp_pktdma, priv->hd); | |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
483 | static void ks2_eth_stop(struct udevice *dev) | |
484 | { | |
485 | struct ks2_eth_priv *priv = dev_get_priv(dev); | |
486 | ||
487 | if (!priv->emac_open) | |
488 | return; | |
489 | ethss_stop(); | |
490 | ||
491 | ksnav_close(priv->netcp_pktdma); | |
492 | qm_close(); | |
493 | phy_shutdown(priv->phydev); | |
494 | priv->emac_open = false; | |
495 | } | |
496 | ||
497 | int ks2_eth_read_rom_hwaddr(struct udevice *dev) | |
498 | { | |
499 | struct ks2_eth_priv *priv = dev_get_priv(dev); | |
c69cda25 | 500 | struct eth_pdata *pdata = dev_get_plat(dev); |
6599f369 M |
501 | u32 maca = 0; |
502 | u32 macb = 0; | |
503 | ||
504 | /* Read the e-fuse mac address */ | |
505 | if (priv->slave_port == 1) { | |
506 | maca = __raw_readl(MAC_ID_BASE_ADDR); | |
507 | macb = __raw_readl(MAC_ID_BASE_ADDR + 4); | |
508 | } | |
509 | ||
510 | pdata->enetaddr[0] = (macb >> 8) & 0xff; | |
511 | pdata->enetaddr[1] = (macb >> 0) & 0xff; | |
512 | pdata->enetaddr[2] = (maca >> 24) & 0xff; | |
513 | pdata->enetaddr[3] = (maca >> 16) & 0xff; | |
514 | pdata->enetaddr[4] = (maca >> 8) & 0xff; | |
515 | pdata->enetaddr[5] = (maca >> 0) & 0xff; | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
520 | int ks2_eth_write_hwaddr(struct udevice *dev) | |
521 | { | |
522 | struct ks2_eth_priv *priv = dev_get_priv(dev); | |
c69cda25 | 523 | struct eth_pdata *pdata = dev_get_plat(dev); |
6599f369 M |
524 | |
525 | writel(mac_hi(pdata->enetaddr), | |
526 | DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) + | |
527 | CPGMACSL_REG_SA_HI); | |
528 | writel(mac_lo(pdata->enetaddr), | |
529 | DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) + | |
530 | CPGMACSL_REG_SA_LO); | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
535 | static int ks2_eth_probe(struct udevice *dev) | |
536 | { | |
537 | struct ks2_eth_priv *priv = dev_get_priv(dev); | |
538 | struct mii_dev *mdio_bus; | |
6599f369 M |
539 | |
540 | priv->dev = dev; | |
79d81271 | 541 | priv->emac_open = false; |
6599f369 M |
542 | |
543 | /* These clock enables has to be moved to common location */ | |
544 | if (cpu_is_k2g()) | |
545 | writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG); | |
546 | ||
547 | /* By default, select PA PLL clock as PA clock source */ | |
548 | #ifndef CONFIG_SOC_K2G | |
549 | if (psc_enable_module(KS2_LPSC_PA)) | |
550 | return -EACCES; | |
551 | #endif | |
552 | if (psc_enable_module(KS2_LPSC_CPGMAC)) | |
553 | return -EACCES; | |
554 | if (psc_enable_module(KS2_LPSC_CRYPTO)) | |
555 | return -EACCES; | |
556 | ||
557 | if (cpu_is_k2e() || cpu_is_k2l()) | |
558 | pll_pa_clk_sel(); | |
559 | ||
1610a921 M |
560 | priv->net_rx_buffs.buff_ptr = rx_buffs; |
561 | priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS; | |
562 | priv->net_rx_buffs.buff_len = RX_BUFF_LEN; | |
6599f369 | 563 | |
a61f6a55 | 564 | if (priv->slave_port == 1) { |
79d81271 GS |
565 | #ifndef CONFIG_SOC_K2G |
566 | keystone2_net_serdes_setup(); | |
567 | #endif | |
a61f6a55 M |
568 | /* |
569 | * Register MDIO bus for slave 0 only, other slave have | |
570 | * to re-use the same | |
571 | */ | |
79d81271 | 572 | mdio_bus = cpsw_mdio_init("ethernet-mdio", |
af8b0a8d | 573 | priv->mdio_base, |
79d81271 | 574 | EMAC_MDIO_CLOCK_FREQ, |
9ea30ea6 RG |
575 | EMAC_MDIO_BUS_FREQ, |
576 | false); | |
a61f6a55 | 577 | if (!mdio_bus) { |
9b643e31 | 578 | pr_err("MDIO alloc failed\n"); |
a61f6a55 M |
579 | return -ENOMEM; |
580 | } | |
581 | priv->mdio_bus = mdio_bus; | |
a61f6a55 M |
582 | } else { |
583 | /* Get the MDIO bus from slave 0 device */ | |
584 | struct ks2_eth_priv *parent_priv; | |
585 | ||
586 | parent_priv = dev_get_priv(dev->parent); | |
587 | priv->mdio_bus = parent_priv->mdio_bus; | |
79d81271 | 588 | priv->mdio_base = parent_priv->mdio_base; |
6599f369 M |
589 | } |
590 | ||
6599f369 M |
591 | priv->netcp_pktdma = &netcp_pktdma; |
592 | ||
a61f6a55 M |
593 | if (priv->has_mdio) { |
594 | priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr, | |
595 | dev, priv->phy_if); | |
8a9e3464 TR |
596 | if (ofnode_valid(priv->phy_ofnode)) |
597 | priv->phydev->node = priv->phy_ofnode; | |
a61f6a55 M |
598 | phy_config(priv->phydev); |
599 | } | |
6599f369 M |
600 | |
601 | return 0; | |
fc9a8e8d | 602 | } |
6599f369 M |
603 | |
604 | int ks2_eth_remove(struct udevice *dev) | |
605 | { | |
606 | struct ks2_eth_priv *priv = dev_get_priv(dev); | |
607 | ||
79d81271 | 608 | cpsw_mdio_free(priv->mdio_bus); |
6599f369 M |
609 | |
610 | return 0; | |
611 | } | |
612 | ||
613 | static const struct eth_ops ks2_eth_ops = { | |
614 | .start = ks2_eth_start, | |
615 | .send = ks2_eth_send, | |
616 | .recv = ks2_eth_recv, | |
617 | .free_pkt = ks2_eth_free_pkt, | |
618 | .stop = ks2_eth_stop, | |
619 | .read_rom_hwaddr = ks2_eth_read_rom_hwaddr, | |
620 | .write_hwaddr = ks2_eth_write_hwaddr, | |
621 | }; | |
622 | ||
71b65d82 | 623 | static int ks2_bind_one_slave(struct udevice *dev, ofnode slave, ofnode *gbe_0) |
6599f369 | 624 | { |
a61f6a55 | 625 | char *slave_name; |
71b65d82 | 626 | u32 slave_no; |
71f47391 MB |
627 | int ret; |
628 | ||
71b65d82 | 629 | if (ofnode_read_u32(slave, "slave-port", &slave_no)) |
71f47391 MB |
630 | return 0; |
631 | ||
632 | if (gbe_0 && slave_no == 0) { | |
633 | /* This is the current eth device */ | |
634 | *gbe_0 = slave; | |
635 | return 0; | |
636 | } | |
637 | ||
638 | /* Slave devices to be registered */ | |
639 | slave_name = malloc(20); | |
640 | snprintf(slave_name, 20, "netcp@slave-%d", slave_no); | |
71b65d82 MB |
641 | ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name, slave, |
642 | NULL); | |
71f47391 MB |
643 | if (ret) |
644 | pr_err("ks2_net - not able to bind slave interfaces\n"); | |
645 | ||
646 | return ret; | |
647 | } | |
648 | ||
71b65d82 | 649 | static int ks2_eth_bind_slaves(struct udevice *dev, ofnode gbe, ofnode *gbe_0) |
71f47391 | 650 | { |
71b65d82 MB |
651 | ofnode interfaces, sec_slave, slave; |
652 | int ret; | |
a61f6a55 | 653 | |
71b65d82 MB |
654 | interfaces = ofnode_find_subnode(gbe, "interfaces"); |
655 | ofnode_for_each_subnode(slave, interfaces) { | |
71f47391 MB |
656 | ret = ks2_bind_one_slave(dev, slave, gbe_0); |
657 | if (ret) | |
658 | return ret; | |
a61f6a55 M |
659 | } |
660 | ||
71b65d82 MB |
661 | sec_slave = ofnode_find_subnode(gbe, "secondary-slave-ports"); |
662 | ofnode_for_each_subnode(slave, sec_slave) { | |
71f47391 MB |
663 | ret = ks2_bind_one_slave(dev, slave, NULL); |
664 | if (ret) | |
a61f6a55 | 665 | return ret; |
a61f6a55 M |
666 | } |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
71b65d82 | 671 | static int ks2_eth_parse_slave_interface(ofnode netcp, ofnode slave, |
a61f6a55 M |
672 | struct ks2_eth_priv *priv, |
673 | struct eth_pdata *pdata) | |
674 | { | |
71b65d82 MB |
675 | struct ofnode_phandle_args dma_args; |
676 | ofnode phy, mdio; | |
a61f6a55 | 677 | int dma_count; |
6599f369 | 678 | |
71b65d82 | 679 | priv->slave_port = ofnode_read_s32_default(slave, "slave-port", -1); |
a61f6a55 | 680 | priv->net_rx_buffs.rx_flow = priv->slave_port * 8; |
6599f369 | 681 | |
6599f369 M |
682 | /* U-Boot slave port number starts with 1 instead of 0 */ |
683 | priv->slave_port += 1; | |
684 | ||
71b65d82 MB |
685 | dma_count = ofnode_count_phandle_with_args(netcp, "ti,navigator-dmas", |
686 | NULL, 1); | |
687 | if (priv->slave_port < dma_count && | |
688 | !ofnode_parse_phandle_with_args(netcp, "ti,navigator-dmas", NULL, 1, | |
689 | priv->slave_port - 1, &dma_args)) | |
690 | priv->net_rx_buffs.rx_flow = dma_args.args[0]; | |
a61f6a55 | 691 | |
71b65d82 | 692 | priv->link_type = ofnode_read_s32_default(slave, "link-interface", -1); |
55d5cb17 | 693 | |
71b65d82 MB |
694 | phy = ofnode_get_phy_node(slave); |
695 | priv->phy_ofnode = phy; | |
696 | if (ofnode_valid(phy)) { | |
697 | priv->phy_addr = ofnode_read_s32_default(phy, "reg", -1); | |
a61f6a55 | 698 | |
71b65d82 MB |
699 | mdio = ofnode_get_parent(phy); |
700 | if (!ofnode_valid(mdio)) { | |
9b643e31 | 701 | pr_err("mdio dt not found\n"); |
a61f6a55 M |
702 | return -ENODEV; |
703 | } | |
af8b0a8d | 704 | priv->mdio_base = ofnode_get_addr(mdio); |
6599f369 | 705 | } |
6599f369 | 706 | |
1de40662 | 707 | if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) { |
6599f369 M |
708 | priv->phy_if = PHY_INTERFACE_MODE_SGMII; |
709 | pdata->phy_interface = priv->phy_if; | |
710 | priv->sgmii_link_type = SGMII_LINK_MAC_PHY; | |
711 | priv->has_mdio = true; | |
1de40662 | 712 | } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) { |
71b65d82 | 713 | priv->phy_if = ofnode_read_phy_mode(slave); |
ffb0f6f4 | 714 | if (priv->phy_if == PHY_INTERFACE_MODE_NA) |
55d5cb17 | 715 | priv->phy_if = PHY_INTERFACE_MODE_RGMII; |
1de40662 | 716 | pdata->phy_interface = priv->phy_if; |
123ca114 MB |
717 | |
718 | if (priv->phy_if != PHY_INTERFACE_MODE_RGMII && | |
719 | priv->phy_if != PHY_INTERFACE_MODE_RGMII_ID && | |
720 | priv->phy_if != PHY_INTERFACE_MODE_RGMII_RXID && | |
721 | priv->phy_if != PHY_INTERFACE_MODE_RGMII_TXID) { | |
722 | pr_err("invalid phy-mode\n"); | |
723 | return -EINVAL; | |
724 | } | |
725 | ||
1de40662 | 726 | priv->has_mdio = true; |
6599f369 | 727 | } |
6599f369 | 728 | |
a61f6a55 M |
729 | return 0; |
730 | } | |
731 | ||
d1998a9f | 732 | static int ks2_sl_eth_of_to_plat(struct udevice *dev) |
a61f6a55 | 733 | { |
71b65d82 | 734 | ofnode slave, interfaces, gbe, netcp_devices, netcp; |
a61f6a55 | 735 | struct ks2_eth_priv *priv = dev_get_priv(dev); |
c69cda25 | 736 | struct eth_pdata *pdata = dev_get_plat(dev); |
71b65d82 MB |
737 | |
738 | slave = dev_ofnode(dev); | |
739 | interfaces = ofnode_get_parent(slave); | |
740 | gbe = ofnode_get_parent(interfaces); | |
741 | netcp_devices = ofnode_get_parent(gbe); | |
742 | netcp = ofnode_get_parent(netcp_devices); | |
a61f6a55 M |
743 | |
744 | ks2_eth_parse_slave_interface(netcp, slave, priv, pdata); | |
745 | ||
71b65d82 | 746 | pdata->iobase = ofnode_get_addr(netcp); |
a61f6a55 M |
747 | |
748 | return 0; | |
749 | } | |
750 | ||
d1998a9f | 751 | static int ks2_eth_of_to_plat(struct udevice *dev) |
a61f6a55 M |
752 | { |
753 | struct ks2_eth_priv *priv = dev_get_priv(dev); | |
c69cda25 | 754 | struct eth_pdata *pdata = dev_get_plat(dev); |
71b65d82 | 755 | ofnode netcp_devices, gbe, gbe_0; |
a61f6a55 | 756 | |
71b65d82 MB |
757 | netcp_devices = dev_read_subnode(dev, "netcp-devices"); |
758 | gbe = ofnode_find_subnode(netcp_devices, "gbe"); | |
a61f6a55 | 759 | |
71b65d82 | 760 | gbe_0 = ofnode_null(); |
a61f6a55 M |
761 | ks2_eth_bind_slaves(dev, gbe, &gbe_0); |
762 | ||
71b65d82 | 763 | ks2_eth_parse_slave_interface(dev_ofnode(dev), gbe_0, priv, pdata); |
a61f6a55 | 764 | |
2548493a | 765 | pdata->iobase = dev_read_addr(dev); |
6599f369 M |
766 | |
767 | return 0; | |
768 | } | |
769 | ||
770 | static const struct udevice_id ks2_eth_ids[] = { | |
771 | { .compatible = "ti,netcp-1.0" }, | |
772 | { } | |
773 | }; | |
774 | ||
a61f6a55 M |
775 | U_BOOT_DRIVER(eth_ks2_slave) = { |
776 | .name = "eth_ks2_sl", | |
777 | .id = UCLASS_ETH, | |
d1998a9f | 778 | .of_to_plat = ks2_sl_eth_of_to_plat, |
a61f6a55 M |
779 | .probe = ks2_eth_probe, |
780 | .remove = ks2_eth_remove, | |
781 | .ops = &ks2_eth_ops, | |
41575d8e | 782 | .priv_auto = sizeof(struct ks2_eth_priv), |
caa4daa2 | 783 | .plat_auto = sizeof(struct eth_pdata), |
a61f6a55 M |
784 | .flags = DM_FLAG_ALLOC_PRIV_DMA, |
785 | }; | |
6599f369 M |
786 | |
787 | U_BOOT_DRIVER(eth_ks2) = { | |
788 | .name = "eth_ks2", | |
789 | .id = UCLASS_ETH, | |
790 | .of_match = ks2_eth_ids, | |
d1998a9f | 791 | .of_to_plat = ks2_eth_of_to_plat, |
6599f369 M |
792 | .probe = ks2_eth_probe, |
793 | .remove = ks2_eth_remove, | |
794 | .ops = &ks2_eth_ops, | |
41575d8e | 795 | .priv_auto = sizeof(struct ks2_eth_priv), |
caa4daa2 | 796 | .plat_auto = sizeof(struct eth_pdata), |
6599f369 M |
797 | .flags = DM_FLAG_ALLOC_PRIV_DMA, |
798 | }; |