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[people/ms/u-boot.git] / drivers / net / uli526x.c
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1f103105
RZ		 1/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
3 *
4 * Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
5 *
6 * Description:
7 * ULI 526x Ethernet port driver.
8 * Based on the Linux driver: drivers/net/tulip/uli526x.c
9 *
10 * This is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#include <common.h>
17#include <malloc.h>
18#include <net.h>
19#include <asm/io.h>
20#include <pci.h>
21#include <miiphy.h>
22
23/* some kernel function compatible define */
24
25#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
26 defined(CONFIG_ULI526X)
27
28#undef DEBUG
29
30/* Board/System/Debug information/definition */
31#define ULI_VENDOR_ID 0x10B9
32#define ULI5261_DEVICE_ID 0x5261
33#define ULI5263_DEVICE_ID 0x5263
34/* ULi M5261 ID*/
e845e07e 35#define PCI_ULI5261_ID (ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID)
1f103105 36/* ULi M5263 ID*/
e845e07e 37#define PCI_ULI5263_ID (ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID)
1f103105
RZ		 38
39#define ULI526X_IO_SIZE 0x100
40#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
41#define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */
42#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
43#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
44#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
45#define TX_BUF_ALLOC 0x300
46#define RX_ALLOC_SIZE PKTSIZE
47#define ULI526X_RESET 1
48#define CR0_DEFAULT 0
49#define CR6_DEFAULT 0x22200000
50#define CR7_DEFAULT 0x180c1
51#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
52#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
53#define MAX_PACKET_SIZE 1514
54#define ULI5261_MAX_MULTICAST 14
55#define RX_COPY_SIZE 100
56#define MAX_CHECK_PACKET 0x8000
57
58#define ULI526X_10MHF 0
59#define ULI526X_100MHF 1
60#define ULI526X_10MFD 4
61#define ULI526X_100MFD 5
62#define ULI526X_AUTO 8
63
64#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
65#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
66#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
67#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
68#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
69#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
70
71/* CR9 definition: SROM/MII */
72#define CR9_SROM_READ 0x4800
73#define CR9_SRCS 0x1
74#define CR9_SRCLK 0x2
75#define CR9_CRDOUT 0x8
76#define SROM_DATA_0 0x0
77#define SROM_DATA_1 0x4
78#define PHY_DATA_1 0x20000
79#define PHY_DATA_0 0x00000
80#define MDCLKH 0x10000
81
82#define PHY_POWER_DOWN 0x800
83
84#define SROM_V41_CODE 0x14
85
86#define SROM_CLK_WRITE(data, ioaddr) do { \
87 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
88 udelay(5); \
89 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
90 udelay(5); \
91 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
92 udelay(5); \
93 } while (0)
94
95/* Structure/enum declaration */
96
97struct tx_desc {
98 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
99 char *tx_buf_ptr; /* Data for us */
100 struct tx_desc *next_tx_desc;
101};
102
103struct rx_desc {
104 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
105 char *rx_buf_ptr; /* Data for us */
106 struct rx_desc *next_rx_desc;
107};
108
109struct uli526x_board_info {
110 u32 chip_id; /* Chip vendor/Device ID */
111 pci_dev_t pdev;
112
113 long ioaddr; /* I/O base address */
114 u32 cr0_data;
115 u32 cr5_data;
116 u32 cr6_data;
117 u32 cr7_data;
118 u32 cr15_data;
119
120 /* pointer for memory physical address */
121 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
122 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
123 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
124 dma_addr_t first_tx_desc_dma;
125 dma_addr_t first_rx_desc_dma;
126
127 /* descriptor pointer */
128 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
129 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
130 unsigned char *desc_pool_ptr; /* descriptor pool memory */
131 struct tx_desc *first_tx_desc;
132 struct tx_desc *tx_insert_ptr;
133 struct tx_desc *tx_remove_ptr;
134 struct rx_desc *first_rx_desc;
135 struct rx_desc *rx_ready_ptr; /* packet come pointer */
136 unsigned long tx_packet_cnt; /* transmitted packet count */
137
138 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
139
140 u8 media_mode; /* user specify media mode */
141 u8 op_mode; /* real work dedia mode */
142 u8 phy_addr;
143
144 /* NIC SROM data */
145 unsigned char srom[128];
146};
147
148enum uli526x_offsets {
149 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
150 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
151 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
152 DCR15 = 0x78
153};
154
155enum uli526x_CR6_bits {
156 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
157 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
158 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
159};
160
161/* Global variable declaration -- */
162
163static unsigned char uli526x_media_mode = ULI526X_AUTO;
164
165static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20]
166 __attribute__ ((aligned(32)));
167static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4];
168
169/* For module input parameter */
170static int mode = 8;
171
172/* function declaration -- */
173static int uli526x_start_xmit(struct eth_device *dev,
174 volatile void *packet, int length);
175static const struct ethtool_ops netdev_ethtool_ops;
176static u16 read_srom_word(long, int);
177static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
178static void allocate_rx_buffer(struct uli526x_board_info *);
179static void update_cr6(u32, unsigned long);
180static u16 phy_read(unsigned long, u8, u8, u32);
181static u16 phy_readby_cr10(unsigned long, u8, u8);
182static void phy_write(unsigned long, u8, u8, u16, u32);
183static void phy_writeby_cr10(unsigned long, u8, u8, u16);
184static void phy_write_1bit(unsigned long, u32, u32);
185static u16 phy_read_1bit(unsigned long, u32);
186static int uli526x_rx_packet(struct eth_device *);
187static void uli526x_free_tx_pkt(struct eth_device *,
188 struct uli526x_board_info *);
189static void uli526x_reuse_buf(struct rx_desc *);
190static void uli526x_init(struct eth_device *);
191static void uli526x_set_phyxcer(struct uli526x_board_info *);
192
193
194static int uli526x_init_one(struct eth_device *, bd_t *);
195static void uli526x_disable(struct eth_device *);
196static void set_mac_addr(struct eth_device *);
197
198static struct pci_device_id uli526x_pci_tbl[] = {
199 { ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */
200 { ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */
201 {}
202};
203
204/* ULI526X network board routine */
205
206/*
207 * Search ULI526X board, register it
208 */
209
210int uli526x_initialize(bd_t *bis)
211{
212 pci_dev_t devno;
213 int card_number = 0;
214 struct eth_device *dev;
215 struct uli526x_board_info *db; /* board information structure */
216
217 u32 iobase;
218 int idx = 0;
219
220 while (1) {
221 /* Find PCI device */
222 devno = pci_find_devices(uli526x_pci_tbl, idx++);
223 if (devno < 0)
224 break;
225
226 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
227 iobase &= ~0xf;
228
229 dev = (struct eth_device *)malloc(sizeof *dev);
230 sprintf(dev->name, "uli526x#%d\n", card_number);
231 db = (struct uli526x_board_info *)
232 malloc(sizeof(struct uli526x_board_info));
233
234 dev->priv = db;
235 db->pdev = devno;
236 dev->iobase = iobase;
237
238 dev->init = uli526x_init_one;
239 dev->halt = uli526x_disable;
240 dev->send = uli526x_start_xmit;
241 dev->recv = uli526x_rx_packet;
242
243 /* init db */
244 db->ioaddr = dev->iobase;
245 /* get chip id */
246
247 pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id);
248#ifdef DEBUG
249 printf("uli526x: uli526x @0x%x\n", iobase);
250 printf("uli526x: chip_id%x\n", db->chip_id);
251#endif
252 eth_register(dev);
253 card_number++;
254 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
255 udelay(10 * 1000);
256 }
257 return card_number;
258}
259
260static int uli526x_init_one(struct eth_device *dev, bd_t *bis)
261{
262
263 struct uli526x_board_info *db = dev->priv;
264 int i;
265
266 switch (mode) {
267 case ULI526X_10MHF:
268 case ULI526X_100MHF:
269 case ULI526X_10MFD:
270 case ULI526X_100MFD:
271 uli526x_media_mode = mode;
272 break;
273 default:
274 uli526x_media_mode = ULI526X_AUTO;
275 break;
276 }
277
278 /* Allocate Tx/Rx descriptor memory */
279 db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
280 db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
281 if (db->desc_pool_ptr == NULL)
422b1a01 282 return -1;
1f103105 283
e845e07e 284 db->buf_pool_ptr = (uchar *)&buf_pool[0];
1f103105
RZ		 285 db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
286 if (db->buf_pool_ptr == NULL)
422b1a01 287 return -1;
1f103105
RZ		 288
289 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
290 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
291
292 db->buf_pool_start = db->buf_pool_ptr;
293 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
294
295#ifdef DEBUG
296 printf("%s(): db->ioaddr= 0x%x\n",
297 __FUNCTION__, db->ioaddr);
298 printf("%s(): media_mode= 0x%x\n",
299 __FUNCTION__, uli526x_media_mode);
300 printf("%s(): db->desc_pool_ptr= 0x%x\n",
301 __FUNCTION__, db->desc_pool_ptr);
302 printf("%s(): db->desc_pool_dma_ptr= 0x%x\n",
303 __FUNCTION__, db->desc_pool_dma_ptr);
304 printf("%s(): db->buf_pool_ptr= 0x%x\n",
305 __FUNCTION__, db->buf_pool_ptr);
306 printf("%s(): db->buf_pool_dma_ptr= 0x%x\n",
307 __FUNCTION__, db->buf_pool_dma_ptr);
308#endif
309
310 /* read 64 word srom data */
311 for (i = 0; i < 64; i++)
312 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr,
313 i));
314
315 /* Set Node address */
316 if (((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0)
317 /* SROM absent, so write MAC address to ID Table */
318 set_mac_addr(dev);
319 else { /*Exist SROM*/
320 for (i = 0; i < 6; i++)
321 dev->enetaddr[i] = db->srom[20 + i];
322 }
323#ifdef DEBUG
324 for (i = 0; i < 6; i++)
325 printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]);
326#endif
327 db->PHY_reg4 = 0x1e0;
328
329 /* system variable init */
330 db->cr6_data = CR6_DEFAULT ;
331 db->cr6_data |= ULI526X_TXTH_256;
332 db->cr0_data = CR0_DEFAULT;
333 uli526x_init(dev);
422b1a01 334 return 0;
1f103105
RZ		 335}
336
337static void uli526x_disable(struct eth_device *dev)
338{
339#ifdef DEBUG
340 printf("uli526x_disable\n");
341#endif
342 struct uli526x_board_info *db = dev->priv;
343
344 if (!((inl(db->ioaddr + DCR12)) & 0x8)) {
345 /* Reset & stop ULI526X board */
346 outl(ULI526X_RESET, db->ioaddr + DCR0);
347 udelay(5);
348 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
349
350 /* reset the board */
351 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
352 update_cr6(db->cr6_data, dev->iobase);
353 outl(0, dev->iobase + DCR7); /* Disable Interrupt */
354 outl(inl(dev->iobase + DCR5), dev->iobase + DCR5);
355 }
356}
357
358/* Initialize ULI526X board
359 * Reset ULI526X board
360 * Initialize TX/Rx descriptor chain structure
361 * Send the set-up frame
362 * Enable Tx/Rx machine
363 */
364
365static void uli526x_init(struct eth_device *dev)
366{
367
368 struct uli526x_board_info *db = dev->priv;
369 u8 phy_tmp;
370 u16 phy_value;
371 u16 phy_reg_reset;
372
373 /* Reset M526x MAC controller */
374 outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */
375 udelay(100);
376 outl(db->cr0_data, db->ioaddr + DCR0);
377 udelay(5);
378
379 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
380 db->phy_addr = 1;
381 db->tx_packet_cnt = 0;
382 for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
383 /* peer add */
384 phy_value = phy_read(db->ioaddr, phy_tmp, 3, db->chip_id);
385 if (phy_value != 0xffff && phy_value != 0) {
386 db->phy_addr = phy_tmp;
387 break;
388 }
389 }
390
391#ifdef DEBUG
392 printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr);
393 printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr);
394#endif
395 if (phy_tmp == 32)
396 printf("Can not find the phy address!!!");
397
398 /* Parser SROM and media mode */
399 db->media_mode = uli526x_media_mode;
400
401 if (!(inl(db->ioaddr + DCR12) & 0x8)) {
402 /* Phyxcer capability setting */
403 phy_reg_reset = phy_read(db->ioaddr,
404 db->phy_addr, 0, db->chip_id);
405 phy_reg_reset = (phy_reg_reset | 0x8000);
406 phy_write(db->ioaddr, db->phy_addr, 0,
407 phy_reg_reset, db->chip_id);
408 udelay(500);
409
410 /* Process Phyxcer Media Mode */
411 uli526x_set_phyxcer(db);
412 }
413 /* Media Mode Process */
414 if (!(db->media_mode & ULI526X_AUTO))
53677ef1 415 db->op_mode = db->media_mode; /* Force Mode */
1f103105
RZ		 416
417 /* Initialize Transmit/Receive decriptor and CR3/4 */
418 uli526x_descriptor_init(db, db->ioaddr);
419
420 /* Init CR6 to program M526X operation */
421 update_cr6(db->cr6_data, db->ioaddr);
422
423 /* Init CR7, interrupt active bit */
424 db->cr7_data = CR7_DEFAULT;
425 outl(db->cr7_data, db->ioaddr + DCR7);
426
427 /* Init CR15, Tx jabber and Rx watchdog timer */
428 outl(db->cr15_data, db->ioaddr + DCR15);
429
430 /* Enable ULI526X Tx/Rx function */
431 db->cr6_data |= CR6_RXSC | CR6_TXSC;
432 update_cr6(db->cr6_data, db->ioaddr);
433 while (!(inl(db->ioaddr + DCR12) & 0x8))
434 udelay(10);
435}
436
437/*
438 * Hardware start transmission.
439 * Send a packet to media from the upper layer.
440 */
441
442static int uli526x_start_xmit(struct eth_device *dev,
443 volatile void *packet, int length)
444{
445 struct uli526x_board_info *db = dev->priv;
446 struct tx_desc *txptr;
447 unsigned int len = length;
448 /* Too large packet check */
449 if (len > MAX_PACKET_SIZE) {
450 printf(": big packet = %d\n", len);
451 return 0;
452 }
453
454 /* No Tx resource check, it never happen nromally */
455 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
456 printf("No Tx resource %ld\n", db->tx_packet_cnt);
457 return 0;
458 }
459
460 /* Disable NIC interrupt */
461 outl(0, dev->iobase + DCR7);
462
463 /* transmit this packet */
464 txptr = db->tx_insert_ptr;
465 memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length);
466 txptr->tdes1 = cpu_to_le32(0xe1000000 | length);
467
468 /* Point to next transmit free descriptor */
469 db->tx_insert_ptr = txptr->next_tx_desc;
470
471 /* Transmit Packet Process */
472 if ((db->tx_packet_cnt < TX_DESC_CNT)) {
473 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
474 db->tx_packet_cnt++; /* Ready to send */
475 outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */
476 }
477
478 /* Got ULI526X status */
479 db->cr5_data = inl(db->ioaddr + DCR5);
480 outl(db->cr5_data, db->ioaddr + DCR5);
481
482#ifdef TX_DEBUG
483 printf("%s(): length = 0x%x\n", __FUNCTION__, length);
484 printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data);
485#endif
486
487 outl(db->cr7_data, dev->iobase + DCR7);
488 uli526x_free_tx_pkt(dev, db);
489
490 return length;
491}
492
493/*
494 * Free TX resource after TX complete
495 */
496
497static void uli526x_free_tx_pkt(struct eth_device *dev,
498 struct uli526x_board_info *db)
499{
500 struct tx_desc *txptr;
501 u32 tdes0;
502
503 txptr = db->tx_remove_ptr;
504 while (db->tx_packet_cnt) {
505 tdes0 = le32_to_cpu(txptr->tdes0);
506 /* printf(DRV_NAME ": tdes0=%x\n", tdes0); */
507 if (tdes0 & 0x80000000)
508 break;
509
510 /* A packet sent completed */
511 db->tx_packet_cnt--;
512
513 if (tdes0 != 0x7fffffff) {
514#ifdef TX_DEBUG
515 printf("%s()tdes0=%x\n", __FUNCTION__, tdes0);
516#endif
517 if (tdes0 & TDES0_ERR_MASK) {
518 if (tdes0 & 0x0002) { /* UnderRun */
519 if (!(db->cr6_data & CR6_SFT)) {
520 db->cr6_data = db->cr6_data |
521 CR6_SFT;
522 update_cr6(db->cr6_data,
523 db->ioaddr);
524 }
525 }
526 }
527 }
528
529 txptr = txptr->next_tx_desc;
530 }/* End of while */
531
532 /* Update TX remove pointer to next */
533 db->tx_remove_ptr = txptr;
534}
535
536
537/*
538 * Receive the come packet and pass to upper layer
539 */
540
541static int uli526x_rx_packet(struct eth_device *dev)
542{
543 struct uli526x_board_info *db = dev->priv;
544 struct rx_desc *rxptr;
545 int rxlen = 0;
546 u32 rdes0;
547
548 rxptr = db->rx_ready_ptr;
549
550 rdes0 = le32_to_cpu(rxptr->rdes0);
551#ifdef RX_DEBUG
552 printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__, rxptr->rdes0);
553#endif
554 if (!(rdes0 & 0x80000000)) { /* packet owner check */
555 if ((rdes0 & 0x300) != 0x300) {
556 /* A packet without First/Last flag */
557 /* reuse this buf */
558 printf("A packet without First/Last flag");
559 uli526x_reuse_buf(rxptr);
560 } else {
561 /* A packet with First/Last flag */
562 rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
563#ifdef RX_DEBUG
564 printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen);
565#endif
566 /* error summary bit check */
567 if (rdes0 & 0x8000) {
568 /* This is a error packet */
569 printf("Eroor: rdes0: %lx\n", rdes0);
570 }
571
572 if (!(rdes0 & 0x8000) ||
573 ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
574
575#ifdef RX_DEBUG
576 printf("%s(): rx_skb_ptr =%x\n",
577 __FUNCTION__, rxptr->rx_buf_ptr);
578 printf("%s(): rxlen =%x\n",
579 __FUNCTION__, rxlen);
580
581 printf("%s(): buf addr =%x\n",
582 __FUNCTION__, rxptr->rx_buf_ptr);
583 printf("%s(): rxlen =%x\n",
584 __FUNCTION__, rxlen);
585 int i;
586 for (i = 0; i < 0x20; i++)
587 printf("%s(): data[%x] =%x\n",
588 __FUNCTION__, i, rxptr->rx_buf_ptr[i]);
589#endif
590
e845e07e 591 NetReceive((uchar *)rxptr->rx_buf_ptr, rxlen);
1f103105
RZ		 592 uli526x_reuse_buf(rxptr);
593
594 } else {
595 /* Reuse SKB buffer when the packet is error */
596 printf("Reuse buffer, rdes0");
597 uli526x_reuse_buf(rxptr);
598 }
599 }
600
601 rxptr = rxptr->next_rx_desc;
602 }
603
604 db->rx_ready_ptr = rxptr;
605 return rxlen;
606}
607
608/*
609 * Reuse the RX buffer
610 */
611
612static void uli526x_reuse_buf(struct rx_desc *rxptr)
613{
614
615 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000)))
616 rxptr->rdes0 = cpu_to_le32(0x80000000);
617 else
618 printf("Buffer reuse method error");
619}
620/*
621 * Initialize transmit/Receive descriptor
622 * Using Chain structure, and allocate Tx/Rx buffer
623 */
624
625static void uli526x_descriptor_init(struct uli526x_board_info *db,
626 unsigned long ioaddr)
627{
628 struct tx_desc *tmp_tx;
629 struct rx_desc *tmp_rx;
630 unsigned char *tmp_buf;
631 dma_addr_t tmp_tx_dma, tmp_rx_dma;
632 dma_addr_t tmp_buf_dma;
633 int i;
634 /* tx descriptor start pointer */
635 db->tx_insert_ptr = db->first_tx_desc;
636 db->tx_remove_ptr = db->first_tx_desc;
637
638 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
639
640 /* rx descriptor start pointer */
641 db->first_rx_desc = (void *)db->first_tx_desc +
642 sizeof(struct tx_desc) * TX_DESC_CNT;
643 db->first_rx_desc_dma = db->first_tx_desc_dma +
644 sizeof(struct tx_desc) * TX_DESC_CNT;
645 db->rx_ready_ptr = db->first_rx_desc;
646 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
647#ifdef DEBUG
648 printf("%s(): db->first_tx_desc= 0x%x\n",
649 __FUNCTION__, db->first_tx_desc);
650 printf("%s(): db->first_rx_desc_dma= 0x%x\n",
651 __FUNCTION__, db->first_rx_desc_dma);
652#endif
653 /* Init Transmit chain */
654 tmp_buf = db->buf_pool_start;
655 tmp_buf_dma = db->buf_pool_dma_start;
656 tmp_tx_dma = db->first_tx_desc_dma;
657 for (tmp_tx = db->first_tx_desc, i = 0;
658 i < TX_DESC_CNT; i++, tmp_tx++) {
e845e07e 659 tmp_tx->tx_buf_ptr = (char *)tmp_buf;
1f103105
RZ		 660 tmp_tx->tdes0 = cpu_to_le32(0);
661 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
662 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
663 tmp_tx_dma += sizeof(struct tx_desc);
664 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
665 tmp_tx->next_tx_desc = tmp_tx + 1;
666 tmp_buf = tmp_buf + TX_BUF_ALLOC;
667 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
668 }
669 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
670 tmp_tx->next_tx_desc = db->first_tx_desc;
671
672 /* Init Receive descriptor chain */
673 tmp_rx_dma = db->first_rx_desc_dma;
674 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT;
675 i++, tmp_rx++) {
676 tmp_rx->rdes0 = cpu_to_le32(0);
677 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
678 tmp_rx_dma += sizeof(struct rx_desc);
679 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
680 tmp_rx->next_rx_desc = tmp_rx + 1;
681 }
682 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
683 tmp_rx->next_rx_desc = db->first_rx_desc;
684
685 /* pre-allocate Rx buffer */
686 allocate_rx_buffer(db);
687}
688
689/*
690 * Update CR6 value
691 * Firstly stop ULI526X, then written value and start
692 */
693
694static void update_cr6(u32 cr6_data, unsigned long ioaddr)
695{
696
697 outl(cr6_data, ioaddr + DCR6);
698 udelay(5);
699}
700
701/*
702 * Allocate rx buffer,
703 */
704
705static void allocate_rx_buffer(struct uli526x_board_info *db)
706{
707 int index;
708 struct rx_desc *rxptr;
709 rxptr = db->first_rx_desc;
710 u32 addr;
711
712 for (index = 0; index < RX_DESC_CNT; index++) {
713 addr = (u32)NetRxPackets[index];
714 addr += (16 - (addr & 15));
715 rxptr->rx_buf_ptr = (char *) addr;
716 rxptr->rdes2 = cpu_to_le32(addr);
717 rxptr->rdes0 = cpu_to_le32(0x80000000);
718#ifdef DEBUG
719 printf("%s(): Number 0x%x:\n", __FUNCTION__, index);
720 printf("%s(): addr 0x%x:\n", __FUNCTION__, addr);
721 printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr);
722 printf("%s(): rxptr buf address = 0x%x\n", \
723 __FUNCTION__, rxptr->rx_buf_ptr);
724 printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2);
725#endif
726 rxptr = rxptr->next_rx_desc;
727 }
728}
729
730/*
731 * Read one word data from the serial ROM
732 */
733
734static u16 read_srom_word(long ioaddr, int offset)
735{
736 int i;
737 u16 srom_data = 0;
738 long cr9_ioaddr = ioaddr + DCR9;
739
740 outl(CR9_SROM_READ, cr9_ioaddr);
741 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
742
743 /* Send the Read Command 110b */
744 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
745 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
746 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
747
748 /* Send the offset */
749 for (i = 5; i >= 0; i--) {
750 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
751 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
752 }
753
754 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
755
756 for (i = 16; i > 0; i--) {
757 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
758 udelay(5);
759 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT)
760 ? 1 : 0);
761 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
762 udelay(5);
763 }
764
765 outl(CR9_SROM_READ, cr9_ioaddr);
766 return srom_data;
767}
768
769/*
770 * Set 10/100 phyxcer capability
771 * AUTO mode : phyxcer register4 is NIC capability
772 * Force mode: phyxcer register4 is the force media
773 */
774
775static void uli526x_set_phyxcer(struct uli526x_board_info *db)
776{
777 u16 phy_reg;
778
779 /* Phyxcer capability setting */
780 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
781
782 if (db->media_mode & ULI526X_AUTO) {
783 /* AUTO Mode */
784 phy_reg |= db->PHY_reg4;
785 } else {
786 /* Force Mode */
787 switch (db->media_mode) {
788 case ULI526X_10MHF: phy_reg |= 0x20; break;
789 case ULI526X_10MFD: phy_reg |= 0x40; break;
790 case ULI526X_100MHF: phy_reg |= 0x80; break;
791 case ULI526X_100MFD: phy_reg |= 0x100; break;
792 }
793
794 }
795
796 /* Write new capability to Phyxcer Reg4 */
797 if (!(phy_reg & 0x01e0)) {
798 phy_reg |= db->PHY_reg4;
799 db->media_mode |= ULI526X_AUTO;
800 }
801 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
802
803 /* Restart Auto-Negotiation */
804 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
805 udelay(50);
806}
807
808/*
809 * Write a word to Phy register
810 */
811
812static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
813 u16 phy_data, u32 chip_id)
814{
815 u16 i;
816 unsigned long ioaddr;
817
818 if (chip_id == PCI_ULI5263_ID) {
819 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
820 return;
821 }
822 /* M5261/M5263 Chip */
823 ioaddr = iobase + DCR9;
824
825 /* Send 33 synchronization clock to Phy controller */
826 for (i = 0; i < 35; i++)
827 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
828
829 /* Send start command(01) to Phy */
830 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
831 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
832
833 /* Send write command(01) to Phy */
834 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
835 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
836
837 /* Send Phy address */
838 for (i = 0x10; i > 0; i = i >> 1)
839 phy_write_1bit(ioaddr, phy_addr & i ?
840 PHY_DATA_1 : PHY_DATA_0, chip_id);
841
842 /* Send register address */
843 for (i = 0x10; i > 0; i = i >> 1)
844 phy_write_1bit(ioaddr, offset & i ?
845 PHY_DATA_1 : PHY_DATA_0, chip_id);
846
847 /* written trasnition */
848 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
849 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
850
851 /* Write a word data to PHY controller */
852 for (i = 0x8000; i > 0; i >>= 1)
853 phy_write_1bit(ioaddr, phy_data & i ?
854 PHY_DATA_1 : PHY_DATA_0, chip_id);
855}
856
857/*
858 * Read a word data from phy register
859 */
860
861static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
862{
863 int i;
864 u16 phy_data;
865 unsigned long ioaddr;
866
867 if (chip_id == PCI_ULI5263_ID)
868 return phy_readby_cr10(iobase, phy_addr, offset);
869 /* M5261/M5263 Chip */
870 ioaddr = iobase + DCR9;
871
872 /* Send 33 synchronization clock to Phy controller */
873 for (i = 0; i < 35; i++)
874 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
875
876 /* Send start command(01) to Phy */
877 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
878 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
879
880 /* Send read command(10) to Phy */
881 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
882 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
883
884 /* Send Phy address */
885 for (i = 0x10; i > 0; i = i >> 1)
886 phy_write_1bit(ioaddr, phy_addr & i ?
887 PHY_DATA_1 : PHY_DATA_0, chip_id);
888
889 /* Send register address */
890 for (i = 0x10; i > 0; i = i >> 1)
891 phy_write_1bit(ioaddr, offset & i ?
892 PHY_DATA_1 : PHY_DATA_0, chip_id);
893
894 /* Skip transition state */
895 phy_read_1bit(ioaddr, chip_id);
896
897 /* read 16bit data */
898 for (phy_data = 0, i = 0; i < 16; i++) {
899 phy_data <<= 1;
900 phy_data |= phy_read_1bit(ioaddr, chip_id);
901 }
902
903 return phy_data;
904}
905
906static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
907{
908 unsigned long ioaddr, cr10_value;
909
910 ioaddr = iobase + DCR10;
911 cr10_value = phy_addr;
912 cr10_value = (cr10_value<<5) + offset;
913 cr10_value = (cr10_value<<16) + 0x08000000;
914 outl(cr10_value, ioaddr);
915 udelay(1);
916 while (1) {
917 cr10_value = inl(ioaddr);
918 if (cr10_value & 0x10000000)
919 break;
920 }
921 return (cr10_value&0x0ffff);
922}
923
924static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr,
925 u8 offset, u16 phy_data)
926{
927 unsigned long ioaddr, cr10_value;
928
929 ioaddr = iobase + DCR10;
930 cr10_value = phy_addr;
931 cr10_value = (cr10_value<<5) + offset;
932 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
933 outl(cr10_value, ioaddr);
934 udelay(1);
935}
936/*
937 * Write one bit data to Phy Controller
938 */
939
940static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
941{
942 outl(phy_data , ioaddr); /* MII Clock Low */
943 udelay(1);
944 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
945 udelay(1);
946 outl(phy_data , ioaddr); /* MII Clock Low */
947 udelay(1);
948}
949
950/*
951 * Read one bit phy data from PHY controller
952 */
953
954static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
955{
956 u16 phy_data;
957
958 outl(0x50000 , ioaddr);
959 udelay(1);
960 phy_data = (inl(ioaddr) >> 19) & 0x1;
961 outl(0x40000 , ioaddr);
962 udelay(1);
963
964 return phy_data;
965}
966
967/*
968 * Set MAC address to ID Table
969 */
970
971static void set_mac_addr(struct eth_device *dev)
972{
973 int i;
974 u16 addr;
975 struct uli526x_board_info *db = dev->priv;
976 outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */
977 /* Reset dianostic pointer port */
978 outl(0x1c0, db->ioaddr + DCR13);
979 outl(0, db->ioaddr + DCR14); /* Clear reset port */
980 outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */
981 outl(0, db->ioaddr + DCR14); /* Clear reset port */
982 outl(0, db->ioaddr + DCR13); /* Clear CR13 */
983 /* Select ID Table access port */
984 outl(0x1b0, db->ioaddr + DCR13);
985 /* Read MAC address from CR14 */
986 for (i = 0; i < 3; i++) {
987 addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8);
988 outl(addr, db->ioaddr + DCR14);
989 }
990 /* write end */
991 outl(0, db->ioaddr + DCR13); /* Clear CR13 */
992 outl(0, db->ioaddr + DCR0); /* Clear CR0 */
993 udelay(10);
994 return;
995}
996#endif
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