[people/ms/u-boot.git] / drivers / net / xilinx_emaclite.c

/*
 * (C) Copyright 2007-2009 Michal Simek
 * (C) Copyright 2003 Xilinx Inc.
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <net.h>
#include <config.h>
#include <console.h>
#include <malloc.h>
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
#include <fdtdec.h>
#include <asm-generic/errno.h>

#undef DEBUG

#define ENET_ADDR_LENGTH	6

/* EmacLite constants */
#define XEL_BUFFER_OFFSET	0x0800	/* Next buffer's offset */
#define XEL_TPLR_OFFSET		0x07F4	/* Tx packet length */
#define XEL_TSR_OFFSET		0x07FC	/* Tx status */
#define XEL_RSR_OFFSET		0x17FC	/* Rx status */
#define XEL_RXBUFF_OFFSET	0x1000	/* Receive Buffer */

/* Xmit complete */
#define XEL_TSR_XMIT_BUSY_MASK		0x00000001UL
/* Xmit interrupt enable bit */
#define XEL_TSR_XMIT_IE_MASK		0x00000008UL
/* Buffer is active, SW bit only */
#define XEL_TSR_XMIT_ACTIVE_MASK	0x80000000UL
/* Program the MAC address */
#define XEL_TSR_PROGRAM_MASK		0x00000002UL
/* define for programming the MAC address into the EMAC Lite */
#define XEL_TSR_PROG_MAC_ADDR	(XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)

/* Transmit packet length upper byte */
#define XEL_TPLR_LENGTH_MASK_HI		0x0000FF00UL
/* Transmit packet length lower byte */
#define XEL_TPLR_LENGTH_MASK_LO		0x000000FFUL

/* Recv complete */
#define XEL_RSR_RECV_DONE_MASK		0x00000001UL
/* Recv interrupt enable bit */
#define XEL_RSR_RECV_IE_MASK		0x00000008UL

/* MDIO Address Register Bit Masks */
#define XEL_MDIOADDR_REGADR_MASK  0x0000001F	/* Register Address */
#define XEL_MDIOADDR_PHYADR_MASK  0x000003E0	/* PHY Address */
#define XEL_MDIOADDR_PHYADR_SHIFT 5
#define XEL_MDIOADDR_OP_MASK	  0x00000400	/* RD/WR Operation */

/* MDIO Write Data Register Bit Masks */
#define XEL_MDIOWR_WRDATA_MASK	  0x0000FFFF	/* Data to be Written */

/* MDIO Read Data Register Bit Masks */
#define XEL_MDIORD_RDDATA_MASK	  0x0000FFFF	/* Data to be Read */

/* MDIO Control Register Bit Masks */
#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001	/* MDIO Status Mask */
#define XEL_MDIOCTRL_MDIOEN_MASK  0x00000008	/* MDIO Enable */

struct emaclite_regs {
	u32 tx_ping; /* 0x0 - TX Ping buffer */
	u32 reserved1[504];
	u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
	u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
	u32 mdiord;/* 0x7ec - MDIO Read Data Register */
	u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
	u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
	u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
	u32 tx_ping_tsr; /* 0x7fc - Tx status */
	u32 tx_pong; /* 0x800 - TX Pong buffer */
	u32 reserved2[508];
	u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
	u32 reserved3; /* 0xff8 */
	u32 tx_pong_tsr; /* 0xffc - Tx status */
	u32 rx_ping; /* 0x1000 - Receive Buffer */
	u32 reserved4[510];
	u32 rx_ping_rsr; /* 0x17fc - Rx status */
	u32 rx_pong; /* 0x1800 - Receive Buffer */
	u32 reserved5[510];
	u32 rx_pong_rsr; /* 0x1ffc - Rx status */
};

struct xemaclite {
	u32 nexttxbuffertouse;	/* Next TX buffer to write to */
	u32 nextrxbuffertouse;	/* Next RX buffer to read from */
	u32 txpp;		/* TX ping pong buffer */
	u32 rxpp;		/* RX ping pong buffer */
	int phyaddr;
	struct emaclite_regs *regs;
	struct phy_device *phydev;
	struct mii_dev *bus;
};

static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */

static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
{
	u32 i;
	u32 alignbuffer;
	u32 *to32ptr;
	u32 *from32ptr;
	u8 *to8ptr;
	u8 *from8ptr;

	from32ptr = (u32 *) srcptr;

	/* Word aligned buffer, no correction needed. */
	to32ptr = (u32 *) destptr;
	while (bytecount > 3) {
		*to32ptr++ = *from32ptr++;
		bytecount -= 4;
	}
	to8ptr = (u8 *) to32ptr;

	alignbuffer = *from32ptr++;
	from8ptr = (u8 *) &alignbuffer;

	for (i = 0; i < bytecount; i++)
		*to8ptr++ = *from8ptr++;
}

static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
{
	u32 i;
	u32 alignbuffer;
	u32 *to32ptr = (u32 *) destptr;
	u32 *from32ptr;
	u8 *to8ptr;
	u8 *from8ptr;

	from32ptr = (u32 *) srcptr;
	while (bytecount > 3) {

		*to32ptr++ = *from32ptr++;
		bytecount -= 4;
	}

	alignbuffer = 0;
	to8ptr = (u8 *) &alignbuffer;
	from8ptr = (u8 *) from32ptr;

	for (i = 0; i < bytecount; i++)
		*to8ptr++ = *from8ptr++;

	*to32ptr++ = alignbuffer;
}

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
			bool set, unsigned int timeout)
{
	u32 val;
	unsigned long start = get_timer(0);

	while (1) {
		val = readl(reg);

		if (!set)
			val = ~val;

		if ((val & mask) == mask)
			return 0;

		if (get_timer(start) > timeout)
			break;

		if (ctrlc()) {
			puts("Abort\n");
			return -EINTR;
		}

		udelay(1);
	}

	debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
	      func, reg, mask, set);

	return -ETIMEDOUT;
}

static int mdio_wait(struct emaclite_regs *regs)
{
	return wait_for_bit(__func__, &regs->mdioctrl,
			    XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
}

static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
		   u16 *data)
{
	struct emaclite_regs *regs = emaclite->regs;

	if (mdio_wait(regs))
		return 1;

	u32 ctrl_reg = in_be32(&regs->mdioctrl);
	out_be32(&regs->mdioaddr, XEL_MDIOADDR_OP_MASK |
		 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
	out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);

	if (mdio_wait(regs))
		return 1;

	/* Read data */
	*data = in_be32(&regs->mdiord);
	return 0;
}

static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
		    u16 data)
{
	struct emaclite_regs *regs = emaclite->regs;

	if (mdio_wait(regs))
		return 1;

	/*
	 * Write the PHY address, register number and clear the OP bit in the
	 * MDIO Address register and then write the value into the MDIO Write
	 * Data register. Finally, set the Status bit in the MDIO Control
	 * register to start a MDIO write transaction.
	 */
	u32 ctrl_reg = in_be32(&regs->mdioctrl);
	out_be32(&regs->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
		 ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) | registernum));
	out_be32(&regs->mdiowr, data);
	out_be32(&regs->mdioctrl, ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK);

	if (mdio_wait(regs))
		return 1;

	return 0;
}
#endif

static void emaclite_halt(struct eth_device *dev)
{
	debug("eth_halt\n");
}

/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG  1

/* Mask used to verify certain PHY features (or register contents)
 * in the register above:
 *  0x1000: 10Mbps full duplex support
 *  0x0800: 10Mbps half duplex support
 *  0x0008: Auto-negotiation support
 */
#define PHY_DETECT_MASK 0x1808

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
static int setup_phy(struct eth_device *dev)
{
	int i;
	u16 phyreg;
	struct xemaclite *emaclite = dev->priv;
	struct phy_device *phydev;

	u32 supported = SUPPORTED_10baseT_Half |
			SUPPORTED_10baseT_Full |
			SUPPORTED_100baseT_Half |
			SUPPORTED_100baseT_Full;

	if (emaclite->phyaddr != -1) {
		phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
		if ((phyreg != 0xFFFF) &&
		    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
			/* Found a valid PHY address */
			debug("Default phy address %d is valid\n",
			      emaclite->phyaddr);
		} else {
			debug("PHY address is not setup correctly %d\n",
			      emaclite->phyaddr);
			emaclite->phyaddr = -1;
		}
	}

	if (emaclite->phyaddr == -1) {
		/* detect the PHY address */
		for (i = 31; i >= 0; i--) {
			phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
			if ((phyreg != 0xFFFF) &&
			    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
				/* Found a valid PHY address */
				emaclite->phyaddr = i;
				debug("emaclite: Found valid phy address, %d\n",
				      i);
				break;
			}
		}
	}

	/* interface - look at tsec */
	phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
			     PHY_INTERFACE_MODE_MII);
	/*
	 * Phy can support 1000baseT but device NOT that's why phydev->supported
	 * must be setup for 1000baseT. phydev->advertising setups what speeds
	 * will be used for autonegotiation where 1000baseT must be disabled.
	 */
	phydev->supported = supported | SUPPORTED_1000baseT_Half |
						SUPPORTED_1000baseT_Full;
	phydev->advertising = supported;
	emaclite->phydev = phydev;
	phy_config(phydev);
	phy_startup(phydev);

	if (!phydev->link) {
		printf("%s: No link.\n", phydev->dev->name);
		return 0;
	}

	/* Do not setup anything */
	return 1;
}
#endif

static int emaclite_init(struct eth_device *dev, bd_t *bis)
{
	struct xemaclite *emaclite = dev->priv;
	struct emaclite_regs *regs = emaclite->regs;

	debug("EmacLite Initialization Started\n");

/*
 * TX - TX_PING & TX_PONG initialization
 */
	/* Restart PING TX */
	out_be32(&regs->tx_ping_tsr, 0);
	/* Copy MAC address */
	xemaclite_alignedwrite(dev->enetaddr, (u32)&regs->tx_ping,
			       ENET_ADDR_LENGTH);
	/* Set the length */
	out_be32(&regs->tx_ping_tplr, ENET_ADDR_LENGTH);
	/* Update the MAC address in the EMAC Lite */
	out_be32(&regs->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
	/* Wait for EMAC Lite to finish with the MAC address update */
	while ((in_be32 (&regs->tx_ping_tsr) &
		XEL_TSR_PROG_MAC_ADDR) != 0)
		;

	if (emaclite->txpp) {
		/* The same operation with PONG TX */
		out_be32(&regs->tx_pong_tsr, 0);
		xemaclite_alignedwrite(dev->enetaddr, (u32)&regs->tx_pong,
				       ENET_ADDR_LENGTH);
		out_be32(&regs->tx_pong_tplr, ENET_ADDR_LENGTH);
		out_be32(&regs->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
		while ((in_be32(&regs->tx_pong_tsr) &
		       XEL_TSR_PROG_MAC_ADDR) != 0)
			;
	}

/*
 * RX - RX_PING & RX_PONG initialization
 */
	/* Write out the value to flush the RX buffer */
	out_be32(&regs->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);

	if (emaclite->rxpp)
		out_be32(&regs->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
	out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
	if (in_be32(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
		if (!setup_phy(dev))
			return -1;
#endif
	debug("EmacLite Initialization complete\n");
	return 0;
}

static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
{
	u32 tmp;
	struct emaclite_regs *regs = emaclite->regs;

	/*
	 * Read the other buffer register
	 * and determine if the other buffer is available
	 */
	tmp = ~in_be32(&regs->tx_ping_tsr);
	if (emaclite->txpp)
		tmp |= ~in_be32(&regs->tx_pong_tsr);

	return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
}

static int emaclite_send(struct eth_device *dev, void *ptr, int len)
{
	u32 reg;
	u32 baseaddress;
	struct xemaclite *emaclite = dev->priv;
	struct emaclite_regs *regs = emaclite->regs;

	u32 maxtry = 1000;

	if (len > PKTSIZE)
		len = PKTSIZE;

	while (xemaclite_txbufferavailable(emaclite) && maxtry) {
		udelay(10);
		maxtry--;
	}

	if (!maxtry) {
		printf("Error: Timeout waiting for ethernet TX buffer\n");
		/* Restart PING TX */
		out_be32(&regs->tx_ping_tsr, 0);
		if (emaclite->txpp) {
			out_be32(&regs->tx_pong_tsr, 0);
		}
		return -1;
	}

	/* Determine the expected TX buffer address */
	baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);

	/* Determine if the expected buffer address is empty */
	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
		&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
			& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {

		if (emaclite->txpp)
			emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;

		debug("Send packet from 0x%x\n", baseaddress);
		/* Write the frame to the buffer */
		xemaclite_alignedwrite(ptr, baseaddress, len);
		out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
			(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
		reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
		reg |= XEL_TSR_XMIT_BUSY_MASK;
		if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
			reg |= XEL_TSR_XMIT_ACTIVE_MASK;
		out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
		return 0;
	}

	if (emaclite->txpp) {
		/* Switch to second buffer */
		baseaddress ^= XEL_BUFFER_OFFSET;
		/* Determine if the expected buffer address is empty */
		reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
		if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
			&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
				& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
			debug("Send packet from 0x%x\n", baseaddress);
			/* Write the frame to the buffer */
			xemaclite_alignedwrite(ptr, baseaddress, len);
			out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
				(XEL_TPLR_LENGTH_MASK_HI |
					XEL_TPLR_LENGTH_MASK_LO)));
			reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
			reg |= XEL_TSR_XMIT_BUSY_MASK;
			if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
				reg |= XEL_TSR_XMIT_ACTIVE_MASK;
			out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
			return 0;
		}
	}

	puts("Error while sending frame\n");
	return -1;
}

static int emaclite_recv(struct eth_device *dev)
{
	u32 length;
	u32 reg;
	u32 baseaddress;
	struct xemaclite *emaclite = dev->priv;

	baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	debug("Testing data at address 0x%x\n", baseaddress);
	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
		if (emaclite->rxpp)
			emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
	} else {

		if (!emaclite->rxpp) {
			debug("No data was available - address 0x%x\n",
								baseaddress);
			return 0;
		} else {
			baseaddress ^= XEL_BUFFER_OFFSET;
			reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
			if ((reg & XEL_RSR_RECV_DONE_MASK) !=
						XEL_RSR_RECV_DONE_MASK) {
				debug("No data was available - address 0x%x\n",
						baseaddress);
				return 0;
			}
		}
	}
	/* Get the length of the frame that arrived */
	switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
			0xFFFF0000 ) >> 16) {
		case 0x806:
			length = 42 + 20; /* FIXME size of ARP */
			debug("ARP Packet\n");
			break;
		case 0x800:
			length = 14 + 14 +
			(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
						0x10))) & 0xFFFF0000) >> 16);
			/* FIXME size of IP packet */
			debug ("IP Packet\n");
			break;
		default:
			debug("Other Packet\n");
			length = PKTSIZE;
			break;
	}

	xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
			etherrxbuff, length);

	/* Acknowledge the frame */
	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	reg &= ~XEL_RSR_RECV_DONE_MASK;
	out_be32 (baseaddress + XEL_RSR_OFFSET, reg);

	debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
	net_process_received_packet((uchar *)etherrxbuff, length);
	return length;

}

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
static int emaclite_miiphy_read(const char *devname, uchar addr,
				uchar reg, ushort *val)
{
	u32 ret;
	struct eth_device *dev = eth_get_dev();

	ret = phyread(dev->priv, addr, reg, val);
	debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val);
	return ret;
}

static int emaclite_miiphy_write(const char *devname, uchar addr,
				 uchar reg, ushort val)
{
	struct eth_device *dev = eth_get_dev();

	debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
	return phywrite(dev->priv, addr, reg, val);
}
#endif

int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
							int txpp, int rxpp)
{
	struct eth_device *dev;
	struct xemaclite *emaclite;
	struct emaclite_regs *regs;

	dev = calloc(1, sizeof(*dev));
	if (dev == NULL)
		return -1;

	emaclite = calloc(1, sizeof(struct xemaclite));
	if (emaclite == NULL) {
		free(dev);
		return -1;
	}

	dev->priv = emaclite;

	emaclite->txpp = txpp;
	emaclite->rxpp = rxpp;

	sprintf(dev->name, "Xelite.%lx", base_addr);

	emaclite->regs = (struct emaclite_regs *)base_addr;
	regs = emaclite->regs;
	dev->iobase = base_addr;
	dev->init = emaclite_init;
	dev->halt = emaclite_halt;
	dev->send = emaclite_send;
	dev->recv = emaclite_recv;

#ifdef CONFIG_PHY_ADDR
	emaclite->phyaddr = CONFIG_PHY_ADDR;
#else
	emaclite->phyaddr = -1;
#endif

	eth_register(dev);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
	miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write);
	emaclite->bus = miiphy_get_dev_by_name(dev->name);

	out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
#endif

	return 1;
}
Commit	Line	Data
78d19a39 MS	1	/*
	2	* (C) Copyright 2007-2009 Michal Simek
	3	* (C) Copyright 2003 Xilinx Inc.
89c53891	4	*
89c53891 MS	5	* Michal SIMEK <monstr@monstr.eu>
89c53891 MS	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
78d19a39	8	*/
89c53891 MS	9
	10	#include <common.h>
	11	#include <net.h>
	12	#include <config.h>
d722e864	13	#include <console.h>
042272a6	14	#include <malloc.h>
89c53891	15	#include <asm/io.h>
d722e864 MS	16	#include <phy.h>
d722e864 MS	17	#include <miiphy.h>
7fd70820	18	#include <fdtdec.h>
d722e864	19	#include <asm-generic/errno.h>
7fd70820	20
89c53891 MS	21	#undef DEBUG
89c53891 MS	22
89c53891 MS	23	#define ENET_ADDR_LENGTH 6
	24
	25	/* EmacLite constants */
	26	#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
	27	#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
	28	#define XEL_TSR_OFFSET 0x07FC /* Tx status */
	29	#define XEL_RSR_OFFSET 0x17FC /* Rx status */
	30	#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
	31
	32	/* Xmit complete */
	33	#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
	34	/* Xmit interrupt enable bit */
	35	#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
	36	/* Buffer is active, SW bit only */
	37	#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
	38	/* Program the MAC address */
	39	#define XEL_TSR_PROGRAM_MASK 0x00000002UL
	40	/* define for programming the MAC address into the EMAC Lite */
	41	#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK \| XEL_TSR_PROGRAM_MASK)
	42
	43	/* Transmit packet length upper byte */
	44	#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
	45	/* Transmit packet length lower byte */
	46	#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
	47
	48	/* Recv complete */
	49	#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
	50	/* Recv interrupt enable bit */
	51	#define XEL_RSR_RECV_IE_MASK 0x00000008UL
	52
d722e864 MS	53	/* MDIO Address Register Bit Masks */
	54	#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
	55	#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
	56	#define XEL_MDIOADDR_PHYADR_SHIFT 5
	57	#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
	58
	59	/* MDIO Write Data Register Bit Masks */
	60	#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
	61
	62	/* MDIO Read Data Register Bit Masks */
	63	#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
	64
	65	/* MDIO Control Register Bit Masks */
	66	#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
	67	#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
	68
9a23c496 MS	69	struct emaclite_regs {
	70	u32 tx_ping; /* 0x0 - TX Ping buffer */
	71	u32 reserved1[504];
	72	u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
	73	u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
	74	u32 mdiord;/* 0x7ec - MDIO Read Data Register */
	75	u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
	76	u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
	77	u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
	78	u32 tx_ping_tsr; /* 0x7fc - Tx status */
	79	u32 tx_pong; /* 0x800 - TX Pong buffer */
	80	u32 reserved2[508];
	81	u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
	82	u32 reserved3; /* 0xff8 */
	83	u32 tx_pong_tsr; /* 0xffc - Tx status */
	84	u32 rx_ping; /* 0x1000 - Receive Buffer */
	85	u32 reserved4[510];
	86	u32 rx_ping_rsr; /* 0x17fc - Rx status */
	87	u32 rx_pong; /* 0x1800 - Receive Buffer */
	88	u32 reserved5[510];
	89	u32 rx_pong_rsr; /* 0x1ffc - Rx status */
	90	};
	91
773cfa8d	92	struct xemaclite {
042272a6 MS	93	u32 nexttxbuffertouse; /* Next TX buffer to write to */
042272a6 MS	94	u32 nextrxbuffertouse; /* Next RX buffer to read from */
947324b9 MS	95	u32 txpp; /* TX ping pong buffer */
947324b9 MS	96	u32 rxpp; /* RX ping pong buffer */
d722e864	97	int phyaddr;
9a23c496	98	struct emaclite_regs *regs;
d722e864 MS	99	struct phy_device *phydev;
d722e864 MS	100	struct mii_dev *bus;
773cfa8d	101	};
89c53891	102
f2a7806f	103	static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
89c53891	104
5ac83801	105	static void xemaclite_alignedread(u32 srcptr, void destptr, u32 bytecount)
89c53891	106	{
042272a6	107	u32 i;
89c53891 MS	108	u32 alignbuffer;
	109	u32 *to32ptr;
	110	u32 *from32ptr;
	111	u8 *to8ptr;
	112	u8 *from8ptr;
	113
	114	from32ptr = (u32 *) srcptr;
	115
	116	/* Word aligned buffer, no correction needed. */
	117	to32ptr = (u32 *) destptr;
	118	while (bytecount > 3) {
	119	to32ptr++ = from32ptr++;
	120	bytecount -= 4;
	121	}
	122	to8ptr = (u8 *) to32ptr;
	123
	124	alignbuffer = *from32ptr++;
5ac83801	125	from8ptr = (u8 *) &alignbuffer;
89c53891	126
5ac83801	127	for (i = 0; i < bytecount; i++)
89c53891	128	to8ptr++ = from8ptr++;
89c53891 MS	129	}
89c53891 MS	130
5ac83801	131	static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
89c53891	132	{
042272a6	133	u32 i;
89c53891 MS	134	u32 alignbuffer;
	135	u32 to32ptr = (u32 ) destptr;
	136	u32 *from32ptr;
	137	u8 *to8ptr;
	138	u8 *from8ptr;
	139
	140	from32ptr = (u32 *) srcptr;
	141	while (bytecount > 3) {
	142
	143	to32ptr++ = from32ptr++;
	144	bytecount -= 4;
	145	}
	146
	147	alignbuffer = 0;
5ac83801	148	to8ptr = (u8 *) &alignbuffer;
89c53891 MS	149	from8ptr = (u8 *) from32ptr;
89c53891 MS	150
5ac83801	151	for (i = 0; i < bytecount; i++)
89c53891	152	to8ptr++ = from8ptr++;
89c53891 MS	153
	154	*to32ptr++ = alignbuffer;
	155	}
	156
d722e864 MS	157	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII) \|\| defined(CONFIG_PHYLIB)
	158	static int wait_for_bit(const char func, u32 reg, const u32 mask,
	159	bool set, unsigned int timeout)
	160	{
	161	u32 val;
	162	unsigned long start = get_timer(0);
	163
	164	while (1) {
	165	val = readl(reg);
	166
	167	if (!set)
	168	val = ~val;
	169
	170	if ((val & mask) == mask)
	171	return 0;
	172
	173	if (get_timer(start) > timeout)
	174	break;
	175
	176	if (ctrlc()) {
	177	puts("Abort\n");
	178	return -EINTR;
	179	}
	180
	181	udelay(1);
	182	}
	183
	184	debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
	185	func, reg, mask, set);
	186
	187	return -ETIMEDOUT;
	188	}
	189
9a23c496	190	static int mdio_wait(struct emaclite_regs *regs)
d722e864	191	{
9a23c496	192	return wait_for_bit(__func__, &regs->mdioctrl,
d722e864 MS	193	XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
	194	}
	195
9a23c496	196	static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
d722e864 MS	197	u16 *data)
d722e864 MS	198	{
9a23c496 MS	199	struct emaclite_regs *regs = emaclite->regs;
	200
	201	if (mdio_wait(regs))
d722e864 MS	202	return 1;
d722e864 MS	203
9a23c496 MS	204	u32 ctrl_reg = in_be32(&regs->mdioctrl);
9a23c496 MS	205	out_be32(&regs->mdioaddr, XEL_MDIOADDR_OP_MASK \|
d722e864	206	((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) \| registernum));
9a23c496	207	out_be32(&regs->mdioctrl, ctrl_reg \| XEL_MDIOCTRL_MDIOSTS_MASK);
d722e864	208
9a23c496	209	if (mdio_wait(regs))
d722e864 MS	210	return 1;
	211
	212	/* Read data */
9a23c496	213	*data = in_be32(&regs->mdiord);
d722e864 MS	214	return 0;
	215	}
	216
9a23c496	217	static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
d722e864 MS	218	u16 data)
d722e864 MS	219	{
9a23c496 MS	220	struct emaclite_regs *regs = emaclite->regs;
	221
	222	if (mdio_wait(regs))
d722e864 MS	223	return 1;
	224
	225	/*
	226	* Write the PHY address, register number and clear the OP bit in the
	227	* MDIO Address register and then write the value into the MDIO Write
	228	* Data register. Finally, set the Status bit in the MDIO Control
	229	* register to start a MDIO write transaction.
	230	*/
9a23c496 MS	231	u32 ctrl_reg = in_be32(&regs->mdioctrl);
9a23c496 MS	232	out_be32(&regs->mdioaddr, ~XEL_MDIOADDR_OP_MASK &
d722e864	233	((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT) \| registernum));
9a23c496 MS	234	out_be32(&regs->mdiowr, data);
9a23c496 MS	235	out_be32(&regs->mdioctrl, ctrl_reg \| XEL_MDIOCTRL_MDIOSTS_MASK);
d722e864	236
9a23c496	237	if (mdio_wait(regs))
d722e864 MS	238	return 1;
	239
	240	return 0;
	241	}
	242	#endif
	243
042272a6	244	static void emaclite_halt(struct eth_device *dev)
89c53891	245	{
5ac83801	246	debug("eth_halt\n");
89c53891 MS	247	}
89c53891 MS	248
d722e864 MS	249	/* Use MII register 1 (MII status register) to detect PHY */
	250	#define PHY_DETECT_REG 1
	251
	252	/* Mask used to verify certain PHY features (or register contents)
	253	* in the register above:
	254	* 0x1000: 10Mbps full duplex support
	255	* 0x0800: 10Mbps half duplex support
	256	* 0x0008: Auto-negotiation support
	257	*/
	258	#define PHY_DETECT_MASK 0x1808
	259
	260	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII) \|\| defined(CONFIG_PHYLIB)
	261	static int setup_phy(struct eth_device *dev)
	262	{
	263	int i;
	264	u16 phyreg;
	265	struct xemaclite *emaclite = dev->priv;
	266	struct phy_device *phydev;
	267
	268	u32 supported = SUPPORTED_10baseT_Half \|
	269	SUPPORTED_10baseT_Full \|
	270	SUPPORTED_100baseT_Half \|
	271	SUPPORTED_100baseT_Full;
	272
	273	if (emaclite->phyaddr != -1) {
9a23c496	274	phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
d722e864 MS	275	if ((phyreg != 0xFFFF) &&
	276	((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
	277	/* Found a valid PHY address */
	278	debug("Default phy address %d is valid\n",
	279	emaclite->phyaddr);
	280	} else {
	281	debug("PHY address is not setup correctly %d\n",
	282	emaclite->phyaddr);
	283	emaclite->phyaddr = -1;
	284	}
	285	}
	286
	287	if (emaclite->phyaddr == -1) {
	288	/* detect the PHY address */
	289	for (i = 31; i >= 0; i--) {
9a23c496	290	phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
d722e864 MS	291	if ((phyreg != 0xFFFF) &&
	292	((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
	293	/* Found a valid PHY address */
	294	emaclite->phyaddr = i;
	295	debug("emaclite: Found valid phy address, %d\n",
	296	i);
	297	break;
	298	}
	299	}
	300	}
	301
	302	/* interface - look at tsec */
	303	phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
	304	PHY_INTERFACE_MODE_MII);
	305	/*
	306	* Phy can support 1000baseT but device NOT that's why phydev->supported
	307	* must be setup for 1000baseT. phydev->advertising setups what speeds
	308	* will be used for autonegotiation where 1000baseT must be disabled.
	309	*/
	310	phydev->supported = supported \| SUPPORTED_1000baseT_Half \|
	311	SUPPORTED_1000baseT_Full;
	312	phydev->advertising = supported;
	313	emaclite->phydev = phydev;
	314	phy_config(phydev);
	315	phy_startup(phydev);
	316
	317	if (!phydev->link) {
	318	printf("%s: No link.\n", phydev->dev->name);
	319	return 0;
	320	}
	321
	322	/* Do not setup anything */
	323	return 1;
	324	}
	325	#endif
	326
042272a6	327	static int emaclite_init(struct eth_device dev, bd_t bis)
89c53891	328	{
947324b9	329	struct xemaclite *emaclite = dev->priv;
9a23c496 MS	330	struct emaclite_regs *regs = emaclite->regs;
9a23c496 MS	331
5ac83801	332	debug("EmacLite Initialization Started\n");
89c53891 MS	333
	334	/*
	335	* TX - TX_PING & TX_PONG initialization
	336	*/
	337	/* Restart PING TX */
a0b2bfb0	338	out_be32(&regs->tx_ping_tsr, 0);
89c53891	339	/* Copy MAC address */
a0b2bfb0 MS	340	xemaclite_alignedwrite(dev->enetaddr, (u32)&regs->tx_ping,
a0b2bfb0 MS	341	ENET_ADDR_LENGTH);
89c53891	342	/* Set the length */
a0b2bfb0	343	out_be32(&regs->tx_ping_tplr, ENET_ADDR_LENGTH);
89c53891	344	/* Update the MAC address in the EMAC Lite */
a0b2bfb0	345	out_be32(&regs->tx_ping_tsr, XEL_TSR_PROG_MAC_ADDR);
89c53891	346	/* Wait for EMAC Lite to finish with the MAC address update */
a0b2bfb0	347	while ((in_be32 (&regs->tx_ping_tsr) &
8d95ddbb MS	348	XEL_TSR_PROG_MAC_ADDR) != 0)
8d95ddbb MS	349	;
89c53891	350
947324b9 MS	351	if (emaclite->txpp) {
947324b9 MS	352	/* The same operation with PONG TX */
a0b2bfb0 MS	353	out_be32(&regs->tx_pong_tsr, 0);
	354	xemaclite_alignedwrite(dev->enetaddr, (u32)&regs->tx_pong,
	355	ENET_ADDR_LENGTH);
	356	out_be32(&regs->tx_pong_tplr, ENET_ADDR_LENGTH);
	357	out_be32(&regs->tx_pong_tsr, XEL_TSR_PROG_MAC_ADDR);
	358	while ((in_be32(&regs->tx_pong_tsr) &
	359	XEL_TSR_PROG_MAC_ADDR) != 0)
947324b9 MS	360	;
947324b9 MS	361	}
89c53891 MS	362
	363	/*
	364	* RX - RX_PING & RX_PONG initialization
	365	*/
	366	/* Write out the value to flush the RX buffer */
3af70909	367	out_be32(&regs->rx_ping_rsr, XEL_RSR_RECV_IE_MASK);
947324b9 MS	368
947324b9 MS	369	if (emaclite->rxpp)
3af70909	370	out_be32(&regs->rx_pong_rsr, XEL_RSR_RECV_IE_MASK);
89c53891	371
d722e864	372	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII) \|\| defined(CONFIG_PHYLIB)
9a23c496 MS	373	out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
9a23c496 MS	374	if (in_be32(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
d722e864 MS	375	if (!setup_phy(dev))
	376	return -1;
	377	#endif
5ac83801	378	debug("EmacLite Initialization complete\n");
89c53891 MS	379	return 0;
	380	}
	381
26c7945a	382	static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
89c53891	383	{
26c7945a MS	384	u32 tmp;
26c7945a MS	385	struct emaclite_regs *regs = emaclite->regs;
773cfa8d	386
89c53891 MS	387	/*
	388	* Read the other buffer register
	389	* and determine if the other buffer is available
	390	*/
26c7945a MS	391	tmp = ~in_be32(&regs->tx_ping_tsr);
	392	if (emaclite->txpp)
	393	tmp \|= ~in_be32(&regs->tx_pong_tsr);
89c53891	394
26c7945a	395	return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
89c53891 MS	396	}
89c53891 MS	397
1ae6b9c4	398	static int emaclite_send(struct eth_device dev, void ptr, int len)
042272a6 MS	399	{
	400	u32 reg;
	401	u32 baseaddress;
773cfa8d	402	struct xemaclite *emaclite = dev->priv;
5a4baa33	403	struct emaclite_regs *regs = emaclite->regs;
89c53891	404
042272a6	405	u32 maxtry = 1000;
89c53891	406
80439252 MS	407	if (len > PKTSIZE)
80439252 MS	408	len = PKTSIZE;
89c53891	409
26c7945a	410	while (xemaclite_txbufferavailable(emaclite) && maxtry) {
5ac83801	411	udelay(10);
89c53891 MS	412	maxtry--;
	413	}
	414
	415	if (!maxtry) {
5ac83801	416	printf("Error: Timeout waiting for ethernet TX buffer\n");
89c53891	417	/* Restart PING TX */
5a4baa33	418	out_be32(&regs->tx_ping_tsr, 0);
947324b9	419	if (emaclite->txpp) {
5a4baa33	420	out_be32(&regs->tx_pong_tsr, 0);
947324b9	421	}
95efa79d	422	return -1;
89c53891 MS	423	}
	424
	425	/* Determine the expected TX buffer address */
773cfa8d	426	baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
89c53891 MS	427
	428	/* Determine if the expected buffer address is empty */
	429	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	430	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
	431	&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
	432	& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
	433
947324b9 MS	434	if (emaclite->txpp)
	435	emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
	436
5ac83801	437	debug("Send packet from 0x%x\n", baseaddress);
89c53891	438	/* Write the frame to the buffer */
1ae6b9c4	439	xemaclite_alignedwrite(ptr, baseaddress, len);
89c53891 MS	440	out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
	441	(XEL_TPLR_LENGTH_MASK_HI \| XEL_TPLR_LENGTH_MASK_LO)));
	442	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	443	reg \|= XEL_TSR_XMIT_BUSY_MASK;
5ac83801	444	if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
89c53891	445	reg \|= XEL_TSR_XMIT_ACTIVE_MASK;
89c53891	446	out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
95efa79d	447	return 0;
89c53891	448	}
947324b9 MS	449
	450	if (emaclite->txpp) {
	451	/* Switch to second buffer */
	452	baseaddress ^= XEL_BUFFER_OFFSET;
	453	/* Determine if the expected buffer address is empty */
89c53891	454	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
947324b9 MS	455	if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
	456	&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
	457	& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
	458	debug("Send packet from 0x%x\n", baseaddress);
	459	/* Write the frame to the buffer */
1ae6b9c4	460	xemaclite_alignedwrite(ptr, baseaddress, len);
947324b9 MS	461	out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
	462	(XEL_TPLR_LENGTH_MASK_HI \|
	463	XEL_TPLR_LENGTH_MASK_LO)));
	464	reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
	465	reg \|= XEL_TSR_XMIT_BUSY_MASK;
	466	if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
	467	reg \|= XEL_TSR_XMIT_ACTIVE_MASK;
	468	out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
	469	return 0;
89c53891	470	}
89c53891	471	}
947324b9	472
5ac83801	473	puts("Error while sending frame\n");
95efa79d	474	return -1;
89c53891 MS	475	}
89c53891 MS	476
042272a6	477	static int emaclite_recv(struct eth_device *dev)
89c53891	478	{
042272a6 MS	479	u32 length;
	480	u32 reg;
	481	u32 baseaddress;
773cfa8d	482	struct xemaclite *emaclite = dev->priv;
89c53891	483
773cfa8d	484	baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
89c53891	485	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
5ac83801	486	debug("Testing data at address 0x%x\n", baseaddress);
89c53891	487	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
947324b9 MS	488	if (emaclite->rxpp)
947324b9 MS	489	emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
89c53891	490	} else {
947324b9 MS	491
947324b9 MS	492	if (!emaclite->rxpp) {
5ac83801	493	debug("No data was available - address 0x%x\n",
947324b9	494	baseaddress);
89c53891	495	return 0;
947324b9 MS	496	} else {
	497	baseaddress ^= XEL_BUFFER_OFFSET;
	498	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	499	if ((reg & XEL_RSR_RECV_DONE_MASK) !=
	500	XEL_RSR_RECV_DONE_MASK) {
	501	debug("No data was available - address 0x%x\n",
	502	baseaddress);
	503	return 0;
	504	}
89c53891	505	}
89c53891 MS	506	}
89c53891 MS	507	/* Get the length of the frame that arrived */
3f91ec0f	508	switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
89c53891 MS	509	0xFFFF0000 ) >> 16) {
	510	case 0x806:
	511	length = 42 + 20; /* FIXME size of ARP */
5ac83801	512	debug("ARP Packet\n");
89c53891 MS	513	break;
	514	case 0x800:
	515	length = 14 + 14 +
5ac83801 MS	516	(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
	517	0x10))) & 0xFFFF0000) >> 16);
	518	/* FIXME size of IP packet */
89c53891 MS	519	debug ("IP Packet\n");
	520	break;
	521	default:
80439252 MS	522	debug("Other Packet\n");
80439252 MS	523	length = PKTSIZE;
89c53891 MS	524	break;
	525	}
	526
5ac83801	527	xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
89c53891 MS	528	etherrxbuff, length);
	529
	530	/* Acknowledge the frame */
	531	reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
	532	reg &= ~XEL_RSR_RECV_DONE_MASK;
	533	out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
	534
5ac83801	535	debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
1fd92db8	536	net_process_received_packet((uchar *)etherrxbuff, length);
95efa79d	537	return length;
89c53891 MS	538
89c53891 MS	539	}
042272a6	540
d722e864 MS	541	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII) \|\| defined(CONFIG_PHYLIB)
	542	static int emaclite_miiphy_read(const char *devname, uchar addr,
	543	uchar reg, ushort *val)
	544	{
	545	u32 ret;
	546	struct eth_device *dev = eth_get_dev();
	547
9a23c496	548	ret = phyread(dev->priv, addr, reg, val);
d722e864 MS	549	debug("emaclite: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val);
	550	return ret;
	551	}
	552
	553	static int emaclite_miiphy_write(const char *devname, uchar addr,
	554	uchar reg, ushort val)
	555	{
	556	struct eth_device *dev = eth_get_dev();
	557
	558	debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
9a23c496	559	return phywrite(dev->priv, addr, reg, val);
d722e864 MS	560	}
	561	#endif
	562
c1044a1e MS	563	int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
c1044a1e MS	564	int txpp, int rxpp)
042272a6 MS	565	{
042272a6 MS	566	struct eth_device *dev;
773cfa8d	567	struct xemaclite *emaclite;
9a23c496	568	struct emaclite_regs *regs;
042272a6	569
28ae02e5	570	dev = calloc(1, sizeof(*dev));
042272a6	571	if (dev == NULL)
95efa79d	572	return -1;
042272a6	573
773cfa8d MS	574	emaclite = calloc(1, sizeof(struct xemaclite));
	575	if (emaclite == NULL) {
	576	free(dev);
	577	return -1;
	578	}
	579
	580	dev->priv = emaclite;
	581
c1044a1e MS	582	emaclite->txpp = txpp;
c1044a1e MS	583	emaclite->rxpp = rxpp;
947324b9	584
9b94755a	585	sprintf(dev->name, "Xelite.%lx", base_addr);
042272a6	586
9a23c496 MS	587	emaclite->regs = (struct emaclite_regs *)base_addr;
9a23c496 MS	588	regs = emaclite->regs;
042272a6	589	dev->iobase = base_addr;
042272a6 MS	590	dev->init = emaclite_init;
	591	dev->halt = emaclite_halt;
	592	dev->send = emaclite_send;
	593	dev->recv = emaclite_recv;
	594
d722e864 MS	595	#ifdef CONFIG_PHY_ADDR
	596	emaclite->phyaddr = CONFIG_PHY_ADDR;
	597	#else
	598	emaclite->phyaddr = -1;
	599	#endif
	600
042272a6 MS	601	eth_register(dev);
042272a6 MS	602
d722e864 MS	603	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII) \|\| defined(CONFIG_PHYLIB)
	604	miiphy_register(dev->name, emaclite_miiphy_read, emaclite_miiphy_write);
	605	emaclite->bus = miiphy_get_dev_by_name(dev->name);
	606
9a23c496	607	out_be32(&regs->mdioctrl, XEL_MDIOCTRL_MDIOEN_MASK);
d722e864 MS	608	#endif
d722e864 MS	609
95efa79d	610	return 1;
042272a6	611	}