[people/ms/u-boot.git] / drivers / pci / pci.c

/*
 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Andreas Heppel <aheppel@sysgo.de>
 *
 * (C) Copyright 2002, 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * PCI routines
 */

#include <common.h>

#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>

#define PCI_HOSE_OP(rw, size, type)					\
int pci_hose_##rw##_config_##size(struct pci_controller *hose,		\
				  pci_dev_t dev,			\
				  int offset, type value)		\
{									\
	return hose->rw##_##size(hose, dev, offset, value);		\
}

PCI_HOSE_OP(read, byte, u8 *)
PCI_HOSE_OP(read, word, u16 *)
PCI_HOSE_OP(read, dword, u32 *)
PCI_HOSE_OP(write, byte, u8)
PCI_HOSE_OP(write, word, u16)
PCI_HOSE_OP(write, dword, u32)

#ifndef CONFIG_IXP425
#define PCI_OP(rw, size, type, error_code)				\
int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)	\
{									\
	struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));	\
									\
	if (!hose)							\
	{								\
		error_code;						\
		return -1;						\
	}								\
									\
	return pci_hose_##rw##_config_##size(hose, dev, offset, value);	\
}

PCI_OP(read, byte, u8 *, *value = 0xff)
PCI_OP(read, word, u16 *, *value = 0xffff)
PCI_OP(read, dword, u32 *, *value = 0xffffffff)
PCI_OP(write, byte, u8, )
PCI_OP(write, word, u16, )
PCI_OP(write, dword, u32, )
#endif	/* CONFIG_IXP425 */

#define PCI_READ_VIA_DWORD_OP(size, type, off_mask)			\
int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
					pci_dev_t dev,			\
					int offset, type val)		\
{									\
	u32 val32;							\
									\
	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) {	\
		*val = -1;						\
		return -1;						\
	}								\
									\
	*val = (val32 >> ((offset & (int)off_mask) * 8));		\
									\
	return 0;							\
}

#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)		\
int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
					     pci_dev_t dev,		\
					     int offset, type val)	\
{									\
	u32 val32, mask, ldata, shift;					\
									\
	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
		return -1;						\
									\
	shift = ((offset & (int)off_mask) * 8);				\
	ldata = (((unsigned long)val) & val_mask) << shift;		\
	mask = val_mask << shift;					\
	val32 = (val32 & ~mask) | ldata;				\
									\
	if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
		return -1;						\
									\
	return 0;							\
}

PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)

/*
 *
 */

static struct pci_controller* hose_head = NULL;

void pci_register_hose(struct pci_controller* hose)
{
	struct pci_controller **phose = &hose_head;

	while(*phose)
		phose = &(*phose)->next;

	hose->next = NULL;

	*phose = hose;
}

struct pci_controller *pci_bus_to_hose (int bus)
{
	struct pci_controller *hose;

	for (hose = hose_head; hose; hose = hose->next)
		if (bus >= hose->first_busno && bus <= hose->last_busno)
			return hose;

	printf("pci_bus_to_hose() failed\n");
	return NULL;
}

#ifndef CONFIG_IXP425
pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
{
	struct pci_controller * hose;
	u16 vendor, device;
	u8 header_type;
	pci_dev_t bdf;
	int i, bus, found_multi = 0;

	for (hose = hose_head; hose; hose = hose->next)
	{
#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
		for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
#else
		for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
#endif
			for (bdf = PCI_BDF(bus,0,0);
#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
			     bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
#else
			     bdf < PCI_BDF(bus+1,0,0);
#endif
			     bdf += PCI_BDF(0,0,1))
			{
				if (!PCI_FUNC(bdf)) {
					pci_read_config_byte(bdf,
							     PCI_HEADER_TYPE,
							     &header_type);

					found_multi = header_type & 0x80;
				} else {
					if (!found_multi)
						continue;
				}

				pci_read_config_word(bdf,
						     PCI_VENDOR_ID,
						     &vendor);
				pci_read_config_word(bdf,
						     PCI_DEVICE_ID,
						     &device);

				for (i=0; ids[i].vendor != 0; i++)
					if (vendor == ids[i].vendor &&
					    device == ids[i].device)
					{
						if (index <= 0)
							return bdf;

						index--;
					}
			}
	}

	return (-1);
}
#endif	/* CONFIG_IXP425 */

pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
{
	static struct pci_device_id ids[2] = {{}, {0, 0}};

	ids[0].vendor = vendor;
	ids[0].device = device;

	return pci_find_devices(ids, index);
}

/*
 *
 */

unsigned long pci_hose_phys_to_bus (struct pci_controller *hose,
				    phys_addr_t phys_addr,
				    unsigned long flags)
{
	struct pci_region *res;
	unsigned long bus_addr;
	int i;

	if (!hose) {
		printf ("pci_hose_phys_to_bus: %s\n", "invalid hose");
		goto Done;
	}

	for (i = 0; i < hose->region_count; i++) {
		res = &hose->regions[i];

		if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
			continue;

		bus_addr = phys_addr - res->phys_start + res->bus_start;

		if (bus_addr >= res->bus_start &&
			bus_addr < res->bus_start + res->size) {
			return bus_addr;
		}
	}

	printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address");

Done:
	return 0;
}

phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
				 unsigned long bus_addr,
				 unsigned long flags)
{
	struct pci_region *res;
	int i;

	if (!hose) {
		printf ("pci_hose_bus_to_phys: %s\n", "invalid hose");
		goto Done;
	}

	for (i = 0; i < hose->region_count; i++) {
		res = &hose->regions[i];

		if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
			continue;

		if (bus_addr >= res->bus_start &&
			bus_addr < res->bus_start + res->size) {
			return bus_addr - res->bus_start + res->phys_start;
		}
	}

	printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address");

Done:
	return 0;
}

/*
 *
 */

int pci_hose_config_device(struct pci_controller *hose,
			   pci_dev_t dev,
			   unsigned long io,
			   unsigned long mem,
			   unsigned long command)
{
	unsigned int bar_response, bar_size, bar_value, old_command;
	unsigned char pin;
	int bar, found_mem64;

	debug ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
		io, mem, command);

	pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);

	for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) {
		pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
		pci_hose_read_config_dword (hose, dev, bar, &bar_response);

		if (!bar_response)
			continue;

		found_mem64 = 0;

		/* Check the BAR type and set our address mask */
		if (bar_response & PCI_BASE_ADDRESS_SPACE) {
			bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
			/* round up region base address to a multiple of size */
			io = ((io - 1) | (bar_size - 1)) + 1;
			bar_value = io;
			/* compute new region base address */
			io = io + bar_size;
		} else {
			if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
				PCI_BASE_ADDRESS_MEM_TYPE_64)
				found_mem64 = 1;

			bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;

			/* round up region base address to multiple of size */
			mem = ((mem - 1) | (bar_size - 1)) + 1;
			bar_value = mem;
			/* compute new region base address */
			mem = mem + bar_size;
		}

		/* Write it out and update our limit */
		pci_hose_write_config_dword (hose, dev, bar, bar_value);

		if (found_mem64) {
			bar += 4;
			pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
		}
	}

	/* Configure Cache Line Size Register */
	pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);

	/* Configure Latency Timer */
	pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);

	/* Disable interrupt line, if device says it wants to use interrupts */
	pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
	if (pin != 0) {
		pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
	}

	pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
	pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
				     (old_command & 0xffff0000) | command);

	return 0;
}

/*
 *
 */

struct pci_config_table *pci_find_config(struct pci_controller *hose,
					 unsigned short class,
					 unsigned int vendor,
					 unsigned int device,
					 unsigned int bus,
					 unsigned int dev,
					 unsigned int func)
{
	struct pci_config_table *table;

	for (table = hose->config_table; table && table->vendor; table++) {
		if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
		    (table->device == PCI_ANY_ID || table->device == device) &&
		    (table->class  == PCI_ANY_ID || table->class  == class)  &&
		    (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
		    (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
		    (table->func   == PCI_ANY_ID || table->func   == func)) {
			return table;
		}
	}

	return NULL;
}

void pci_cfgfunc_config_device(struct pci_controller *hose,
			       pci_dev_t dev,
			       struct pci_config_table *entry)
{
	pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
}

void pci_cfgfunc_do_nothing(struct pci_controller *hose,
			    pci_dev_t dev, struct pci_config_table *entry)
{
}

/*
 *
 */

/* HJF: Changed this to return int. I think this is required
 * to get the correct result when scanning bridges
 */
extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
extern void pciauto_config_init(struct pci_controller *hose);

int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
{
	/*
	 * Check if pci device should be skipped in configuration
	 */
	if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
#if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
		/*
		 * Only skip configuration if "pciconfighost" is not set
		 */
		if (getenv("pciconfighost") == NULL)
			return 1;
#else
		return 1;
#endif
	}

	return 0;
}
int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
	__attribute__((weak, alias("__pci_skip_dev")));

#ifdef CONFIG_PCI_SCAN_SHOW
int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
{
	if (dev == PCI_BDF(hose->first_busno, 0, 0))
		return 0;

	return 1;
}
int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
	__attribute__((weak, alias("__pci_print_dev")));
#endif /* CONFIG_PCI_SCAN_SHOW */

int pci_hose_scan_bus(struct pci_controller *hose, int bus)
{
	unsigned int sub_bus, found_multi=0;
	unsigned short vendor, device, class;
	unsigned char header_type;
	struct pci_config_table *cfg;
	pci_dev_t dev;

	sub_bus = bus;

	for (dev =  PCI_BDF(bus,0,0);
	     dev <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
	     dev += PCI_BDF(0,0,1)) {

		if (pci_skip_dev(hose, dev))
			continue;

		if (PCI_FUNC(dev) && !found_multi)
			continue;

		pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);

		pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);

		if (vendor != 0xffff && vendor != 0x0000) {

			if (!PCI_FUNC(dev))
				found_multi = header_type & 0x80;

			debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
				PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );

			pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
			pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);

			cfg = pci_find_config(hose, class, vendor, device,
					      PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
			if (cfg) {
				cfg->config_device(hose, dev, cfg);
				sub_bus = max(sub_bus, hose->current_busno);
#ifdef CONFIG_PCI_PNP
			} else {
				int n = pciauto_config_device(hose, dev);

				sub_bus = max(sub_bus, n);
#endif
			}
			if (hose->fixup_irq)
				hose->fixup_irq(hose, dev);

#ifdef CONFIG_PCI_SCAN_SHOW
			if (pci_print_dev(hose, dev)) {
				unsigned char int_line;

				pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE,
							  &int_line);
				printf("        %02x  %02x  %04x  %04x  %04x  %02x\n",
				       PCI_BUS(dev), PCI_DEV(dev), vendor, device, class,
				       int_line);
			}
#endif
		}
	}

	return sub_bus;
}

int pci_hose_scan(struct pci_controller *hose)
{
	/* Start scan at current_busno.
	 * PCIe will start scan at first_busno+1.
	 */
	/* For legacy support, ensure current>=first */
	if (hose->first_busno > hose->current_busno)
		hose->current_busno = hose->first_busno;
#ifdef CONFIG_PCI_PNP
	pciauto_config_init(hose);
#endif
	return pci_hose_scan_bus(hose, hose->current_busno);
}

void pci_init(void)
{
#if defined(CONFIG_PCI_BOOTDELAY)
	char *s;
	int i;

	/* wait "pcidelay" ms (if defined)... */
	s = getenv ("pcidelay");
	if (s) {
		int val = simple_strtoul (s, NULL, 10);
		for (i=0; i<val; i++)
			udelay (1000);
	}
#endif /* CONFIG_PCI_BOOTDELAY */

	/* now call board specific pci_init()... */
	pci_init_board();
}
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	3	* Andreas Heppel <aheppel@sysgo.de>
	4	*
f07771cc	5	* (C) Copyright 2002, 2003
c609719b WD	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	/*
	28	* PCI routines
	29	*/
	30
	31	#include <common.h>
	32
c609719b	33	#include <command.h>
c609719b WD	34	#include <asm/processor.h>
	35	#include <asm/io.h>
	36	#include <pci.h>
	37
f07771cc	38	#define PCI_HOSE_OP(rw, size, type) \
53677ef1 WD	39	int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
53677ef1 WD	40	pci_dev_t dev, \
f07771cc WD	41	int offset, type value) \
	42	{ \
	43	return hose->rw##_##size(hose, dev, offset, value); \
c609719b WD	44	}
	45
	46	PCI_HOSE_OP(read, byte, u8 *)
	47	PCI_HOSE_OP(read, word, u16 *)
	48	PCI_HOSE_OP(read, dword, u32 *)
	49	PCI_HOSE_OP(write, byte, u8)
	50	PCI_HOSE_OP(write, word, u16)
	51	PCI_HOSE_OP(write, dword, u32)
	52
a1191902	53	#ifndef CONFIG_IXP425
f07771cc WD	54	#define PCI_OP(rw, size, type, error_code) \
	55	int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
	56	{ \
	57	struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
	58	\
	59	if (!hose) \
	60	{ \
	61	error_code; \
	62	return -1; \
	63	} \
	64	\
	65	return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
c609719b WD	66	}
	67
	68	PCI_OP(read, byte, u8 , value = 0xff)
	69	PCI_OP(read, word, u16 , value = 0xffff)
	70	PCI_OP(read, dword, u32 , value = 0xffffffff)
	71	PCI_OP(write, byte, u8, )
	72	PCI_OP(write, word, u16, )
	73	PCI_OP(write, dword, u32, )
a1191902	74	#endif /* CONFIG_IXP425 */
c609719b	75
f07771cc WD	76	#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
f07771cc WD	77	int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
53677ef1	78	pci_dev_t dev, \
f07771cc WD	79	int offset, type val) \
	80	{ \
	81	u32 val32; \
	82	\
815b5bd5 SK	83	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
815b5bd5 SK	84	*val = -1; \
f07771cc	85	return -1; \
815b5bd5	86	} \
f07771cc WD	87	\
	88	val = (val32 >> ((offset & (int)off_mask) 8)); \
	89	\
	90	return 0; \
c609719b WD	91	}
c609719b WD	92
f07771cc WD	93	#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
f07771cc WD	94	int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
53677ef1	95	pci_dev_t dev, \
f07771cc WD	96	int offset, type val) \
f07771cc WD	97	{ \
498b8db7	98	u32 val32, mask, ldata, shift; \
f07771cc WD	99	\
	100	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
	101	return -1; \
	102	\
498b8db7 WD	103	shift = ((offset & (int)off_mask) * 8); \
	104	ldata = (((unsigned long)val) & val_mask) << shift; \
	105	mask = val_mask << shift; \
f07771cc WD	106	val32 = (val32 & ~mask) \| ldata; \
	107	\
	108	if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
	109	return -1; \
	110	\
	111	return 0; \
c609719b WD	112	}
	113
	114	PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
	115	PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
	116	PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
	117	PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
	118
	119	/*
	120	*
	121	*/
	122
	123	static struct pci_controller* hose_head = NULL;
	124
	125	void pci_register_hose(struct pci_controller* hose)
	126	{
	127	struct pci_controller **phose = &hose_head;
	128
	129	while(*phose)
	130	phose = &(*phose)->next;
	131
	132	hose->next = NULL;
	133
	134	*phose = hose;
	135	}
	136
f07771cc	137	struct pci_controller *pci_bus_to_hose (int bus)
c609719b WD	138	{
	139	struct pci_controller *hose;
	140
	141	for (hose = hose_head; hose; hose = hose->next)
f07771cc	142	if (bus >= hose->first_busno && bus <= hose->last_busno)
c609719b WD	143	return hose;
c609719b WD	144
6902df56	145	printf("pci_bus_to_hose() failed\n");
c609719b WD	146	return NULL;
	147	}
	148
a1191902	149	#ifndef CONFIG_IXP425
c609719b WD	150	pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
	151	{
	152	struct pci_controller * hose;
	153	u16 vendor, device;
	154	u8 header_type;
	155	pci_dev_t bdf;
	156	int i, bus, found_multi = 0;
	157
	158	for (hose = hose_head; hose; hose = hose->next)
	159	{
6d0f6bcf	160	#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
c609719b WD	161	for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
	162	#else
	163	for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
	164	#endif
	165	for (bdf = PCI_BDF(bus,0,0);
f5e0d039	166	#if defined(CONFIG_ELPPC) \|\| defined(CONFIG_PPMC7XX)
c609719b WD	167	bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
	168	#else
	169	bdf < PCI_BDF(bus+1,0,0);
	170	#endif
	171	bdf += PCI_BDF(0,0,1))
	172	{
f07771cc	173	if (!PCI_FUNC(bdf)) {
c609719b WD	174	pci_read_config_byte(bdf,
	175	PCI_HEADER_TYPE,
	176	&header_type);
	177
	178	found_multi = header_type & 0x80;
f07771cc	179	} else {
c609719b WD	180	if (!found_multi)
	181	continue;
	182	}
	183
	184	pci_read_config_word(bdf,
	185	PCI_VENDOR_ID,
	186	&vendor);
	187	pci_read_config_word(bdf,
	188	PCI_DEVICE_ID,
	189	&device);
	190
	191	for (i=0; ids[i].vendor != 0; i++)
	192	if (vendor == ids[i].vendor &&
	193	device == ids[i].device)
	194	{
	195	if (index <= 0)
	196	return bdf;
	197
	198	index--;
	199	}
	200	}
	201	}
	202
	203	return (-1);
	204	}
a1191902	205	#endif /* CONFIG_IXP425 */
c609719b WD	206
	207	pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
	208	{
	209	static struct pci_device_id ids[2] = {{}, {0, 0}};
	210
	211	ids[0].vendor = vendor;
	212	ids[0].device = device;
	213
	214	return pci_find_devices(ids, index);
	215	}
	216
	217	/*
	218	*
	219	*/
	220
f07771cc	221	unsigned long pci_hose_phys_to_bus (struct pci_controller *hose,
36f32675	222	phys_addr_t phys_addr,
f07771cc	223	unsigned long flags)
c609719b WD	224	{
	225	struct pci_region *res;
	226	unsigned long bus_addr;
	227	int i;
	228
f07771cc WD	229	if (!hose) {
f07771cc WD	230	printf ("pci_hose_phys_to_bus: %s\n", "invalid hose");
c609719b WD	231	goto Done;
	232	}
	233
f07771cc	234	for (i = 0; i < hose->region_count; i++) {
c609719b WD	235	res = &hose->regions[i];
	236
	237	if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
	238	continue;
	239
	240	bus_addr = phys_addr - res->phys_start + res->bus_start;
	241
	242	if (bus_addr >= res->bus_start &&
f07771cc	243	bus_addr < res->bus_start + res->size) {
c609719b WD	244	return bus_addr;
	245	}
	246	}
	247
f07771cc	248	printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address");
c609719b	249
f07771cc	250	Done:
c609719b WD	251	return 0;
	252	}
	253
36f32675 BB	254	phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
	255	unsigned long bus_addr,
	256	unsigned long flags)
c609719b WD	257	{
	258	struct pci_region *res;
	259	int i;
	260
f07771cc WD	261	if (!hose) {
f07771cc WD	262	printf ("pci_hose_bus_to_phys: %s\n", "invalid hose");
c609719b WD	263	goto Done;
	264	}
	265
f07771cc	266	for (i = 0; i < hose->region_count; i++) {
c609719b WD	267	res = &hose->regions[i];
	268
	269	if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
	270	continue;
	271
	272	if (bus_addr >= res->bus_start &&
f07771cc	273	bus_addr < res->bus_start + res->size) {
c609719b WD	274	return bus_addr - res->bus_start + res->phys_start;
	275	}
	276	}
	277
f07771cc	278	printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address");
c609719b	279
f07771cc	280	Done:
c609719b WD	281	return 0;
	282	}
	283
	284	/*
	285	*
	286	*/
	287
	288	int pci_hose_config_device(struct pci_controller *hose,
	289	pci_dev_t dev,
	290	unsigned long io,
	291	unsigned long mem,
	292	unsigned long command)
	293	{
	294	unsigned int bar_response, bar_size, bar_value, old_command;
	295	unsigned char pin;
	296	int bar, found_mem64;
	297
a1191902	298	debug ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
f07771cc	299	io, mem, command);
c609719b	300
f07771cc	301	pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
c609719b	302
f07771cc WD	303	for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) {
	304	pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
	305	pci_hose_read_config_dword (hose, dev, bar, &bar_response);
c609719b WD	306
	307	if (!bar_response)
	308	continue;
	309
	310	found_mem64 = 0;
	311
	312	/* Check the BAR type and set our address mask */
f07771cc	313	if (bar_response & PCI_BASE_ADDRESS_SPACE) {
c609719b	314	bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
f07771cc	315	/* round up region base address to a multiple of size */
c609719b	316	io = ((io - 1) \| (bar_size - 1)) + 1;
f07771cc WD	317	bar_value = io;
	318	/* compute new region base address */
	319	io = io + bar_size;
	320	} else {
	321	if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
	322	PCI_BASE_ADDRESS_MEM_TYPE_64)
c609719b WD	323	found_mem64 = 1;
	324
	325	bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
c609719b	326
f07771cc	327	/* round up region base address to multiple of size */
c609719b	328	mem = ((mem - 1) \| (bar_size - 1)) + 1;
f07771cc WD	329	bar_value = mem;
	330	/* compute new region base address */
	331	mem = mem + bar_size;
c609719b WD	332	}
	333
	334	/* Write it out and update our limit */
f07771cc	335	pci_hose_write_config_dword (hose, dev, bar, bar_value);
c609719b	336
f07771cc	337	if (found_mem64) {
c609719b	338	bar += 4;
f07771cc	339	pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
c609719b WD	340	}
	341	}
	342
	343	/* Configure Cache Line Size Register */
f07771cc	344	pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
c609719b WD	345
c609719b WD	346	/* Configure Latency Timer */
f07771cc	347	pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
c609719b WD	348
c609719b WD	349	/* Disable interrupt line, if device says it wants to use interrupts */
f07771cc WD	350	pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
	351	if (pin != 0) {
	352	pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
c609719b WD	353	}
c609719b WD	354
f07771cc WD	355	pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
	356	pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
	357	(old_command & 0xffff0000) \| command);
c609719b WD	358
	359	return 0;
	360	}
	361
	362	/*
	363	*
	364	*/
	365
	366	struct pci_config_table pci_find_config(struct pci_controller hose,
	367	unsigned short class,
	368	unsigned int vendor,
	369	unsigned int device,
	370	unsigned int bus,
	371	unsigned int dev,
	372	unsigned int func)
	373	{
	374	struct pci_config_table *table;
	375
f07771cc	376	for (table = hose->config_table; table && table->vendor; table++) {
c609719b WD	377	if ((table->vendor == PCI_ANY_ID \|\| table->vendor == vendor) &&
	378	(table->device == PCI_ANY_ID \|\| table->device == device) &&
	379	(table->class == PCI_ANY_ID \|\| table->class == class) &&
	380	(table->bus == PCI_ANY_ID \|\| table->bus == bus) &&
	381	(table->dev == PCI_ANY_ID \|\| table->dev == dev) &&
f07771cc	382	(table->func == PCI_ANY_ID \|\| table->func == func)) {
c609719b WD	383	return table;
	384	}
	385	}
	386
	387	return NULL;
	388	}
	389
	390	void pci_cfgfunc_config_device(struct pci_controller *hose,
	391	pci_dev_t dev,
	392	struct pci_config_table *entry)
	393	{
	394	pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
	395	}
	396
	397	void pci_cfgfunc_do_nothing(struct pci_controller *hose,
	398	pci_dev_t dev, struct pci_config_table *entry)
	399	{
	400	}
	401
	402	/*
	403	*
	404	*/
	405
c7de829c WD	406	/* HJF: Changed this to return int. I think this is required
	407	* to get the correct result when scanning bridges
	408	*/
	409	extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
c609719b	410	extern void pciauto_config_init(struct pci_controller *hose);
c609719b	411
dc1da42f SR	412	int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
	413	{
	414	/*
	415	* Check if pci device should be skipped in configuration
	416	*/
	417	if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
	418	#if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
	419	/*
	420	* Only skip configuration if "pciconfighost" is not set
	421	*/
	422	if (getenv("pciconfighost") == NULL)
	423	return 1;
	424	#else
	425	return 1;
	426	#endif
	427	}
	428
	429	return 0;
	430	}
	431	int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
	432	__attribute__((weak, alias("__pci_skip_dev")));
	433
	434	#ifdef CONFIG_PCI_SCAN_SHOW
	435	int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
	436	{
	437	if (dev == PCI_BDF(hose->first_busno, 0, 0))
	438	return 0;
	439
	440	return 1;
	441	}
	442	int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
	443	__attribute__((weak, alias("__pci_print_dev")));
	444	#endif /* CONFIG_PCI_SCAN_SHOW */
	445
c609719b WD	446	int pci_hose_scan_bus(struct pci_controller *hose, int bus)
	447	{
	448	unsigned int sub_bus, found_multi=0;
	449	unsigned short vendor, device, class;
	450	unsigned char header_type;
	451	struct pci_config_table *cfg;
	452	pci_dev_t dev;
	453
	454	sub_bus = bus;
	455
	456	for (dev = PCI_BDF(bus,0,0);
	457	dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
dc1da42f SR	458	dev += PCI_BDF(0,0,1)) {
	459
	460	if (pci_skip_dev(hose, dev))
	461	continue;
c609719b WD	462
	463	if (PCI_FUNC(dev) && !found_multi)
	464	continue;
	465
	466	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
	467
	468	pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
	469
c7de829c	470	if (vendor != 0xffff && vendor != 0x0000) {
c609719b WD	471
	472	if (!PCI_FUNC(dev))
	473	found_multi = header_type & 0x80;
	474
a1191902 WD	475	debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
a1191902 WD	476	PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
c609719b WD	477
	478	pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
	479	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
	480
	481	cfg = pci_find_config(hose, class, vendor, device,
	482	PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
c7de829c	483	if (cfg) {
c609719b	484	cfg->config_device(hose, dev, cfg);
3411d117	485	sub_bus = max(sub_bus, hose->current_busno);
c609719b	486	#ifdef CONFIG_PCI_PNP
c7de829c WD	487	} else {
	488	int n = pciauto_config_device(hose, dev);
	489
	490	sub_bus = max(sub_bus, n);
c609719b	491	#endif
c7de829c	492	}
c609719b WD	493	if (hose->fixup_irq)
	494	hose->fixup_irq(hose, dev);
	495
	496	#ifdef CONFIG_PCI_SCAN_SHOW
dc1da42f SR	497	if (pci_print_dev(hose, dev)) {
	498	unsigned char int_line;
	499
	500	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE,
	501	&int_line);
	502	printf(" %02x %02x %04x %04x %04x %02x\n",
	503	PCI_BUS(dev), PCI_DEV(dev), vendor, device, class,
	504	int_line);
c609719b WD	505	}
	506	#endif
	507	}
	508	}
	509
	510	return sub_bus;
	511	}
	512
	513	int pci_hose_scan(struct pci_controller *hose)
	514	{
40e81add ES	515	/* Start scan at current_busno.
	516	* PCIe will start scan at first_busno+1.
	517	*/
	518	/* For legacy support, ensure current>=first */
	519	if (hose->first_busno > hose->current_busno)
	520	hose->current_busno = hose->first_busno;
c609719b WD	521	#ifdef CONFIG_PCI_PNP
	522	pciauto_config_init(hose);
	523	#endif
40e81add	524	return pci_hose_scan_bus(hose, hose->current_busno);
c609719b WD	525	}
c609719b WD	526
ad10dd9a SR	527	void pci_init(void)
	528	{
	529	#if defined(CONFIG_PCI_BOOTDELAY)
	530	char *s;
	531	int i;
	532
	533	/* wait "pcidelay" ms (if defined)... */
	534	s = getenv ("pcidelay");
	535	if (s) {
	536	int val = simple_strtoul (s, NULL, 10);
	537	for (i=0; i<val; i++)
	538	udelay (1000);
	539	}
	540	#endif /* CONFIG_PCI_BOOTDELAY */
	541
	542	/* now call board specific pci_init()... */
	543	pci_init_board();
	544	}