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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
9c28d61c AS |
2 | /* |
3 | * PCIe driver for Marvell MVEBU SoCs | |
4 | * | |
5 | * Based on Barebox drivers/pci/pci-mvebu.c | |
6 | * | |
7 | * Ported to U-Boot by: | |
8 | * Anton Schubert <anton.schubert@gmx.de> | |
9 | * Stefan Roese <sr@denx.de> | |
22f69fc7 | 10 | * Pali Rohár <pali@kernel.org> |
9c28d61c AS |
11 | */ |
12 | ||
d678a59d | 13 | #include <common.h> |
94f453ea | 14 | #include <dm.h> |
f7ae49fc | 15 | #include <log.h> |
336d4615 | 16 | #include <malloc.h> |
94f453ea SR |
17 | #include <dm/device-internal.h> |
18 | #include <dm/lists.h> | |
19 | #include <dm/of_access.h> | |
9c28d61c | 20 | #include <pci.h> |
94c30f9c | 21 | #include <reset.h> |
9c28d61c AS |
22 | #include <asm/io.h> |
23 | #include <asm/arch/cpu.h> | |
24 | #include <asm/arch/soc.h> | |
ca3756c8 | 25 | #include <asm/gpio.h> |
cd93d625 | 26 | #include <linux/bitops.h> |
e7ff4271 | 27 | #include <linux/delay.h> |
94f453ea SR |
28 | #include <linux/errno.h> |
29 | #include <linux/ioport.h> | |
9c28d61c | 30 | #include <linux/mbus.h> |
1e94b46f | 31 | #include <linux/printk.h> |
537b0142 | 32 | #include <linux/sizes.h> |
9c28d61c | 33 | |
9c28d61c | 34 | /* PCIe unit register offsets */ |
fc27e5df T |
35 | #define MVPCIE_ROOT_PORT_PCI_CFG_OFF 0x0000 |
36 | #define MVPCIE_ROOT_PORT_PCI_EXP_OFF 0x0060 | |
37 | #define MVPCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3)) | |
38 | #define MVPCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3)) | |
39 | #define MVPCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4)) | |
40 | #define MVPCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4)) | |
41 | #define MVPCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4)) | |
42 | #define MVPCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4)) | |
43 | #define MVPCIE_WIN5_CTRL_OFF 0x1880 | |
44 | #define MVPCIE_WIN5_BASE_OFF 0x1884 | |
45 | #define MVPCIE_WIN5_REMAP_OFF 0x188c | |
46 | #define MVPCIE_CONF_ADDR_OFF 0x18f8 | |
47 | #define MVPCIE_CONF_DATA_OFF 0x18fc | |
48 | #define MVPCIE_CTRL_OFF 0x1a00 | |
49 | #define MVPCIE_CTRL_RC_MODE BIT(1) | |
50 | #define MVPCIE_STAT_OFF 0x1a04 | |
51 | #define MVPCIE_STAT_BUS (0xff << 8) | |
52 | #define MVPCIE_STAT_DEV (0x1f << 16) | |
53 | #define MVPCIE_STAT_LINK_DOWN BIT(0) | |
9c28d61c | 54 | |
e7ff4271 T |
55 | #define LINK_WAIT_RETRIES 100 |
56 | #define LINK_WAIT_TIMEOUT 1000 | |
57 | ||
9c28d61c AS |
58 | struct mvebu_pcie { |
59 | struct pci_controller hose; | |
9c28d61c AS |
60 | void __iomem *base; |
61 | void __iomem *membase; | |
62 | struct resource mem; | |
63 | void __iomem *iobase; | |
ba8ae03e | 64 | struct resource io; |
ca3756c8 | 65 | struct gpio_desc reset_gpio; |
137db2af | 66 | u32 intregs; |
9c28d61c AS |
67 | u32 port; |
68 | u32 lane; | |
94c30f9c | 69 | bool is_x4; |
94f453ea | 70 | int devfn; |
a7b61ab5 | 71 | int sec_busno; |
94f453ea SR |
72 | char name[16]; |
73 | unsigned int mem_target; | |
74 | unsigned int mem_attr; | |
ba8ae03e PS |
75 | unsigned int io_target; |
76 | unsigned int io_attr; | |
a48e4287 | 77 | u32 cfgcache[(0x3c - 0x10) / 4]; |
9c28d61c AS |
78 | }; |
79 | ||
9c28d61c AS |
80 | static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) |
81 | { | |
82 | u32 val; | |
fc27e5df T |
83 | val = readl(pcie->base + MVPCIE_STAT_OFF); |
84 | return !(val & MVPCIE_STAT_LINK_DOWN); | |
9c28d61c AS |
85 | } |
86 | ||
e7ff4271 T |
87 | static void mvebu_pcie_wait_for_link(struct mvebu_pcie *pcie) |
88 | { | |
89 | int retries; | |
90 | ||
91 | /* check if the link is up or not */ | |
92 | for (retries = 0; retries < LINK_WAIT_RETRIES; retries++) { | |
93 | if (mvebu_pcie_link_up(pcie)) { | |
94 | printf("%s: Link up\n", pcie->name); | |
95 | return; | |
96 | } | |
97 | ||
98 | udelay(LINK_WAIT_TIMEOUT); | |
99 | } | |
100 | ||
101 | printf("%s: Link down\n", pcie->name); | |
102 | } | |
103 | ||
9c28d61c AS |
104 | static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno) |
105 | { | |
106 | u32 stat; | |
107 | ||
fc27e5df T |
108 | stat = readl(pcie->base + MVPCIE_STAT_OFF); |
109 | stat &= ~MVPCIE_STAT_BUS; | |
9c28d61c | 110 | stat |= busno << 8; |
fc27e5df | 111 | writel(stat, pcie->base + MVPCIE_STAT_OFF); |
9c28d61c AS |
112 | } |
113 | ||
114 | static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno) | |
115 | { | |
116 | u32 stat; | |
117 | ||
fc27e5df T |
118 | stat = readl(pcie->base + MVPCIE_STAT_OFF); |
119 | stat &= ~MVPCIE_STAT_DEV; | |
9c28d61c | 120 | stat |= devno << 16; |
fc27e5df | 121 | writel(stat, pcie->base + MVPCIE_STAT_OFF); |
9c28d61c AS |
122 | } |
123 | ||
9c28d61c AS |
124 | static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose) |
125 | { | |
126 | return container_of(hose, struct mvebu_pcie, hose); | |
127 | } | |
128 | ||
a7b61ab5 T |
129 | static bool mvebu_pcie_valid_addr(struct mvebu_pcie *pcie, |
130 | int busno, int dev, int func) | |
10eb2cc3 | 131 | { |
0eebc3db T |
132 | /* On the root bus is only one PCI Bridge */ |
133 | if (busno == 0 && (dev != 0 || func != 0)) | |
a7b61ab5 T |
134 | return false; |
135 | ||
79b4eb21 | 136 | /* Access to other buses is possible when link is up */ |
0eebc3db | 137 | if (busno != 0 && !mvebu_pcie_link_up(pcie)) |
79b4eb21 T |
138 | return false; |
139 | ||
a7b61ab5 T |
140 | /* On secondary bus can be only one PCIe device */ |
141 | if (busno == pcie->sec_busno && dev != 0) | |
142 | return false; | |
10eb2cc3 | 143 | |
a7b61ab5 | 144 | return true; |
10eb2cc3 MB |
145 | } |
146 | ||
c4e72c4a | 147 | static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, |
94f453ea SR |
148 | uint offset, ulong *valuep, |
149 | enum pci_size_t size) | |
9c28d61c | 150 | { |
c69cda25 | 151 | struct mvebu_pcie *pcie = dev_get_plat(bus); |
a7b61ab5 T |
152 | int busno = PCI_BUS(bdf) - dev_seq(bus); |
153 | u32 addr, data; | |
94f453ea | 154 | |
10eb2cc3 MB |
155 | debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ", |
156 | PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); | |
6a2fa284 | 157 | |
a7b61ab5 | 158 | if (!mvebu_pcie_valid_addr(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) { |
6a2fa284 SR |
159 | debug("- out of range\n"); |
160 | *valuep = pci_get_ff(size); | |
161 | return 0; | |
9c28d61c AS |
162 | } |
163 | ||
a7b61ab5 | 164 | /* |
0eebc3db | 165 | * The configuration space of the PCI Bridge on the root bus (zero) is |
a48e4287 T |
166 | * of Type 0 but the BAR registers (including ROM BAR) don't have the |
167 | * same meaning as in the PCIe specification. Therefore do not access | |
168 | * BAR registers and non-common registers (those which have different | |
169 | * meaning for Type 0 and Type 1 config space) of the PCI Bridge and | |
170 | * instead read their content from driver virtual cfgcache[]. | |
a7b61ab5 | 171 | */ |
0eebc3db T |
172 | if (busno == 0 && ((offset >= 0x10 && offset < 0x34) || |
173 | (offset >= 0x38 && offset < 0x3c))) { | |
a7b61ab5 T |
174 | data = pcie->cfgcache[(offset - 0x10) / 4]; |
175 | debug("(addr,size,val)=(0x%04x, %d, 0x%08x) from cfgcache\n", | |
176 | offset, size, data); | |
177 | *valuep = pci_conv_32_to_size(data, offset, size); | |
178 | return 0; | |
a7b61ab5 T |
179 | } |
180 | ||
181 | /* | |
0eebc3db T |
182 | * PCI bridge is device 0 at the root bus (zero) but mvebu has it |
183 | * mapped on secondary bus with device number 1. | |
a7b61ab5 | 184 | */ |
0eebc3db | 185 | if (busno == 0) |
d0dd49f9 | 186 | addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset); |
a7b61ab5 | 187 | else |
d0dd49f9 | 188 | addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); |
a7b61ab5 | 189 | |
9c28d61c | 190 | /* write address */ |
fc27e5df | 191 | writel(addr, pcie->base + MVPCIE_CONF_ADDR_OFF); |
241d7636 MB |
192 | |
193 | /* read data */ | |
657177ad T |
194 | switch (size) { |
195 | case PCI_SIZE_8: | |
fc27e5df | 196 | data = readb(pcie->base + MVPCIE_CONF_DATA_OFF + (offset & 3)); |
657177ad T |
197 | break; |
198 | case PCI_SIZE_16: | |
fc27e5df | 199 | data = readw(pcie->base + MVPCIE_CONF_DATA_OFF + (offset & 2)); |
657177ad T |
200 | break; |
201 | case PCI_SIZE_32: | |
fc27e5df | 202 | data = readl(pcie->base + MVPCIE_CONF_DATA_OFF); |
657177ad T |
203 | break; |
204 | default: | |
205 | return -EINVAL; | |
206 | } | |
207 | ||
0eebc3db | 208 | if (busno == 0 && (offset & ~3) == (PCI_HEADER_TYPE & ~3)) { |
a7b61ab5 T |
209 | /* |
210 | * Change Header Type of PCI Bridge device to Type 1 | |
211 | * (0x01, used by PCI Bridges) because mvebu reports | |
212 | * Type 0 (0x00, used by Upstream and Endpoint devices). | |
213 | */ | |
214 | data = pci_conv_size_to_32(data, 0, offset, size); | |
215 | data &= ~0x007f0000; | |
216 | data |= PCI_HEADER_TYPE_BRIDGE << 16; | |
217 | data = pci_conv_32_to_size(data, offset, size); | |
218 | } | |
219 | ||
26f7a76e | 220 | debug("(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, data); |
657177ad | 221 | *valuep = data; |
9c28d61c AS |
222 | |
223 | return 0; | |
224 | } | |
225 | ||
94f453ea SR |
226 | static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, |
227 | uint offset, ulong value, | |
228 | enum pci_size_t size) | |
9c28d61c | 229 | { |
c69cda25 | 230 | struct mvebu_pcie *pcie = dev_get_plat(bus); |
a7b61ab5 T |
231 | int busno = PCI_BUS(bdf) - dev_seq(bus); |
232 | u32 addr, data; | |
94f453ea | 233 | |
10eb2cc3 MB |
234 | debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", |
235 | PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); | |
26f7a76e | 236 | debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value); |
9c28d61c | 237 | |
a7b61ab5 | 238 | if (!mvebu_pcie_valid_addr(pcie, busno, PCI_DEV(bdf), PCI_FUNC(bdf))) { |
6a2fa284 SR |
239 | debug("- out of range\n"); |
240 | return 0; | |
9c28d61c AS |
241 | } |
242 | ||
a7b61ab5 | 243 | /* |
a48e4287 T |
244 | * As explained in mvebu_pcie_read_config(), PCI Bridge Type 1 specific |
245 | * config registers are not available, so we write their content only | |
246 | * into driver virtual cfgcache[]. | |
247 | * And as explained in mvebu_pcie_probe(), mvebu has its own specific | |
0eebc3db | 248 | * way for configuring secondary bus number. |
a7b61ab5 | 249 | */ |
0eebc3db T |
250 | if (busno == 0 && ((offset >= 0x10 && offset < 0x34) || |
251 | (offset >= 0x38 && offset < 0x3c))) { | |
a7b61ab5 T |
252 | debug("Writing to cfgcache only\n"); |
253 | data = pcie->cfgcache[(offset - 0x10) / 4]; | |
254 | data = pci_conv_size_to_32(data, value, offset, size); | |
255 | /* mvebu PCI bridge does not have configurable bars */ | |
256 | if ((offset & ~3) == PCI_BASE_ADDRESS_0 || | |
a48e4287 T |
257 | (offset & ~3) == PCI_BASE_ADDRESS_1 || |
258 | (offset & ~3) == PCI_ROM_ADDRESS1) | |
a7b61ab5 T |
259 | data = 0x0; |
260 | pcie->cfgcache[(offset - 0x10) / 4] = data; | |
a7b61ab5 T |
261 | /* mvebu has its own way how to set PCI secondary bus number */ |
262 | if (offset == PCI_SECONDARY_BUS || | |
263 | (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) { | |
264 | pcie->sec_busno = (data >> 8) & 0xff; | |
265 | mvebu_pcie_set_local_bus_nr(pcie, pcie->sec_busno); | |
266 | debug("Secondary bus number was changed to %d\n", | |
267 | pcie->sec_busno); | |
268 | } | |
269 | return 0; | |
a7b61ab5 T |
270 | } |
271 | ||
272 | /* | |
0eebc3db T |
273 | * PCI bridge is device 0 at the root bus (zero) but mvebu has it |
274 | * mapped on secondary bus with device number 1. | |
a7b61ab5 | 275 | */ |
0eebc3db | 276 | if (busno == 0) |
d0dd49f9 | 277 | addr = PCI_CONF1_EXT_ADDRESS(pcie->sec_busno, 1, 0, offset); |
a7b61ab5 | 278 | else |
d0dd49f9 | 279 | addr = PCI_CONF1_EXT_ADDRESS(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); |
a7b61ab5 | 280 | |
241d7636 | 281 | /* write address */ |
fc27e5df | 282 | writel(addr, pcie->base + MVPCIE_CONF_ADDR_OFF); |
241d7636 MB |
283 | |
284 | /* write data */ | |
daa9bfdb T |
285 | switch (size) { |
286 | case PCI_SIZE_8: | |
fc27e5df | 287 | writeb(value, pcie->base + MVPCIE_CONF_DATA_OFF + (offset & 3)); |
daa9bfdb T |
288 | break; |
289 | case PCI_SIZE_16: | |
fc27e5df | 290 | writew(value, pcie->base + MVPCIE_CONF_DATA_OFF + (offset & 2)); |
daa9bfdb T |
291 | break; |
292 | case PCI_SIZE_32: | |
fc27e5df | 293 | writel(value, pcie->base + MVPCIE_CONF_DATA_OFF); |
daa9bfdb T |
294 | break; |
295 | default: | |
296 | return -EINVAL; | |
297 | } | |
9c28d61c AS |
298 | |
299 | return 0; | |
300 | } | |
301 | ||
302 | /* | |
303 | * Setup PCIE BARs and Address Decode Wins: | |
4a1a593d T |
304 | * BAR[0] -> internal registers |
305 | * BAR[1] -> covers all DRAM banks | |
306 | * BAR[2] -> disabled | |
9c28d61c AS |
307 | * WIN[0-3] -> DRAM bank[0-3] |
308 | */ | |
309 | static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie) | |
310 | { | |
311 | const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info(); | |
312 | u32 size; | |
313 | int i; | |
314 | ||
315 | /* First, disable and clear BARs and windows. */ | |
316 | for (i = 1; i < 3; i++) { | |
fc27e5df T |
317 | writel(0, pcie->base + MVPCIE_BAR_CTRL_OFF(i)); |
318 | writel(0, pcie->base + MVPCIE_BAR_LO_OFF(i)); | |
319 | writel(0, pcie->base + MVPCIE_BAR_HI_OFF(i)); | |
9c28d61c AS |
320 | } |
321 | ||
322 | for (i = 0; i < 5; i++) { | |
fc27e5df T |
323 | writel(0, pcie->base + MVPCIE_WIN04_CTRL_OFF(i)); |
324 | writel(0, pcie->base + MVPCIE_WIN04_BASE_OFF(i)); | |
325 | writel(0, pcie->base + MVPCIE_WIN04_REMAP_OFF(i)); | |
9c28d61c AS |
326 | } |
327 | ||
fc27e5df T |
328 | writel(0, pcie->base + MVPCIE_WIN5_CTRL_OFF); |
329 | writel(0, pcie->base + MVPCIE_WIN5_BASE_OFF); | |
330 | writel(0, pcie->base + MVPCIE_WIN5_REMAP_OFF); | |
9c28d61c AS |
331 | |
332 | /* Setup windows for DDR banks. Count total DDR size on the fly. */ | |
333 | size = 0; | |
334 | for (i = 0; i < dram->num_cs; i++) { | |
335 | const struct mbus_dram_window *cs = dram->cs + i; | |
336 | ||
337 | writel(cs->base & 0xffff0000, | |
fc27e5df T |
338 | pcie->base + MVPCIE_WIN04_BASE_OFF(i)); |
339 | writel(0, pcie->base + MVPCIE_WIN04_REMAP_OFF(i)); | |
9c28d61c AS |
340 | writel(((cs->size - 1) & 0xffff0000) | |
341 | (cs->mbus_attr << 8) | | |
342 | (dram->mbus_dram_target_id << 4) | 1, | |
fc27e5df | 343 | pcie->base + MVPCIE_WIN04_CTRL_OFF(i)); |
9c28d61c AS |
344 | |
345 | size += cs->size; | |
346 | } | |
347 | ||
348 | /* Round up 'size' to the nearest power of two. */ | |
349 | if ((size & (size - 1)) != 0) | |
350 | size = 1 << fls(size); | |
351 | ||
352 | /* Setup BAR[1] to all DRAM banks. */ | |
fc27e5df T |
353 | writel(dram->cs[0].base | 0xc, pcie->base + MVPCIE_BAR_LO_OFF(1)); |
354 | writel(0, pcie->base + MVPCIE_BAR_HI_OFF(1)); | |
9c28d61c | 355 | writel(((size - 1) & 0xffff0000) | 0x1, |
fc27e5df | 356 | pcie->base + MVPCIE_BAR_CTRL_OFF(1)); |
4a1a593d T |
357 | |
358 | /* Setup BAR[0] to internal registers. */ | |
fc27e5df T |
359 | writel(pcie->intregs, pcie->base + MVPCIE_BAR_LO_OFF(0)); |
360 | writel(0, pcie->base + MVPCIE_BAR_HI_OFF(0)); | |
9c28d61c AS |
361 | } |
362 | ||
afef9f42 T |
363 | /* Only enable PCIe link, do not setup it */ |
364 | static int mvebu_pcie_enable_link(struct mvebu_pcie *pcie, ofnode node) | |
365 | { | |
94c30f9c T |
366 | struct reset_ctl rst; |
367 | int ret; | |
368 | ||
369 | ret = reset_get_by_index_nodev(node, 0, &rst); | |
370 | if (ret == -ENOENT) { | |
371 | return 0; | |
372 | } else if (ret < 0) { | |
373 | printf("%s: cannot get reset controller: %d\n", pcie->name, ret); | |
374 | return ret; | |
375 | } | |
376 | ||
377 | ret = reset_request(&rst); | |
378 | if (ret) { | |
379 | printf("%s: cannot request reset controller: %d\n", pcie->name, ret); | |
380 | return ret; | |
381 | } | |
382 | ||
383 | ret = reset_deassert(&rst); | |
384 | reset_free(&rst); | |
385 | if (ret) { | |
386 | printf("%s: cannot enable PCIe port: %d\n", pcie->name, ret); | |
387 | return ret; | |
388 | } | |
389 | ||
afef9f42 T |
390 | return 0; |
391 | } | |
392 | ||
393 | /* Setup PCIe link but do not enable it */ | |
394 | static void mvebu_pcie_setup_link(struct mvebu_pcie *pcie) | |
9c28d61c | 395 | { |
9c28d61c | 396 | u32 reg; |
9c28d61c | 397 | |
2344a76f | 398 | /* Setup PCIe controller to Root Complex mode */ |
fc27e5df T |
399 | reg = readl(pcie->base + MVPCIE_CTRL_OFF); |
400 | reg |= MVPCIE_CTRL_RC_MODE; | |
401 | writel(reg, pcie->base + MVPCIE_CTRL_OFF); | |
94c30f9c T |
402 | |
403 | /* | |
404 | * Set Maximum Link Width to X1 or X4 in Root Port's PCIe Link | |
405 | * Capability register. This register is defined by PCIe specification | |
406 | * as read-only but this mvebu controller has it as read-write and must | |
407 | * be set to number of SerDes PCIe lanes (1 or 4). If this register is | |
408 | * not set correctly then link with endpoint card is not established. | |
409 | */ | |
fc27e5df | 410 | reg = readl(pcie->base + MVPCIE_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_LNKCAP); |
94c30f9c T |
411 | reg &= ~PCI_EXP_LNKCAP_MLW; |
412 | reg |= (pcie->is_x4 ? 4 : 1) << 4; | |
fc27e5df | 413 | writel(reg, pcie->base + MVPCIE_ROOT_PORT_PCI_EXP_OFF + PCI_EXP_LNKCAP); |
afef9f42 T |
414 | } |
415 | ||
416 | static int mvebu_pcie_probe(struct udevice *dev) | |
417 | { | |
418 | struct mvebu_pcie *pcie = dev_get_plat(dev); | |
419 | struct udevice *ctlr = pci_get_controller(dev); | |
420 | struct pci_controller *hose = dev_get_uclass_priv(ctlr); | |
421 | u32 reg; | |
ca3756c8 T |
422 | int ret; |
423 | ||
424 | /* Request for optional PERST# GPIO */ | |
425 | ret = gpio_request_by_name(dev, "reset-gpios", 0, &pcie->reset_gpio, GPIOD_IS_OUT); | |
426 | if (ret && ret != -ENOENT) { | |
427 | printf("%s: unable to request reset-gpios: %d\n", pcie->name, ret); | |
428 | return ret; | |
429 | } | |
2344a76f | 430 | |
a7b61ab5 T |
431 | /* |
432 | * Change Class Code of PCI Bridge device to PCI Bridge (0x600400) | |
433 | * because default value is Memory controller (0x508000) which | |
434 | * U-Boot cannot recognize as P2P Bridge. | |
435 | * | |
436 | * Note that this mvebu PCI Bridge does not have compliant Type 1 | |
a48e4287 T |
437 | * Configuration Space. Header Type is reported as Type 0 and it |
438 | * has format of Type 0 config space. | |
a7b61ab5 | 439 | * |
a48e4287 T |
440 | * Moreover Type 0 BAR registers (ranges 0x10 - 0x28 and 0x30 - 0x34) |
441 | * have the same format in Marvell's specification as in PCIe | |
442 | * specification, but their meaning is totally different and they do | |
443 | * different things: they are aliased into internal mvebu registers | |
fc27e5df | 444 | * (e.g. MVPCIE_BAR_LO_OFF) and these should not be changed or |
a48e4287 T |
445 | * reconfigured by pci device drivers. |
446 | * | |
447 | * So our driver converts Type 0 config space to Type 1 and reports | |
448 | * Header Type as Type 1. Access to BAR registers and to non-existent | |
449 | * Type 1 registers is redirected to the virtual cfgcache[] buffer, | |
450 | * which avoids changing unrelated registers. | |
a7b61ab5 | 451 | */ |
fc27e5df | 452 | reg = readl(pcie->base + MVPCIE_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION); |
a7b61ab5 | 453 | reg &= ~0xffffff00; |
d7b90409 | 454 | reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8; |
fc27e5df | 455 | writel(reg, pcie->base + MVPCIE_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION); |
10eb2cc3 | 456 | |
a7b61ab5 T |
457 | /* |
458 | * mvebu uses local bus number and local device number to determinate | |
459 | * type of config request. Type 0 is used if target bus number equals | |
460 | * local bus number and target device number differs from local device | |
461 | * number. Type 1 is used if target bus number differs from local bus | |
462 | * number. And when target bus number equals local bus number and | |
463 | * target device equals local device number then request is routed to | |
464 | * PCI Bridge which represent local PCIe Root Port. | |
465 | * | |
0eebc3db | 466 | * It means that PCI root and secondary buses shares one bus number |
a7b61ab5 | 467 | * which is configured via local bus number. Determination if config |
0eebc3db | 468 | * request should go to root or secondary bus is done based on local |
a7b61ab5 T |
469 | * device number. |
470 | * | |
471 | * PCIe is point-to-point bus, so at secondary bus is always exactly one | |
472 | * device with number 0. So set local device number to 1, it would not | |
473 | * conflict with any device on secondary bus number and will ensure that | |
474 | * accessing secondary bus and all buses behind secondary would work | |
475 | * automatically and correctly. Therefore this configuration of local | |
476 | * device number implies that setting of local bus number configures | |
477 | * secondary bus number. Set it to 0 as U-Boot CONFIG_PCI_PNP code will | |
478 | * later configure it via config write requests to the correct value. | |
479 | * mvebu_pcie_write_config() catches config write requests which tries | |
0eebc3db T |
480 | * to change secondary bus number and correctly updates local bus number |
481 | * based on new secondary bus number. | |
a7b61ab5 T |
482 | * |
483 | * With this configuration is PCI Bridge available at secondary bus as | |
0eebc3db | 484 | * device number 1. But it must be available at root bus (zero) as device |
a7b61ab5 | 485 | * number 0. So in mvebu_pcie_read_config() and mvebu_pcie_write_config() |
0eebc3db | 486 | * functions rewrite address to the real one when accessing the root bus. |
a7b61ab5 T |
487 | */ |
488 | mvebu_pcie_set_local_bus_nr(pcie, 0); | |
489 | mvebu_pcie_set_local_dev_nr(pcie, 1); | |
94f453ea | 490 | |
43640713 T |
491 | /* |
492 | * Kirkwood arch code already maps mbus windows for PCIe IO and MEM. | |
493 | * So skip calling mvebu_mbus_add_window_by_id() function as it would | |
494 | * fail on error "conflicts with another window" which means conflict | |
495 | * with existing PCIe window mappings. | |
496 | */ | |
497 | #ifndef CONFIG_ARCH_KIRKWOOD | |
537b0142 T |
498 | if (resource_size(&pcie->mem) && |
499 | mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr, | |
94f453ea | 500 | (phys_addr_t)pcie->mem.start, |
e1cee89e | 501 | resource_size(&pcie->mem))) { |
afef9f42 T |
502 | printf("%s: unable to add mbus window for mem at %08x+%08x\n", |
503 | pcie->name, | |
e1cee89e | 504 | (u32)pcie->mem.start, (unsigned)resource_size(&pcie->mem)); |
537b0142 T |
505 | pcie->mem.start = 0; |
506 | pcie->mem.end = -1; | |
94f453ea SR |
507 | } |
508 | ||
537b0142 T |
509 | if (resource_size(&pcie->io) && |
510 | mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr, | |
ba8ae03e | 511 | (phys_addr_t)pcie->io.start, |
e1cee89e | 512 | resource_size(&pcie->io))) { |
afef9f42 T |
513 | printf("%s: unable to add mbus window for IO at %08x+%08x\n", |
514 | pcie->name, | |
e1cee89e | 515 | (u32)pcie->io.start, (unsigned)resource_size(&pcie->io)); |
537b0142 T |
516 | pcie->io.start = 0; |
517 | pcie->io.end = -1; | |
ba8ae03e | 518 | } |
43640713 | 519 | #endif |
ba8ae03e | 520 | |
94f453ea SR |
521 | /* Setup windows and configure host bridge */ |
522 | mvebu_pcie_setup_wins(pcie); | |
523 | ||
94f453ea SR |
524 | /* PCI memory space */ |
525 | pci_set_region(hose->regions + 0, pcie->mem.start, | |
e1cee89e | 526 | pcie->mem.start, resource_size(&pcie->mem), PCI_REGION_MEM); |
537b0142 T |
527 | hose->region_count = 1; |
528 | ||
529 | if (resource_size(&pcie->mem)) { | |
530 | pci_set_region(hose->regions + hose->region_count, | |
531 | pcie->mem.start, pcie->mem.start, | |
532 | resource_size(&pcie->mem), | |
533 | PCI_REGION_MEM); | |
534 | hose->region_count++; | |
535 | } | |
536 | ||
537 | if (resource_size(&pcie->io)) { | |
538 | pci_set_region(hose->regions + hose->region_count, | |
539 | pcie->io.start, pcie->io.start, | |
540 | resource_size(&pcie->io), | |
541 | PCI_REGION_IO); | |
542 | hose->region_count++; | |
543 | } | |
9c28d61c | 544 | |
a7b61ab5 T |
545 | /* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */ |
546 | pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] = | |
547 | PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8); | |
548 | pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] = | |
549 | PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16); | |
550 | ||
ca3756c8 T |
551 | /* Release PERST# via GPIO when it was defined */ |
552 | if (dm_gpio_is_valid(&pcie->reset_gpio)) | |
553 | dm_gpio_set_value(&pcie->reset_gpio, 0); | |
554 | ||
e7ff4271 T |
555 | mvebu_pcie_wait_for_link(pcie); |
556 | ||
94f453ea SR |
557 | return 0; |
558 | } | |
559 | ||
94f453ea SR |
560 | #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03) |
561 | #define DT_TYPE_IO 0x1 | |
562 | #define DT_TYPE_MEM32 0x2 | |
563 | #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF) | |
564 | #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF) | |
565 | ||
566 | static int mvebu_get_tgt_attr(ofnode node, int devfn, | |
567 | unsigned long type, | |
568 | unsigned int *tgt, | |
569 | unsigned int *attr) | |
570 | { | |
571 | const int na = 3, ns = 2; | |
572 | const __be32 *range; | |
573 | int rlen, nranges, rangesz, pna, i; | |
574 | ||
575 | *tgt = -1; | |
576 | *attr = -1; | |
577 | ||
578 | range = ofnode_get_property(node, "ranges", &rlen); | |
579 | if (!range) | |
580 | return -EINVAL; | |
581 | ||
0df62e8d SR |
582 | /* |
583 | * Linux uses of_n_addr_cells() to get the number of address cells | |
584 | * here. Currently this function is only available in U-Boot when | |
585 | * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in | |
586 | * general, lets't hardcode the "pna" value in the U-Boot code. | |
587 | */ | |
94f453ea SR |
588 | pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */ |
589 | rangesz = pna + na + ns; | |
590 | nranges = rlen / sizeof(__be32) / rangesz; | |
591 | ||
592 | for (i = 0; i < nranges; i++, range += rangesz) { | |
593 | u32 flags = of_read_number(range, 1); | |
594 | u32 slot = of_read_number(range + 1, 1); | |
595 | u64 cpuaddr = of_read_number(range + na, pna); | |
596 | unsigned long rtype; | |
597 | ||
598 | if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO) | |
599 | rtype = IORESOURCE_IO; | |
600 | else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32) | |
601 | rtype = IORESOURCE_MEM; | |
602 | else | |
9c28d61c | 603 | continue; |
94f453ea SR |
604 | |
605 | /* | |
606 | * The Linux code used PCI_SLOT() here, which expects devfn | |
607 | * in bits 7..0. PCI_DEV() in U-Boot is similar to PCI_SLOT(), | |
608 | * only expects devfn in 15..8, where its saved in this driver. | |
609 | */ | |
610 | if (slot == PCI_DEV(devfn) && type == rtype) { | |
611 | *tgt = DT_CPUADDR_TO_TARGET(cpuaddr); | |
612 | *attr = DT_CPUADDR_TO_ATTR(cpuaddr); | |
613 | return 0; | |
9c28d61c | 614 | } |
94f453ea SR |
615 | } |
616 | ||
617 | return -ENOENT; | |
618 | } | |
619 | ||
afef9f42 | 620 | static int mvebu_pcie_port_parse_dt(ofnode node, ofnode parent, struct mvebu_pcie *pcie) |
94f453ea | 621 | { |
afef9f42 | 622 | struct fdt_pci_addr pci_addr; |
6f4988f9 | 623 | const u32 *addr; |
94c30f9c | 624 | u32 num_lanes; |
94f453ea | 625 | int ret = 0; |
6f4988f9 | 626 | int len; |
94f453ea SR |
627 | |
628 | /* Get port number, lane number and memory target / attr */ | |
afef9f42 | 629 | if (ofnode_read_u32(node, "marvell,pcie-port", |
94f453ea SR |
630 | &pcie->port)) { |
631 | ret = -ENODEV; | |
632 | goto err; | |
633 | } | |
634 | ||
afef9f42 | 635 | if (ofnode_read_u32(node, "marvell,pcie-lane", &pcie->lane)) |
94f453ea | 636 | pcie->lane = 0; |
9c28d61c | 637 | |
94f453ea | 638 | sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane); |
9c28d61c | 639 | |
94c30f9c T |
640 | if (!ofnode_read_u32(node, "num-lanes", &num_lanes) && num_lanes == 4) |
641 | pcie->is_x4 = true; | |
642 | ||
afef9f42 | 643 | /* devfn is in bits [15:8], see PCI_DEV usage */ |
f69d3d6d SG |
644 | ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg", &pci_addr, |
645 | NULL); | |
afef9f42 T |
646 | if (ret < 0) { |
647 | printf("%s: property \"reg\" is invalid\n", pcie->name); | |
94f453ea SR |
648 | goto err; |
649 | } | |
afef9f42 | 650 | pcie->devfn = pci_addr.phys_hi & 0xff00; |
94f453ea | 651 | |
afef9f42 | 652 | ret = mvebu_get_tgt_attr(parent, pcie->devfn, |
94f453ea SR |
653 | IORESOURCE_MEM, |
654 | &pcie->mem_target, &pcie->mem_attr); | |
655 | if (ret < 0) { | |
656 | printf("%s: cannot get tgt/attr for mem window\n", pcie->name); | |
657 | goto err; | |
658 | } | |
659 | ||
afef9f42 | 660 | ret = mvebu_get_tgt_attr(parent, pcie->devfn, |
ba8ae03e PS |
661 | IORESOURCE_IO, |
662 | &pcie->io_target, &pcie->io_attr); | |
663 | if (ret < 0) { | |
664 | printf("%s: cannot get tgt/attr for IO window\n", pcie->name); | |
665 | goto err; | |
666 | } | |
667 | ||
94f453ea | 668 | /* Parse PCIe controller register base from DT */ |
afef9f42 | 669 | addr = ofnode_get_property(node, "assigned-addresses", &len); |
6f4988f9 T |
670 | if (!addr) { |
671 | printf("%s: property \"assigned-addresses\" not found\n", pcie->name); | |
672 | ret = -FDT_ERR_NOTFOUND; | |
94f453ea | 673 | goto err; |
6f4988f9 T |
674 | } |
675 | ||
afef9f42 | 676 | pcie->base = (void *)(u32)ofnode_translate_address(node, addr); |
137db2af | 677 | pcie->intregs = (u32)pcie->base - fdt32_to_cpu(addr[2]); |
94f453ea | 678 | |
94f453ea SR |
679 | return 0; |
680 | ||
681 | err: | |
682 | return ret; | |
683 | } | |
684 | ||
685 | static const struct dm_pci_ops mvebu_pcie_ops = { | |
686 | .read_config = mvebu_pcie_read_config, | |
687 | .write_config = mvebu_pcie_write_config, | |
688 | }; | |
689 | ||
690 | static struct driver pcie_mvebu_drv = { | |
691 | .name = "pcie_mvebu", | |
692 | .id = UCLASS_PCI, | |
693 | .ops = &mvebu_pcie_ops, | |
694 | .probe = mvebu_pcie_probe, | |
caa4daa2 | 695 | .plat_auto = sizeof(struct mvebu_pcie), |
94f453ea SR |
696 | }; |
697 | ||
698 | /* | |
699 | * Use a MISC device to bind the n instances (child nodes) of the | |
700 | * PCIe base controller in UCLASS_PCI. | |
701 | */ | |
702 | static int mvebu_pcie_bind(struct udevice *parent) | |
703 | { | |
afef9f42 | 704 | struct mvebu_pcie **ports_pcie; |
94f453ea SR |
705 | struct mvebu_pcie *pcie; |
706 | struct uclass_driver *drv; | |
707 | struct udevice *dev; | |
537b0142 T |
708 | struct resource mem; |
709 | struct resource io; | |
afef9f42 T |
710 | int ports_count, i; |
711 | ofnode *ports_nodes; | |
94f453ea SR |
712 | ofnode subnode; |
713 | ||
03a8a5e2 | 714 | /* Lookup pci driver */ |
94f453ea SR |
715 | drv = lists_uclass_lookup(UCLASS_PCI); |
716 | if (!drv) { | |
717 | puts("Cannot find PCI driver\n"); | |
718 | return -ENOENT; | |
719 | } | |
720 | ||
afef9f42 T |
721 | ports_count = ofnode_get_child_count(dev_ofnode(parent)); |
722 | ports_pcie = calloc(ports_count, sizeof(*ports_pcie)); | |
723 | ports_nodes = calloc(ports_count, sizeof(*ports_nodes)); | |
724 | if (!ports_pcie || !ports_nodes) { | |
725 | free(ports_pcie); | |
726 | free(ports_nodes); | |
727 | return -ENOMEM; | |
728 | } | |
729 | ports_count = 0; | |
730 | ||
43640713 T |
731 | #ifdef CONFIG_ARCH_KIRKWOOD |
732 | mem.start = KW_DEFADR_PCI_MEM; | |
733 | mem.end = KW_DEFADR_PCI_MEM + KW_DEFADR_PCI_MEM_SIZE - 1; | |
734 | io.start = KW_DEFADR_PCI_IO; | |
735 | io.end = KW_DEFADR_PCI_IO + KW_DEFADR_PCI_IO_SIZE - 1; | |
736 | #else | |
537b0142 T |
737 | mem.start = MBUS_PCI_MEM_BASE; |
738 | mem.end = MBUS_PCI_MEM_BASE + MBUS_PCI_MEM_SIZE - 1; | |
739 | io.start = MBUS_PCI_IO_BASE; | |
740 | io.end = MBUS_PCI_IO_BASE + MBUS_PCI_IO_SIZE - 1; | |
43640713 | 741 | #endif |
537b0142 | 742 | |
afef9f42 | 743 | /* First phase: Fill mvebu_pcie struct for each port */ |
94f453ea | 744 | ofnode_for_each_subnode(subnode, dev_ofnode(parent)) { |
89090661 | 745 | if (!ofnode_is_enabled(subnode)) |
9c28d61c | 746 | continue; |
9c28d61c | 747 | |
94f453ea SR |
748 | pcie = calloc(1, sizeof(*pcie)); |
749 | if (!pcie) | |
afef9f42 T |
750 | continue; |
751 | ||
752 | if (mvebu_pcie_port_parse_dt(subnode, dev_ofnode(parent), pcie) < 0) { | |
753 | free(pcie); | |
754 | continue; | |
755 | } | |
94f453ea | 756 | |
537b0142 T |
757 | /* |
758 | * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped | |
759 | * into SoCs address space. Each controller will map 128M of MEM | |
760 | * and 64K of I/O space when registered. | |
761 | */ | |
762 | ||
763 | if (resource_size(&mem) >= SZ_128M) { | |
764 | pcie->mem.start = mem.start; | |
765 | pcie->mem.end = mem.start + SZ_128M - 1; | |
766 | mem.start += SZ_128M; | |
767 | } else { | |
afef9f42 | 768 | printf("%s: unable to assign mbus window for mem\n", pcie->name); |
537b0142 T |
769 | pcie->mem.start = 0; |
770 | pcie->mem.end = -1; | |
771 | } | |
772 | ||
773 | if (resource_size(&io) >= SZ_64K) { | |
774 | pcie->io.start = io.start; | |
775 | pcie->io.end = io.start + SZ_64K - 1; | |
776 | io.start += SZ_64K; | |
777 | } else { | |
afef9f42 | 778 | printf("%s: unable to assign mbus window for io\n", pcie->name); |
537b0142 T |
779 | pcie->io.start = 0; |
780 | pcie->io.end = -1; | |
781 | } | |
782 | ||
afef9f42 T |
783 | ports_pcie[ports_count] = pcie; |
784 | ports_nodes[ports_count] = subnode; | |
785 | ports_count++; | |
786 | } | |
787 | ||
788 | /* Second phase: Setup all PCIe links (do not enable them yet) */ | |
789 | for (i = 0; i < ports_count; i++) | |
790 | mvebu_pcie_setup_link(ports_pcie[i]); | |
791 | ||
792 | /* Third phase: Enable all PCIe links and create for each UCLASS_PCI device */ | |
793 | for (i = 0; i < ports_count; i++) { | |
794 | pcie = ports_pcie[i]; | |
795 | subnode = ports_nodes[i]; | |
796 | ||
797 | /* | |
798 | * PCIe link can be enabled only after all PCIe links were | |
799 | * properly configured. This is because more PCIe links shares | |
800 | * one enable bit and some PCIe links cannot be enabled | |
801 | * individually. | |
802 | */ | |
803 | if (mvebu_pcie_enable_link(pcie, subnode) < 0) { | |
804 | free(pcie); | |
805 | continue; | |
806 | } | |
807 | ||
94f453ea | 808 | /* Create child device UCLASS_PCI and bind it */ |
734206dd SG |
809 | device_bind(parent, &pcie_mvebu_drv, pcie->name, pcie, subnode, |
810 | &dev); | |
9c28d61c | 811 | } |
94f453ea | 812 | |
afef9f42 T |
813 | free(ports_pcie); |
814 | free(ports_nodes); | |
815 | ||
94f453ea | 816 | return 0; |
9c28d61c | 817 | } |
94f453ea SR |
818 | |
819 | static const struct udevice_id mvebu_pcie_ids[] = { | |
820 | { .compatible = "marvell,armada-xp-pcie" }, | |
821 | { .compatible = "marvell,armada-370-pcie" }, | |
43640713 | 822 | { .compatible = "marvell,kirkwood-pcie" }, |
94f453ea SR |
823 | { } |
824 | }; | |
825 | ||
826 | U_BOOT_DRIVER(pcie_mvebu_base) = { | |
827 | .name = "pcie_mvebu_base", | |
828 | .id = UCLASS_MISC, | |
829 | .of_match = mvebu_pcie_ids, | |
830 | .bind = mvebu_pcie_bind, | |
831 | }; |