[thirdparty/u-boot.git] / drivers / phy / meson-gxl-usb2.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Meson GXL and GXM USB2 PHY driver
 *
 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
 * Copyright (C) 2018 BayLibre, SAS
 * Author: Neil Armstrong <narmstron@baylibre.com>
 */

#include <common.h>
#include <malloc.h>
#include <asm/io.h>
#include <bitfield.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <generic-phy.h>
#include <regmap.h>
#include <linux/delay.h>
#include <linux/printk.h>
#include <linux/usb/otg.h>

#include <asm/arch/usb-gx.h>

#include <linux/bitops.h>
#include <linux/compat.h>

/* bits [31:27] are read-only */
#define U2P_R0							0x0
	#define U2P_R0_BYPASS_SEL				BIT(0)
	#define U2P_R0_BYPASS_DM_EN				BIT(1)
	#define U2P_R0_BYPASS_DP_EN				BIT(2)
	#define U2P_R0_TXBITSTUFF_ENH				BIT(3)
	#define U2P_R0_TXBITSTUFF_EN				BIT(4)
	#define U2P_R0_DM_PULLDOWN				BIT(5)
	#define U2P_R0_DP_PULLDOWN				BIT(6)
	#define U2P_R0_DP_VBUS_VLD_EXT_SEL			BIT(7)
	#define U2P_R0_DP_VBUS_VLD_EXT				BIT(8)
	#define U2P_R0_ADP_PRB_EN				BIT(9)
	#define U2P_R0_ADP_DISCHARGE				BIT(10)
	#define U2P_R0_ADP_CHARGE				BIT(11)
	#define U2P_R0_DRV_VBUS					BIT(12)
	#define U2P_R0_ID_PULLUP				BIT(13)
	#define U2P_R0_LOOPBACK_EN_B				BIT(14)
	#define U2P_R0_OTG_DISABLE				BIT(15)
	#define U2P_R0_COMMON_ONN				BIT(16)
	#define U2P_R0_FSEL_MASK				GENMASK(19, 17)
	#define U2P_R0_REF_CLK_SEL_MASK				GENMASK(21, 20)
	#define U2P_R0_POWER_ON_RESET				BIT(22)
	#define U2P_R0_V_ATE_TEST_EN_B_MASK			GENMASK(24, 23)
	#define U2P_R0_ID_SET_ID_DQ				BIT(25)
	#define U2P_R0_ATE_RESET				BIT(26)
	#define U2P_R0_FSV_MINUS				BIT(27)
	#define U2P_R0_FSV_PLUS					BIT(28)
	#define U2P_R0_BYPASS_DM_DATA				BIT(29)
	#define U2P_R0_BYPASS_DP_DATA				BIT(30)

#define U2P_R1							0x4
	#define U2P_R1_BURN_IN_TEST				BIT(0)
	#define U2P_R1_ACA_ENABLE				BIT(1)
	#define U2P_R1_DCD_ENABLE				BIT(2)
	#define U2P_R1_VDAT_SRC_EN_B				BIT(3)
	#define U2P_R1_VDAT_DET_EN_B				BIT(4)
	#define U2P_R1_CHARGES_SEL				BIT(5)
	#define U2P_R1_TX_PREEMP_PULSE_TUNE			BIT(6)
	#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK			GENMASK(8, 7)
	#define U2P_R1_TX_RES_TUNE_MASK				GENMASK(10, 9)
	#define U2P_R1_TX_RISE_TUNE_MASK			GENMASK(12, 11)
	#define U2P_R1_TX_VREF_TUNE_MASK			GENMASK(16, 13)
	#define U2P_R1_TX_FSLS_TUNE_MASK			GENMASK(20, 17)
	#define U2P_R1_TX_HSXV_TUNE_MASK			GENMASK(22, 21)
	#define U2P_R1_OTG_TUNE_MASK				GENMASK(25, 23)
	#define U2P_R1_SQRX_TUNE_MASK				GENMASK(28, 26)
	#define U2P_R1_COMP_DIS_TUNE_MASK			GENMASK(31, 29)

/* bits [31:14] are read-only */
#define U2P_R2							0x8
	#define U2P_R2_TESTDATA_IN_MASK				GENMASK(7, 0)
	#define U2P_R2_TESTADDR_MASK				GENMASK(11, 8)
	#define U2P_R2_TESTDATA_OUT_SEL				BIT(12)
	#define U2P_R2_TESTCLK					BIT(13)
	#define U2P_R2_TESTDATA_OUT_MASK			GENMASK(17, 14)
	#define U2P_R2_ACA_PIN_RANGE_C				BIT(18)
	#define U2P_R2_ACA_PIN_RANGE_B				BIT(19)
	#define U2P_R2_ACA_PIN_RANGE_A				BIT(20)
	#define U2P_R2_ACA_PIN_GND				BIT(21)
	#define U2P_R2_ACA_PIN_FLOAT				BIT(22)
	#define U2P_R2_CHARGE_DETECT				BIT(23)
	#define U2P_R2_DEVICE_SESSION_VALID			BIT(24)
	#define U2P_R2_ADP_PROBE				BIT(25)
	#define U2P_R2_ADP_SENSE				BIT(26)
	#define U2P_R2_SESSION_END				BIT(27)
	#define U2P_R2_VBUS_VALID				BIT(28)
	#define U2P_R2_B_VALID					BIT(29)
	#define U2P_R2_A_VALID					BIT(30)
	#define U2P_R2_ID_DIG					BIT(31)

#define U2P_R3							0xc

#define RESET_COMPLETE_TIME				500

struct phy_meson_gxl_usb2_priv {
	struct regmap		*regmap;
#if CONFIG_IS_ENABLED(CLK)
	struct clk		clk;
#endif
};

static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv)
{
	uint val;

	regmap_read(priv->regmap, U2P_R0, &val);

	/* reset the PHY and wait until settings are stabilized */
	val |= U2P_R0_POWER_ON_RESET;
	regmap_write(priv->regmap, U2P_R0, val);
	udelay(RESET_COMPLETE_TIME);

	val &= ~U2P_R0_POWER_ON_RESET;
	regmap_write(priv->regmap, U2P_R0, val);
	udelay(RESET_COMPLETE_TIME);
}

void phy_meson_gxl_usb2_set_mode(struct phy *phy, enum usb_dr_mode mode)
{
	struct udevice *dev = phy->dev;
	struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
	uint val;

	regmap_read(priv->regmap, U2P_R0, &val);

	switch (mode) {
	case USB_DR_MODE_UNKNOWN:
	case USB_DR_MODE_HOST:
	case USB_DR_MODE_OTG:
		val |= U2P_R0_DM_PULLDOWN;
		val |= U2P_R0_DP_PULLDOWN;
		val &= ~U2P_R0_ID_PULLUP;
		break;

	case USB_DR_MODE_PERIPHERAL:
		val &= ~U2P_R0_DM_PULLDOWN;
		val &= ~U2P_R0_DP_PULLDOWN;
		val |= U2P_R0_ID_PULLUP;
		break;
	}

	regmap_write(priv->regmap, U2P_R0, val);

	phy_meson_gxl_usb2_reset(priv);
}

static int phy_meson_gxl_usb2_power_on(struct phy *phy)
{
	struct udevice *dev = phy->dev;
	struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
	uint val;

	regmap_read(priv->regmap, U2P_R0, &val);
	/* power on the PHY by taking it out of reset mode */
	val &= ~U2P_R0_POWER_ON_RESET;
	regmap_write(priv->regmap, U2P_R0, val);

	phy_meson_gxl_usb2_set_mode(phy, USB_DR_MODE_HOST);

	return 0;
}

static int phy_meson_gxl_usb2_power_off(struct phy *phy)
{
	struct udevice *dev = phy->dev;
	struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
	uint val;

	regmap_read(priv->regmap, U2P_R0, &val);
	/* power off the PHY by putting it into reset mode */
	val |= U2P_R0_POWER_ON_RESET;
	regmap_write(priv->regmap, U2P_R0, val);

	return 0;
}

struct phy_ops meson_gxl_usb2_phy_ops = {
	.power_on = phy_meson_gxl_usb2_power_on,
	.power_off = phy_meson_gxl_usb2_power_off,
};

int meson_gxl_usb2_phy_probe(struct udevice *dev)
{
	struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
	int ret;

	ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
	if (ret)
		return ret;

#if CONFIG_IS_ENABLED(CLK)
	ret = clk_get_by_index(dev, 0, &priv->clk);
	if (ret < 0)
		return ret;

	ret = clk_enable(&priv->clk);
	if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
		pr_err("failed to enable PHY clock\n");
		return ret;
	}
#endif

	return 0;
}

static const struct udevice_id meson_gxl_usb2_phy_ids[] = {
	{ .compatible = "amlogic,meson-gxl-usb2-phy" },
	{ }
};

U_BOOT_DRIVER(meson_gxl_usb2_phy) = {
	.name = "meson_gxl_usb2_phy",
	.id = UCLASS_PHY,
	.of_match = meson_gxl_usb2_phy_ids,
	.probe = meson_gxl_usb2_phy_probe,
	.ops = &meson_gxl_usb2_phy_ops,
	.priv_auto	= sizeof(struct phy_meson_gxl_usb2_priv),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
2960e27e NA	2	/*
	3	* Meson GXL and GXM USB2 PHY driver
	4	*
	5	* Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
	6	* Copyright (C) 2018 BayLibre, SAS
	7	* Author: Neil Armstrong <narmstron@baylibre.com>
2960e27e NA	8	*/
2960e27e NA	9
d678a59d	10	#include <common.h>
336d4615	11	#include <malloc.h>
2960e27e NA	12	#include <asm/io.h>
2960e27e NA	13	#include <bitfield.h>
1e94b46f	14	#include <clk.h>
2960e27e NA	15	#include <dm.h>
	16	#include <errno.h>
	17	#include <generic-phy.h>
	18	#include <regmap.h>
c05ed00a	19	#include <linux/delay.h>
1e94b46f	20	#include <linux/printk.h>
838c0af9 NA	21	#include <linux/usb/otg.h>
	22
	23	#include <asm/arch/usb-gx.h>
2960e27e NA	24
	25	#include <linux/bitops.h>
	26	#include <linux/compat.h>
	27
2960e27e NA	28	/* bits [31:27] are read-only */
	29	#define U2P_R0 0x0
	30	#define U2P_R0_BYPASS_SEL BIT(0)
	31	#define U2P_R0_BYPASS_DM_EN BIT(1)
	32	#define U2P_R0_BYPASS_DP_EN BIT(2)
	33	#define U2P_R0_TXBITSTUFF_ENH BIT(3)
	34	#define U2P_R0_TXBITSTUFF_EN BIT(4)
	35	#define U2P_R0_DM_PULLDOWN BIT(5)
	36	#define U2P_R0_DP_PULLDOWN BIT(6)
	37	#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7)
	38	#define U2P_R0_DP_VBUS_VLD_EXT BIT(8)
	39	#define U2P_R0_ADP_PRB_EN BIT(9)
	40	#define U2P_R0_ADP_DISCHARGE BIT(10)
	41	#define U2P_R0_ADP_CHARGE BIT(11)
	42	#define U2P_R0_DRV_VBUS BIT(12)
	43	#define U2P_R0_ID_PULLUP BIT(13)
	44	#define U2P_R0_LOOPBACK_EN_B BIT(14)
	45	#define U2P_R0_OTG_DISABLE BIT(15)
	46	#define U2P_R0_COMMON_ONN BIT(16)
	47	#define U2P_R0_FSEL_MASK GENMASK(19, 17)
	48	#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20)
	49	#define U2P_R0_POWER_ON_RESET BIT(22)
	50	#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23)
	51	#define U2P_R0_ID_SET_ID_DQ BIT(25)
	52	#define U2P_R0_ATE_RESET BIT(26)
	53	#define U2P_R0_FSV_MINUS BIT(27)
	54	#define U2P_R0_FSV_PLUS BIT(28)
	55	#define U2P_R0_BYPASS_DM_DATA BIT(29)
	56	#define U2P_R0_BYPASS_DP_DATA BIT(30)
	57
	58	#define U2P_R1 0x4
	59	#define U2P_R1_BURN_IN_TEST BIT(0)
	60	#define U2P_R1_ACA_ENABLE BIT(1)
	61	#define U2P_R1_DCD_ENABLE BIT(2)
	62	#define U2P_R1_VDAT_SRC_EN_B BIT(3)
	63	#define U2P_R1_VDAT_DET_EN_B BIT(4)
	64	#define U2P_R1_CHARGES_SEL BIT(5)
	65	#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6)
	66	#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7)
	67	#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9)
	68	#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11)
	69	#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13)
	70	#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17)
	71	#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21)
	72	#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23)
	73	#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26)
	74	#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29)
	75
	76	/* bits [31:14] are read-only */
	77	#define U2P_R2 0x8
	78	#define U2P_R2_TESTDATA_IN_MASK GENMASK(7, 0)
	79	#define U2P_R2_TESTADDR_MASK GENMASK(11, 8)
	80	#define U2P_R2_TESTDATA_OUT_SEL BIT(12)
	81	#define U2P_R2_TESTCLK BIT(13)
	82	#define U2P_R2_TESTDATA_OUT_MASK GENMASK(17, 14)
	83	#define U2P_R2_ACA_PIN_RANGE_C BIT(18)
	84	#define U2P_R2_ACA_PIN_RANGE_B BIT(19)
	85	#define U2P_R2_ACA_PIN_RANGE_A BIT(20)
	86	#define U2P_R2_ACA_PIN_GND BIT(21)
	87	#define U2P_R2_ACA_PIN_FLOAT BIT(22)
	88	#define U2P_R2_CHARGE_DETECT BIT(23)
	89	#define U2P_R2_DEVICE_SESSION_VALID BIT(24)
	90	#define U2P_R2_ADP_PROBE BIT(25)
	91	#define U2P_R2_ADP_SENSE BIT(26)
92	#define U2P_R2_SESSION_END BIT(27)
93	#define U2P_R2_VBUS_VALID BIT(28)
94	#define U2P_R2_B_VALID BIT(29)
95	#define U2P_R2_A_VALID BIT(30)
96	#define U2P_R2_ID_DIG BIT(31)
97
98	#define U2P_R3 0xc
99
100	#define RESET_COMPLETE_TIME 500
101
102	struct phy_meson_gxl_usb2_priv {
103	struct regmap *regmap;
2960e27e NA	104	#if CONFIG_IS_ENABLED(CLK)
	105	struct clk clk;
	106	#endif
	107	};
	108
	109	static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv)
	110	{
	111	uint val;
	112
	113	regmap_read(priv->regmap, U2P_R0, &val);
	114
	115	/* reset the PHY and wait until settings are stabilized */
	116	val \|= U2P_R0_POWER_ON_RESET;
	117	regmap_write(priv->regmap, U2P_R0, val);
	118	udelay(RESET_COMPLETE_TIME);
	119
	120	val &= ~U2P_R0_POWER_ON_RESET;
	121	regmap_write(priv->regmap, U2P_R0, val);
	122	udelay(RESET_COMPLETE_TIME);
	123	}
	124
838c0af9	125	void phy_meson_gxl_usb2_set_mode(struct phy *phy, enum usb_dr_mode mode)
2960e27e	126	{
838c0af9 NA	127	struct udevice *dev = phy->dev;
838c0af9 NA	128	struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
2960e27e NA	129	uint val;
	130
	131	regmap_read(priv->regmap, U2P_R0, &val);
838c0af9 NA	132
	133	switch (mode) {
	134	case USB_DR_MODE_UNKNOWN:
	135	case USB_DR_MODE_HOST:
	136	case USB_DR_MODE_OTG:
	137	val \|= U2P_R0_DM_PULLDOWN;
	138	val \|= U2P_R0_DP_PULLDOWN;
	139	val &= ~U2P_R0_ID_PULLUP;
	140	break;
	141
	142	case USB_DR_MODE_PERIPHERAL:
	143	val &= ~U2P_R0_DM_PULLDOWN;
	144	val &= ~U2P_R0_DP_PULLDOWN;
	145	val \|= U2P_R0_ID_PULLUP;
	146	break;
	147	}
	148
2960e27e NA	149	regmap_write(priv->regmap, U2P_R0, val);
	150
	151	phy_meson_gxl_usb2_reset(priv);
	152	}
	153
	154	static int phy_meson_gxl_usb2_power_on(struct phy *phy)
	155	{
	156	struct udevice *dev = phy->dev;
	157	struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
	158	uint val;
	159
	160	regmap_read(priv->regmap, U2P_R0, &val);
	161	/* power on the PHY by taking it out of reset mode */
	162	val &= ~U2P_R0_POWER_ON_RESET;
	163	regmap_write(priv->regmap, U2P_R0, val);
	164
838c0af9	165	phy_meson_gxl_usb2_set_mode(phy, USB_DR_MODE_HOST);
2960e27e	166
2960e27e NA	167	return 0;
	168	}
	169
	170	static int phy_meson_gxl_usb2_power_off(struct phy *phy)
	171	{
	172	struct udevice *dev = phy->dev;
	173	struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
	174	uint val;
	175
	176	regmap_read(priv->regmap, U2P_R0, &val);
	177	/* power off the PHY by putting it into reset mode */
	178	val \|= U2P_R0_POWER_ON_RESET;
	179	regmap_write(priv->regmap, U2P_R0, val);
	180
2960e27e NA	181	return 0;
	182	}
	183
	184	struct phy_ops meson_gxl_usb2_phy_ops = {
	185	.power_on = phy_meson_gxl_usb2_power_on,
	186	.power_off = phy_meson_gxl_usb2_power_off,
	187	};
	188
	189	int meson_gxl_usb2_phy_probe(struct udevice *dev)
	190	{
	191	struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
	192	int ret;
	193
d3581236	194	ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
2960e27e NA	195	if (ret)
	196	return ret;
	197
	198	#if CONFIG_IS_ENABLED(CLK)
	199	ret = clk_get_by_index(dev, 0, &priv->clk);
	200	if (ret < 0)
	201	return ret;
	202
	203	ret = clk_enable(&priv->clk);
	204	if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
	205	pr_err("failed to enable PHY clock\n");
2960e27e NA	206	return ret;
	207	}
	208	#endif
	209
2960e27e NA	210	return 0;
	211	}
	212
	213	static const struct udevice_id meson_gxl_usb2_phy_ids[] = {
	214	{ .compatible = "amlogic,meson-gxl-usb2-phy" },
	215	{ }
	216	};
	217
	218	U_BOOT_DRIVER(meson_gxl_usb2_phy) = {
	219	.name = "meson_gxl_usb2_phy",
	220	.id = UCLASS_PHY,
	221	.of_match = meson_gxl_usb2_phy_ids,
	222	.probe = meson_gxl_usb2_phy_probe,
	223	.ops = &meson_gxl_usb2_phy_ops,
41575d8e	224	.priv_auto = sizeof(struct phy_meson_gxl_usb2_priv),
2960e27e	225	};