[thirdparty/u-boot.git] / drivers / phy / phy-rcar-gen3.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Renesas RCar Gen3 USB PHY driver
 *
 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
 */

#include <common.h>
#include <clk.h>
#include <div64.h>
#include <dm.h>
#include <fdtdec.h>
#include <generic-phy.h>
#include <malloc.h>
#include <reset.h>
#include <syscon.h>
#include <usb.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/printk.h>
#include <power/regulator.h>

/* USB2.0 Host registers (original offset is +0x200) */
#define USB2_INT_ENABLE		0x000
#define USB2_USBCTR		0x00c
#define USB2_SPD_RSM_TIMSET	0x10c
#define USB2_OC_TIMSET		0x110
#define USB2_COMMCTRL		0x600
#define USB2_OBINTSTA		0x604
#define USB2_OBINTEN		0x608
#define USB2_VBCTRL		0x60c
#define USB2_LINECTRL1		0x610
#define USB2_ADPCTRL		0x630

/* USBCTR */
#define USB2_USBCTR_PLL_RST	BIT(1)

/* SPD_RSM_TIMSET */
#define USB2_SPD_RSM_TIMSET_INIT	0x014e029b

/* OC_TIMSET */
#define USB2_OC_TIMSET_INIT		0x000209ab

/* COMMCTRL */
#define USB2_COMMCTRL_OTG_PERI		BIT(31)	/* 1 = Peripheral mode */

/* LINECTRL1 */
#define USB2_LINECTRL1_DP_RPD		BIT(18)
#define USB2_LINECTRL1_DM_RPD		BIT(16)

/* ADPCTRL */
#define USB2_ADPCTRL_DRVVBUS		BIT(4)

struct rcar_gen3_phy {
	fdt_addr_t	regs;
	struct clk	clk;
	struct udevice	*vbus_supply;
};

static int rcar_gen3_phy_phy_init(struct phy *phy)
{
	struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);

	/* Initialize USB2 part */
	writel(0, priv->regs + USB2_INT_ENABLE);
	writel(USB2_SPD_RSM_TIMSET_INIT, priv->regs + USB2_SPD_RSM_TIMSET);
	writel(USB2_OC_TIMSET_INIT, priv->regs + USB2_OC_TIMSET);

	setbits_le32(priv->regs + USB2_LINECTRL1,
		     USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);

	clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);

	setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS);

	return 0;
}

static int rcar_gen3_phy_phy_power_on(struct phy *phy)
{
	struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
	int ret;

	if (priv->vbus_supply) {
		ret = regulator_set_enable(priv->vbus_supply, true);
		if (ret)
			return ret;
	}

	setbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST);
	clrbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST);

	return 0;
}

static int rcar_gen3_phy_phy_power_off(struct phy *phy)
{
	struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);

	if (!priv->vbus_supply)
		return 0;

	return regulator_set_enable(priv->vbus_supply, false);
}

static const struct phy_ops rcar_gen3_phy_phy_ops = {
	.init		= rcar_gen3_phy_phy_init,
	.power_on	= rcar_gen3_phy_phy_power_on,
	.power_off	= rcar_gen3_phy_phy_power_off,
};

static int rcar_gen3_phy_probe(struct udevice *dev)
{
	struct rcar_gen3_phy *priv = dev_get_priv(dev);
	int ret;

	priv->regs = dev_read_addr(dev);
	if (priv->regs == FDT_ADDR_T_NONE)
		return -EINVAL;

	ret = device_get_supply_regulator(dev, "vbus-supply",
					  &priv->vbus_supply);
	if (ret && ret != -ENOENT) {
		pr_err("Failed to get PHY regulator\n");
		return ret;
	}

	/* Enable clock */
	ret = clk_get_by_index(dev, 0, &priv->clk);
	if (ret)
		return ret;

	ret = clk_enable(&priv->clk);
	if (ret)
		return ret;

	return 0;
}

static int rcar_gen3_phy_remove(struct udevice *dev)
{
	struct rcar_gen3_phy *priv = dev_get_priv(dev);

	clk_disable(&priv->clk);

	return 0;
}

static const struct udevice_id rcar_gen3_phy_of_match[] = {
	{ .compatible = "renesas,rcar-gen3-usb2-phy", },
	{ },
};

U_BOOT_DRIVER(rcar_gen3_phy) = {
	.name		= "rcar-gen3-phy",
	.id		= UCLASS_PHY,
	.of_match	= rcar_gen3_phy_of_match,
	.ops		= &rcar_gen3_phy_phy_ops,
	.probe		= rcar_gen3_phy_probe,
	.remove		= rcar_gen3_phy_remove,
	.priv_auto	= sizeof(struct rcar_gen3_phy),
};
Commit	Line	Data
6cfc3d66 MV	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Renesas RCar Gen3 USB PHY driver
	4	*
	5	* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
	6	*/
	7
d678a59d	8	#include <common.h>
6cfc3d66 MV	9	#include <clk.h>
	10	#include <div64.h>
	11	#include <dm.h>
	12	#include <fdtdec.h>
	13	#include <generic-phy.h>
336d4615	14	#include <malloc.h>
6cfc3d66 MV	15	#include <reset.h>
	16	#include <syscon.h>
	17	#include <usb.h>
	18	#include <asm/io.h>
	19	#include <linux/bitops.h>
1e94b46f	20	#include <linux/printk.h>
6cfc3d66 MV	21	#include <power/regulator.h>
	22
	23	/* USB2.0 Host registers (original offset is +0x200) */
	24	#define USB2_INT_ENABLE 0x000
	25	#define USB2_USBCTR 0x00c
	26	#define USB2_SPD_RSM_TIMSET 0x10c
	27	#define USB2_OC_TIMSET 0x110
	28	#define USB2_COMMCTRL 0x600
	29	#define USB2_OBINTSTA 0x604
	30	#define USB2_OBINTEN 0x608
	31	#define USB2_VBCTRL 0x60c
	32	#define USB2_LINECTRL1 0x610
	33	#define USB2_ADPCTRL 0x630
	34
	35	/* USBCTR */
	36	#define USB2_USBCTR_PLL_RST BIT(1)
	37
	38	/* SPD_RSM_TIMSET */
	39	#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
	40
	41	/* OC_TIMSET */
	42	#define USB2_OC_TIMSET_INIT 0x000209ab
	43
	44	/* COMMCTRL */
	45	#define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */
	46
	47	/* LINECTRL1 */
	48	#define USB2_LINECTRL1_DP_RPD BIT(18)
	49	#define USB2_LINECTRL1_DM_RPD BIT(16)
	50
	51	/* ADPCTRL */
	52	#define USB2_ADPCTRL_DRVVBUS BIT(4)
	53
	54	struct rcar_gen3_phy {
	55	fdt_addr_t regs;
	56	struct clk clk;
	57	struct udevice *vbus_supply;
	58	};
	59
	60	static int rcar_gen3_phy_phy_init(struct phy *phy)
	61	{
	62	struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
	63
	64	/* Initialize USB2 part */
	65	writel(0, priv->regs + USB2_INT_ENABLE);
	66	writel(USB2_SPD_RSM_TIMSET_INIT, priv->regs + USB2_SPD_RSM_TIMSET);
	67	writel(USB2_OC_TIMSET_INIT, priv->regs + USB2_OC_TIMSET);
	68
	69	setbits_le32(priv->regs + USB2_LINECTRL1,
	70	USB2_LINECTRL1_DP_RPD \| USB2_LINECTRL1_DM_RPD);
	71
	72	clrbits_le32(priv->regs + USB2_COMMCTRL, USB2_COMMCTRL_OTG_PERI);
	73
	74	setbits_le32(priv->regs + USB2_ADPCTRL, USB2_ADPCTRL_DRVVBUS);
	75
	76	return 0;
	77	}
	78
	79	static int rcar_gen3_phy_phy_power_on(struct phy *phy)
	80	{
	81	struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
	82	int ret;
	83
	84	if (priv->vbus_supply) {
85	ret = regulator_set_enable(priv->vbus_supply, true);
86	if (ret)
87	return ret;
88	}
89
90	setbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST);
91	clrbits_le32(priv->regs + USB2_USBCTR, USB2_USBCTR_PLL_RST);
92
93	return 0;
94	}
95
96	static int rcar_gen3_phy_phy_power_off(struct phy *phy)
97	{
98	struct rcar_gen3_phy *priv = dev_get_priv(phy->dev);
99
100	if (!priv->vbus_supply)
101	return 0;
102
103	return regulator_set_enable(priv->vbus_supply, false);
104	}
105
106	static const struct phy_ops rcar_gen3_phy_phy_ops = {
107	.init = rcar_gen3_phy_phy_init,
108	.power_on = rcar_gen3_phy_phy_power_on,
109	.power_off = rcar_gen3_phy_phy_power_off,
110	};
111
112	static int rcar_gen3_phy_probe(struct udevice *dev)
113	{
114	struct rcar_gen3_phy *priv = dev_get_priv(dev);
115	int ret;
116
117	priv->regs = dev_read_addr(dev);
118	if (priv->regs == FDT_ADDR_T_NONE)
119	return -EINVAL;
120
121	ret = device_get_supply_regulator(dev, "vbus-supply",
122	&priv->vbus_supply);
123	if (ret && ret != -ENOENT) {
124	pr_err("Failed to get PHY regulator\n");
125	return ret;
126	}
127
128	/* Enable clock */
129	ret = clk_get_by_index(dev, 0, &priv->clk);
130	if (ret)
131	return ret;
132
133	ret = clk_enable(&priv->clk);
134	if (ret)
135	return ret;
136
137	return 0;
138	}
139
140	static int rcar_gen3_phy_remove(struct udevice *dev)
141	{
142	struct rcar_gen3_phy *priv = dev_get_priv(dev);
143
144	clk_disable(&priv->clk);
6cfc3d66 MV	145
	146	return 0;
	147	}
	148
	149	static const struct udevice_id rcar_gen3_phy_of_match[] = {
	150	{ .compatible = "renesas,rcar-gen3-usb2-phy", },
	151	{ },
	152	};
	153
	154	U_BOOT_DRIVER(rcar_gen3_phy) = {
	155	.name = "rcar-gen3-phy",
	156	.id = UCLASS_PHY,
	157	.of_match = rcar_gen3_phy_of_match,
	158	.ops = &rcar_gen3_phy_phy_ops,
	159	.probe = rcar_gen3_phy_probe,
	160	.remove = rcar_gen3_phy_remove,
41575d8e	161	.priv_auto = sizeof(struct rcar_gen3_phy),
6cfc3d66	162	};