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7981c001 MW |
1 | /* |
2 | * Core pinctrl/GPIO driver for Intel GPIO controllers | |
3 | * | |
4 | * Copyright (C) 2015, Intel Corporation | |
5 | * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> | |
6 | * Mika Westerberg <mika.westerberg@linux.intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef PINCTRL_INTEL_H | |
14 | #define PINCTRL_INTEL_H | |
15 | ||
16 | struct pinctrl_pin_desc; | |
17 | struct platform_device; | |
18 | struct device; | |
19 | ||
20 | /** | |
21 | * struct intel_pingroup - Description about group of pins | |
22 | * @name: Name of the groups | |
23 | * @pins: All pins in this group | |
24 | * @npins: Number of pins in this groups | |
1f6b419b MW |
25 | * @mode: Native mode in which the group is muxed out @pins. Used if @modes |
26 | * is %NULL. | |
27 | * @modes: If not %NULL this will hold mode for each pin in @pins | |
7981c001 MW |
28 | */ |
29 | struct intel_pingroup { | |
30 | const char *name; | |
31 | const unsigned *pins; | |
32 | size_t npins; | |
33 | unsigned short mode; | |
1f6b419b | 34 | const unsigned *modes; |
7981c001 MW |
35 | }; |
36 | ||
37 | /** | |
38 | * struct intel_function - Description about a function | |
39 | * @name: Name of the function | |
40 | * @groups: An array of groups for this function | |
41 | * @ngroups: Number of groups in @groups | |
42 | */ | |
43 | struct intel_function { | |
44 | const char *name; | |
45 | const char * const *groups; | |
46 | size_t ngroups; | |
47 | }; | |
48 | ||
919eb475 MW |
49 | /** |
50 | * struct intel_padgroup - Hardware pad group information | |
51 | * @reg_num: GPI_IS register number | |
52 | * @base: Starting pin of this group | |
53 | * @size: Size of this group (maximum is 32). | |
54 | * @padown_num: PAD_OWN register number (assigned by the core driver) | |
55 | * | |
56 | * If pad groups of a community are not the same size, use this structure | |
57 | * to specify them. | |
58 | */ | |
59 | struct intel_padgroup { | |
60 | unsigned reg_num; | |
61 | unsigned base; | |
62 | unsigned size; | |
63 | unsigned padown_num; | |
64 | }; | |
65 | ||
7981c001 MW |
66 | /** |
67 | * struct intel_community - Intel pin community description | |
68 | * @barno: MMIO BAR number where registers for this community reside | |
69 | * @padown_offset: Register offset of PAD_OWN register from @regs. If %0 | |
70 | * then there is no support for owner. | |
71 | * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then | |
72 | * locking is not supported. | |
73 | * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it | |
74 | * is assumed that the host owns the pin (rather than | |
75 | * ACPI). | |
cf769bd8 MW |
76 | * @is_offset: Register offset of GPI_IS from @regs. If %0 then uses the |
77 | * default (%0x100). | |
7981c001 MW |
78 | * @ie_offset: Register offset of GPI_IE from @regs. |
79 | * @pin_base: Starting pin of pins in this community | |
618a919b | 80 | * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, |
919eb475 MW |
81 | * HOSTSW_OWN, GPI_IS, GPI_IE, etc. Used when @gpps is %NULL. |
82 | * @gpp_num_padown_regs: Number of pad registers each pad group consumes at | |
83 | * minimum. Use %0 if the number of registers can be | |
84 | * determined by the size of the group. | |
7981c001 | 85 | * @npins: Number of pins in this community |
e57725ea | 86 | * @features: Additional features supported by the hardware |
919eb475 MW |
87 | * @gpps: Pad groups if the controller has variable size pad groups |
88 | * @ngpps: Number of pad groups in this community | |
7981c001 MW |
89 | * @regs: Community specific common registers (reserved for core driver) |
90 | * @pad_regs: Community specific pad registers (reserved for core driver) | |
919eb475 MW |
91 | * |
92 | * Most Intel GPIO host controllers this driver supports each pad group is | |
93 | * of equal size (except the last one). In that case the driver can just | |
94 | * fill in @gpp_size field and let the core driver to handle the rest. If | |
95 | * the controller has pad groups of variable size the client driver can | |
96 | * pass custom @gpps and @ngpps instead. | |
7981c001 MW |
97 | */ |
98 | struct intel_community { | |
99 | unsigned barno; | |
100 | unsigned padown_offset; | |
101 | unsigned padcfglock_offset; | |
102 | unsigned hostown_offset; | |
cf769bd8 | 103 | unsigned is_offset; |
7981c001 MW |
104 | unsigned ie_offset; |
105 | unsigned pin_base; | |
618a919b | 106 | unsigned gpp_size; |
919eb475 | 107 | unsigned gpp_num_padown_regs; |
7981c001 | 108 | size_t npins; |
e57725ea | 109 | unsigned features; |
919eb475 MW |
110 | const struct intel_padgroup *gpps; |
111 | size_t ngpps; | |
112 | /* Reserved for the core driver */ | |
7981c001 MW |
113 | void __iomem *regs; |
114 | void __iomem *pad_regs; | |
7981c001 MW |
115 | }; |
116 | ||
e57725ea MW |
117 | /* Additional features supported by the hardware */ |
118 | #define PINCTRL_FEATURE_DEBOUNCE BIT(0) | |
04cc058f | 119 | #define PINCTRL_FEATURE_1K_PD BIT(1) |
e57725ea | 120 | |
1f6b419b MW |
121 | /** |
122 | * PIN_GROUP - Declare a pin group | |
123 | * @n: Name of the group | |
124 | * @p: An array of pins this group consists | |
125 | * @m: Mode which the pins are put when this group is active. Can be either | |
126 | * a single integer or an array of integers in which case mode is per | |
127 | * pin. | |
128 | */ | |
129 | #define PIN_GROUP(n, p, m) \ | |
130 | { \ | |
131 | .name = (n), \ | |
132 | .pins = (p), \ | |
133 | .npins = ARRAY_SIZE((p)), \ | |
134 | .mode = __builtin_choose_expr( \ | |
135 | __builtin_constant_p((m)), (m), 0), \ | |
136 | .modes = __builtin_choose_expr( \ | |
137 | __builtin_constant_p((m)), NULL, (m)), \ | |
7981c001 MW |
138 | } |
139 | ||
140 | #define FUNCTION(n, g) \ | |
141 | { \ | |
142 | .name = (n), \ | |
143 | .groups = (g), \ | |
144 | .ngroups = ARRAY_SIZE((g)), \ | |
145 | } | |
146 | ||
147 | /** | |
148 | * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration | |
149 | * @uid: ACPI _UID for the probe driver use if needed | |
150 | * @pins: Array if pins this pinctrl controls | |
151 | * @npins: Number of pins in the array | |
152 | * @groups: Array of pin groups | |
153 | * @ngroups: Number of groups in the array | |
154 | * @functions: Array of functions | |
155 | * @nfunctions: Number of functions in the array | |
156 | * @communities: Array of communities this pinctrl handles | |
157 | * @ncommunities: Number of communities in the array | |
158 | * | |
159 | * The @communities is used as a template by the core driver. It will make | |
160 | * copy of all communities and fill in rest of the information. | |
161 | */ | |
162 | struct intel_pinctrl_soc_data { | |
163 | const char *uid; | |
164 | const struct pinctrl_pin_desc *pins; | |
165 | size_t npins; | |
166 | const struct intel_pingroup *groups; | |
167 | size_t ngroups; | |
168 | const struct intel_function *functions; | |
169 | size_t nfunctions; | |
170 | const struct intel_community *communities; | |
171 | size_t ncommunities; | |
172 | }; | |
173 | ||
174 | int intel_pinctrl_probe(struct platform_device *pdev, | |
175 | const struct intel_pinctrl_soc_data *soc_data); | |
7981c001 MW |
176 | #ifdef CONFIG_PM_SLEEP |
177 | int intel_pinctrl_suspend(struct device *dev); | |
178 | int intel_pinctrl_resume(struct device *dev); | |
179 | #endif | |
180 | ||
181 | #endif /* PINCTRL_INTEL_H */ |