[thirdparty/u-boot.git] / drivers / power / domain / mtk-power-domain.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2018 MediaTek Inc.
 * Author: Ryder Lee <ryder.lee@mediatek.com>
 */

#include <clk.h>
#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <power-domain-uclass.h>
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/iopoll.h>

#include <dt-bindings/power/mt7623-power.h>
#include <dt-bindings/power/mt7629-power.h>

#define SPM_EN			(0xb16 << 16 | 0x1)
#define SPM_VDE_PWR_CON		0x0210
#define SPM_MFG_PWR_CON		0x0214
#define SPM_ISP_PWR_CON		0x0238
#define SPM_DIS_PWR_CON		0x023c
#define SPM_CONN_PWR_CON	0x0280
#define SPM_BDP_PWR_CON		0x029c
#define SPM_ETH_PWR_CON		0x02a0
#define SPM_HIF_PWR_CON		0x02a4
#define SPM_IFR_MSC_PWR_CON	0x02a8
#define SPM_ETHSYS_PWR_CON	0x2e0
#define SPM_HIF0_PWR_CON	0x2e4
#define SPM_HIF1_PWR_CON	0x2e8
#define SPM_PWR_STATUS		0x60c
#define SPM_PWR_STATUS_2ND	0x610

#define PWR_RST_B_BIT		BIT(0)
#define PWR_ISO_BIT		BIT(1)
#define PWR_ON_BIT		BIT(2)
#define PWR_ON_2ND_BIT		BIT(3)
#define PWR_CLK_DIS_BIT		BIT(4)

#define PWR_STATUS_CONN		BIT(1)
#define PWR_STATUS_DISP		BIT(3)
#define PWR_STATUS_MFG		BIT(4)
#define PWR_STATUS_ISP		BIT(5)
#define PWR_STATUS_VDEC		BIT(7)
#define PWR_STATUS_BDP		BIT(14)
#define PWR_STATUS_ETH		BIT(15)
#define PWR_STATUS_HIF		BIT(16)
#define PWR_STATUS_IFR_MSC	BIT(17)
#define PWR_STATUS_ETHSYS	BIT(24)
#define PWR_STATUS_HIF0		BIT(25)
#define PWR_STATUS_HIF1		BIT(26)

/* Infrasys configuration */
#define INFRA_TOPDCM_CTRL	0x10
#define INFRA_TOPAXI_PROT_EN	0x220
#define INFRA_TOPAXI_PROT_STA1	0x228

#define DCM_TOP_EN		BIT(0)

enum scp_domain_type {
	SCPSYS_MT7622,
	SCPSYS_MT7623,
	SCPSYS_MT7629,
};

struct scp_domain;

struct scp_domain_data {
	struct scp_domain *scpd;
	u32 sta_mask;
	int ctl_offs;
	u32 sram_pdn_bits;
	u32 sram_pdn_ack_bits;
	u32 bus_prot_mask;
};

struct scp_domain {
	void __iomem *base;
	void __iomem *infracfg;
	enum scp_domain_type type;
	struct scp_domain_data *data;
};

static struct scp_domain_data scp_domain_mt7623[] = {
	[MT7623_POWER_DOMAIN_CONN] = {
		.sta_mask = PWR_STATUS_CONN,
		.ctl_offs = SPM_CONN_PWR_CON,
		.bus_prot_mask = BIT(8) | BIT(2),
	},
	[MT7623_POWER_DOMAIN_DISP] = {
		.sta_mask = PWR_STATUS_DISP,
		.ctl_offs = SPM_DIS_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.bus_prot_mask = BIT(2),
	},
	[MT7623_POWER_DOMAIN_MFG] = {
		.sta_mask = PWR_STATUS_MFG,
		.ctl_offs = SPM_MFG_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(12, 12),
	},
	[MT7623_POWER_DOMAIN_VDEC] = {
		.sta_mask = PWR_STATUS_VDEC,
		.ctl_offs = SPM_VDE_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(12, 12),
	},
	[MT7623_POWER_DOMAIN_ISP] = {
		.sta_mask = PWR_STATUS_ISP,
		.ctl_offs = SPM_ISP_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(13, 12),
	},
	[MT7623_POWER_DOMAIN_BDP] = {
		.sta_mask = PWR_STATUS_BDP,
		.ctl_offs = SPM_BDP_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
	},
	[MT7623_POWER_DOMAIN_ETH] = {
		.sta_mask = PWR_STATUS_ETH,
		.ctl_offs = SPM_ETH_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(15, 12),
	},
	[MT7623_POWER_DOMAIN_HIF] = {
		.sta_mask = PWR_STATUS_HIF,
		.ctl_offs = SPM_HIF_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(15, 12),
	},
	[MT7623_POWER_DOMAIN_IFR_MSC] = {
		.sta_mask = PWR_STATUS_IFR_MSC,
		.ctl_offs = SPM_IFR_MSC_PWR_CON,
	},
};

static struct scp_domain_data scp_domain_mt7629[] = {
	[MT7629_POWER_DOMAIN_ETHSYS] = {
		.sta_mask = PWR_STATUS_ETHSYS,
		.ctl_offs = SPM_ETHSYS_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(15, 12),
		.bus_prot_mask = (BIT(3) | BIT(17)),
	},
	[MT7629_POWER_DOMAIN_HIF0] = {
		.sta_mask = PWR_STATUS_HIF0,
		.ctl_offs = SPM_HIF0_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(15, 12),
		.bus_prot_mask = GENMASK(25, 24),
	},
	[MT7629_POWER_DOMAIN_HIF1] = {
		.sta_mask = PWR_STATUS_HIF1,
		.ctl_offs = SPM_HIF1_PWR_CON,
		.sram_pdn_bits = GENMASK(11, 8),
		.sram_pdn_ack_bits = GENMASK(15, 12),
		.bus_prot_mask = GENMASK(28, 26),
	},
};

/**
 * This function enables the bus protection bits for disabled power
 * domains so that the system does not hang when some unit accesses the
 * bus while in power down.
 */
static int mtk_infracfg_set_bus_protection(void __iomem *infracfg,
					   u32 mask)
{
	u32 val;

	clrsetbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask, mask);

	return readl_poll_timeout(infracfg + INFRA_TOPAXI_PROT_STA1, val,
				  (val & mask) == mask, 100);
}

static int mtk_infracfg_clear_bus_protection(void __iomem *infracfg,
					     u32 mask)
{
	u32 val;

	clrbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask);

	return readl_poll_timeout(infracfg + INFRA_TOPAXI_PROT_STA1, val,
				  !(val & mask), 100);
}

static int scpsys_domain_is_on(struct scp_domain_data *data)
{
	struct scp_domain *scpd = data->scpd;
	u32 sta = readl(scpd->base + SPM_PWR_STATUS) &
			data->sta_mask;
	u32 sta2 = readl(scpd->base + SPM_PWR_STATUS_2ND) &
			 data->sta_mask;

	/*
	 * A domain is on when both status bits are set. If only one is set
	 * return an error. This happens while powering up a domain
	 */
	if (sta && sta2)
		return true;
	if (!sta && !sta2)
		return false;

	return -EINVAL;
}

static int scpsys_power_on(struct power_domain *power_domain)
{
	struct scp_domain *scpd = dev_get_priv(power_domain->dev);
	struct scp_domain_data *data = &scpd->data[power_domain->id];
	void __iomem *ctl_addr = scpd->base + data->ctl_offs;
	u32 pdn_ack = data->sram_pdn_ack_bits;
	u32 val;
	int ret, tmp;

	writel(SPM_EN, scpd->base);

	val = readl(ctl_addr);
	val |= PWR_ON_BIT;
	writel(val, ctl_addr);

	val |= PWR_ON_2ND_BIT;
	writel(val, ctl_addr);

	ret = readx_poll_timeout(scpsys_domain_is_on, data, tmp, tmp > 0,
				 100);
	if (ret < 0)
		return ret;

	val &= ~PWR_CLK_DIS_BIT;
	writel(val, ctl_addr);

	val &= ~PWR_ISO_BIT;
	writel(val, ctl_addr);

	val |= PWR_RST_B_BIT;
	writel(val, ctl_addr);

	val &= ~data->sram_pdn_bits;
	writel(val, ctl_addr);

	ret = readl_poll_timeout(ctl_addr, tmp, !(tmp & pdn_ack), 100);
	if (ret < 0)
		return ret;

	if (data->bus_prot_mask) {
		ret = mtk_infracfg_clear_bus_protection(scpd->infracfg,
							data->bus_prot_mask);
		if (ret)
			return ret;
	}

	return 0;
}

static int scpsys_power_off(struct power_domain *power_domain)
{
	struct scp_domain *scpd = dev_get_priv(power_domain->dev);
	struct scp_domain_data *data = &scpd->data[power_domain->id];
	void __iomem *ctl_addr = scpd->base + data->ctl_offs;
	u32 pdn_ack = data->sram_pdn_ack_bits;
	u32 val;
	int ret, tmp;

	if (data->bus_prot_mask) {
		ret = mtk_infracfg_set_bus_protection(scpd->infracfg,
						      data->bus_prot_mask);
		if (ret)
			return ret;
	}

	val = readl(ctl_addr);
	val |= data->sram_pdn_bits;
	writel(val, ctl_addr);

	ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == pdn_ack,
				 100);
	if (ret < 0)
		return ret;

	val |= PWR_ISO_BIT;
	writel(val, ctl_addr);

	val &= ~PWR_RST_B_BIT;
	writel(val, ctl_addr);

	val |= PWR_CLK_DIS_BIT;
	writel(val, ctl_addr);

	val &= ~PWR_ON_BIT;
	writel(val, ctl_addr);

	val &= ~PWR_ON_2ND_BIT;
	writel(val, ctl_addr);

	ret = readx_poll_timeout(scpsys_domain_is_on, data, tmp, !tmp, 100);
	if (ret < 0)
		return ret;

	return 0;
}

static int scpsys_power_request(struct power_domain *power_domain)
{
	struct scp_domain *scpd = dev_get_priv(power_domain->dev);
	struct scp_domain_data *data;

	data = &scpd->data[power_domain->id];
	data->scpd = scpd;

	return 0;
}

static int mtk_power_domain_hook(struct udevice *dev)
{
	struct scp_domain *scpd = dev_get_priv(dev);

	scpd->type = (enum scp_domain_type)dev_get_driver_data(dev);

	switch (scpd->type) {
	case SCPSYS_MT7623:
		scpd->data = scp_domain_mt7623;
		break;
	case SCPSYS_MT7622:
	case SCPSYS_MT7629:
		scpd->data = scp_domain_mt7629;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static int mtk_power_domain_probe(struct udevice *dev)
{
	struct ofnode_phandle_args args;
	struct scp_domain *scpd = dev_get_priv(dev);
	struct regmap *regmap;
	struct clk_bulk bulk;
	int err;

	scpd->base = dev_read_addr_ptr(dev);
	if (!scpd->base)
		return -ENOENT;

	err = mtk_power_domain_hook(dev);
	if (err)
		return err;

	/* get corresponding syscon phandle */
	err = dev_read_phandle_with_args(dev, "infracfg", NULL, 0, 0, &args);
	if (err)
		return err;

	regmap = syscon_node_to_regmap(args.node);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	scpd->infracfg = regmap_get_range(regmap, 0);
	if (!scpd->infracfg)
		return -ENOENT;

	/* enable Infra DCM */
	setbits_le32(scpd->infracfg + INFRA_TOPDCM_CTRL, DCM_TOP_EN);

	err = clk_get_bulk(dev, &bulk);
	if (err)
		return err;

	return clk_enable_bulk(&bulk);
}

static const struct udevice_id mtk_power_domain_ids[] = {
	{
		.compatible = "mediatek,mt7622-scpsys",
		.data = SCPSYS_MT7622,
	},
	{
		.compatible = "mediatek,mt7623-scpsys",
		.data = SCPSYS_MT7623,
	},
	{
		.compatible = "mediatek,mt7629-scpsys",
		.data = SCPSYS_MT7629,
	},
	{ /* sentinel */ }
};

struct power_domain_ops mtk_power_domain_ops = {
	.off = scpsys_power_off,
	.on = scpsys_power_on,
	.request = scpsys_power_request,
};

U_BOOT_DRIVER(mtk_power_domain) = {
	.name = "mtk_power_domain",
	.id = UCLASS_POWER_DOMAIN,
	.ops = &mtk_power_domain_ops,
	.probe = mtk_power_domain_probe,
	.of_match = mtk_power_domain_ids,
	.priv_auto	= sizeof(struct scp_domain),
};
Commit	Line	Data
2ae7e4dc RL	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) 2018 MediaTek Inc.
	4	* Author: Ryder Lee <ryder.lee@mediatek.com>
	5	*/
	6
	7	#include <clk.h>
d678a59d	8	#include <common.h>
2ae7e4dc	9	#include <dm.h>
336d4615	10	#include <malloc.h>
2ae7e4dc RL	11	#include <power-domain-uclass.h>
	12	#include <regmap.h>
	13	#include <syscon.h>
	14	#include <asm/io.h>
	15	#include <asm/processor.h>
cd93d625	16	#include <linux/bitops.h>
61b29b82	17	#include <linux/err.h>
2ae7e4dc RL	18	#include <linux/iopoll.h>
2ae7e4dc RL	19
9dec738a	20	#include <dt-bindings/power/mt7623-power.h>
2ae7e4dc RL	21	#include <dt-bindings/power/mt7629-power.h>
	22
	23	#define SPM_EN (0xb16 << 16 \| 0x1)
9dec738a RL	24	#define SPM_VDE_PWR_CON 0x0210
	25	#define SPM_MFG_PWR_CON 0x0214
	26	#define SPM_ISP_PWR_CON 0x0238
	27	#define SPM_DIS_PWR_CON 0x023c
	28	#define SPM_CONN_PWR_CON 0x0280
	29	#define SPM_BDP_PWR_CON 0x029c
	30	#define SPM_ETH_PWR_CON 0x02a0
	31	#define SPM_HIF_PWR_CON 0x02a4
	32	#define SPM_IFR_MSC_PWR_CON 0x02a8
2ae7e4dc RL	33	#define SPM_ETHSYS_PWR_CON 0x2e0
	34	#define SPM_HIF0_PWR_CON 0x2e4
	35	#define SPM_HIF1_PWR_CON 0x2e8
	36	#define SPM_PWR_STATUS 0x60c
	37	#define SPM_PWR_STATUS_2ND 0x610
	38
	39	#define PWR_RST_B_BIT BIT(0)
	40	#define PWR_ISO_BIT BIT(1)
	41	#define PWR_ON_BIT BIT(2)
	42	#define PWR_ON_2ND_BIT BIT(3)
	43	#define PWR_CLK_DIS_BIT BIT(4)
	44
9dec738a RL	45	#define PWR_STATUS_CONN BIT(1)
	46	#define PWR_STATUS_DISP BIT(3)
	47	#define PWR_STATUS_MFG BIT(4)
	48	#define PWR_STATUS_ISP BIT(5)
	49	#define PWR_STATUS_VDEC BIT(7)
	50	#define PWR_STATUS_BDP BIT(14)
	51	#define PWR_STATUS_ETH BIT(15)
	52	#define PWR_STATUS_HIF BIT(16)
	53	#define PWR_STATUS_IFR_MSC BIT(17)
2ae7e4dc RL	54	#define PWR_STATUS_ETHSYS BIT(24)
	55	#define PWR_STATUS_HIF0 BIT(25)
	56	#define PWR_STATUS_HIF1 BIT(26)
	57
	58	/* Infrasys configuration */
	59	#define INFRA_TOPDCM_CTRL 0x10
	60	#define INFRA_TOPAXI_PROT_EN 0x220
	61	#define INFRA_TOPAXI_PROT_STA1 0x228
	62
	63	#define DCM_TOP_EN BIT(0)
	64
	65	enum scp_domain_type {
abb65f12	66	SCPSYS_MT7622,
9dec738a	67	SCPSYS_MT7623,
2ae7e4dc RL	68	SCPSYS_MT7629,
	69	};
	70
	71	struct scp_domain;
	72
	73	struct scp_domain_data {
	74	struct scp_domain *scpd;
	75	u32 sta_mask;
	76	int ctl_offs;
	77	u32 sram_pdn_bits;
	78	u32 sram_pdn_ack_bits;
	79	u32 bus_prot_mask;
	80	};
	81
	82	struct scp_domain {
	83	void __iomem *base;
	84	void __iomem *infracfg;
	85	enum scp_domain_type type;
	86	struct scp_domain_data *data;
	87	};
	88
9dec738a RL	89	static struct scp_domain_data scp_domain_mt7623[] = {
	90	[MT7623_POWER_DOMAIN_CONN] = {
	91	.sta_mask = PWR_STATUS_CONN,
	92	.ctl_offs = SPM_CONN_PWR_CON,
	93	.bus_prot_mask = BIT(8) \| BIT(2),
	94	},
	95	[MT7623_POWER_DOMAIN_DISP] = {
	96	.sta_mask = PWR_STATUS_DISP,
	97	.ctl_offs = SPM_DIS_PWR_CON,
	98	.sram_pdn_bits = GENMASK(11, 8),
	99	.bus_prot_mask = BIT(2),
	100	},
	101	[MT7623_POWER_DOMAIN_MFG] = {
	102	.sta_mask = PWR_STATUS_MFG,
	103	.ctl_offs = SPM_MFG_PWR_CON,
	104	.sram_pdn_bits = GENMASK(11, 8),
	105	.sram_pdn_ack_bits = GENMASK(12, 12),
	106	},
	107	[MT7623_POWER_DOMAIN_VDEC] = {
	108	.sta_mask = PWR_STATUS_VDEC,
	109	.ctl_offs = SPM_VDE_PWR_CON,
	110	.sram_pdn_bits = GENMASK(11, 8),
	111	.sram_pdn_ack_bits = GENMASK(12, 12),
	112	},
	113	[MT7623_POWER_DOMAIN_ISP] = {
	114	.sta_mask = PWR_STATUS_ISP,
	115	.ctl_offs = SPM_ISP_PWR_CON,
	116	.sram_pdn_bits = GENMASK(11, 8),
	117	.sram_pdn_ack_bits = GENMASK(13, 12),
	118	},
	119	[MT7623_POWER_DOMAIN_BDP] = {
	120	.sta_mask = PWR_STATUS_BDP,
	121	.ctl_offs = SPM_BDP_PWR_CON,
	122	.sram_pdn_bits = GENMASK(11, 8),
	123	},
	124	[MT7623_POWER_DOMAIN_ETH] = {
	125	.sta_mask = PWR_STATUS_ETH,
	126	.ctl_offs = SPM_ETH_PWR_CON,
	127	.sram_pdn_bits = GENMASK(11, 8),
	128	.sram_pdn_ack_bits = GENMASK(15, 12),
	129	},
	130	[MT7623_POWER_DOMAIN_HIF] = {
	131	.sta_mask = PWR_STATUS_HIF,
	132	.ctl_offs = SPM_HIF_PWR_CON,
	133	.sram_pdn_bits = GENMASK(11, 8),
	134	.sram_pdn_ack_bits = GENMASK(15, 12),
	135	},
	136	[MT7623_POWER_DOMAIN_IFR_MSC] = {
	137	.sta_mask = PWR_STATUS_IFR_MSC,
	138	.ctl_offs = SPM_IFR_MSC_PWR_CON,
	139	},
	140	};
	141
2ae7e4dc RL	142	static struct scp_domain_data scp_domain_mt7629[] = {
	143	[MT7629_POWER_DOMAIN_ETHSYS] = {
	144	.sta_mask = PWR_STATUS_ETHSYS,
	145	.ctl_offs = SPM_ETHSYS_PWR_CON,
	146	.sram_pdn_bits = GENMASK(11, 8),
	147	.sram_pdn_ack_bits = GENMASK(15, 12),
	148	.bus_prot_mask = (BIT(3) \| BIT(17)),
	149	},
	150	[MT7629_POWER_DOMAIN_HIF0] = {
	151	.sta_mask = PWR_STATUS_HIF0,
	152	.ctl_offs = SPM_HIF0_PWR_CON,
	153	.sram_pdn_bits = GENMASK(11, 8),
	154	.sram_pdn_ack_bits = GENMASK(15, 12),
	155	.bus_prot_mask = GENMASK(25, 24),
	156	},
	157	[MT7629_POWER_DOMAIN_HIF1] = {
	158	.sta_mask = PWR_STATUS_HIF1,
	159	.ctl_offs = SPM_HIF1_PWR_CON,
	160	.sram_pdn_bits = GENMASK(11, 8),
	161	.sram_pdn_ack_bits = GENMASK(15, 12),
	162	.bus_prot_mask = GENMASK(28, 26),
	163	},
	164	};
	165
	166	/**
	167	* This function enables the bus protection bits for disabled power
	168	* domains so that the system does not hang when some unit accesses the
	169	* bus while in power down.
	170	*/
	171	static int mtk_infracfg_set_bus_protection(void __iomem *infracfg,
	172	u32 mask)
	173	{
	174	u32 val;
	175
	176	clrsetbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask, mask);
	177
	178	return readl_poll_timeout(infracfg + INFRA_TOPAXI_PROT_STA1, val,
	179	(val & mask) == mask, 100);
	180	}
	181
	182	static int mtk_infracfg_clear_bus_protection(void __iomem *infracfg,
	183	u32 mask)
	184	{
	185	u32 val;
	186
	187	clrbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask);
	188
	189	return readl_poll_timeout(infracfg + INFRA_TOPAXI_PROT_STA1, val,
	190	!(val & mask), 100);
	191	}
	192
	193	static int scpsys_domain_is_on(struct scp_domain_data *data)
	194	{
	195	struct scp_domain *scpd = data->scpd;
	196	u32 sta = readl(scpd->base + SPM_PWR_STATUS) &
	197	data->sta_mask;
	198	u32 sta2 = readl(scpd->base + SPM_PWR_STATUS_2ND) &
	199	data->sta_mask;
	200
	201	/*
	202	* A domain is on when both status bits are set. If only one is set
	203	* return an error. This happens while powering up a domain
	204	*/
	205	if (sta && sta2)
206	return true;
207	if (!sta && !sta2)
208	return false;
209
210	return -EINVAL;
211	}
212
213	static int scpsys_power_on(struct power_domain *power_domain)
214	{
215	struct scp_domain *scpd = dev_get_priv(power_domain->dev);
216	struct scp_domain_data *data = &scpd->data[power_domain->id];
217	void __iomem *ctl_addr = scpd->base + data->ctl_offs;
218	u32 pdn_ack = data->sram_pdn_ack_bits;
219	u32 val;
220	int ret, tmp;
221
222	writel(SPM_EN, scpd->base);
223
224	val = readl(ctl_addr);
225	val \|= PWR_ON_BIT;
226	writel(val, ctl_addr);
227
228	val \|= PWR_ON_2ND_BIT;
229	writel(val, ctl_addr);
230
231	ret = readx_poll_timeout(scpsys_domain_is_on, data, tmp, tmp > 0,
232	100);
233	if (ret < 0)
234	return ret;
235
236	val &= ~PWR_CLK_DIS_BIT;
237	writel(val, ctl_addr);
238
239	val &= ~PWR_ISO_BIT;
240	writel(val, ctl_addr);
241
242	val \|= PWR_RST_B_BIT;
243	writel(val, ctl_addr);
244
245	val &= ~data->sram_pdn_bits;
246	writel(val, ctl_addr);
247
248	ret = readl_poll_timeout(ctl_addr, tmp, !(tmp & pdn_ack), 100);
249	if (ret < 0)
250	return ret;
251
252	if (data->bus_prot_mask) {
253	ret = mtk_infracfg_clear_bus_protection(scpd->infracfg,
254	data->bus_prot_mask);
255	if (ret)
256	return ret;
257	}
258
259	return 0;
260	}
261
262	static int scpsys_power_off(struct power_domain *power_domain)
263	{
264	struct scp_domain *scpd = dev_get_priv(power_domain->dev);
265	struct scp_domain_data *data = &scpd->data[power_domain->id];
266	void __iomem *ctl_addr = scpd->base + data->ctl_offs;
267	u32 pdn_ack = data->sram_pdn_ack_bits;
268	u32 val;
269	int ret, tmp;
270
271	if (data->bus_prot_mask) {
272	ret = mtk_infracfg_set_bus_protection(scpd->infracfg,
273	data->bus_prot_mask);
274	if (ret)
275	return ret;
276	}
277
278	val = readl(ctl_addr);
279	val \|= data->sram_pdn_bits;
280	writel(val, ctl_addr);
281
282	ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == pdn_ack,
283	100);
284	if (ret < 0)
285	return ret;
286
287	val \|= PWR_ISO_BIT;
288	writel(val, ctl_addr);
289
290	val &= ~PWR_RST_B_BIT;
291	writel(val, ctl_addr);
292
293	val \|= PWR_CLK_DIS_BIT;
294	writel(val, ctl_addr);
295
296	val &= ~PWR_ON_BIT;
297	writel(val, ctl_addr);
298
299	val &= ~PWR_ON_2ND_BIT;
300	writel(val, ctl_addr);
301
302	ret = readx_poll_timeout(scpsys_domain_is_on, data, tmp, !tmp, 100);
303	if (ret < 0)
304	return ret;
305
306	return 0;
307	}
308
309	static int scpsys_power_request(struct power_domain *power_domain)
310	{
311	struct scp_domain *scpd = dev_get_priv(power_domain->dev);
312	struct scp_domain_data *data;
313
314	data = &scpd->data[power_domain->id];
315	data->scpd = scpd;
316
317	return 0;
318	}
319
2ae7e4dc RL	320	static int mtk_power_domain_hook(struct udevice *dev)
	321	{
	322	struct scp_domain *scpd = dev_get_priv(dev);
	323
	324	scpd->type = (enum scp_domain_type)dev_get_driver_data(dev);
	325
	326	switch (scpd->type) {
9dec738a RL	327	case SCPSYS_MT7623:
	328	scpd->data = scp_domain_mt7623;
	329	break;
abb65f12	330	case SCPSYS_MT7622:
2ae7e4dc RL	331	case SCPSYS_MT7629:
	332	scpd->data = scp_domain_mt7629;
	333	break;
	334	default:
	335	return -EINVAL;
	336	}
	337
	338	return 0;
	339	}
	340
	341	static int mtk_power_domain_probe(struct udevice *dev)
	342	{
	343	struct ofnode_phandle_args args;
	344	struct scp_domain *scpd = dev_get_priv(dev);
	345	struct regmap *regmap;
	346	struct clk_bulk bulk;
	347	int err;
	348
	349	scpd->base = dev_read_addr_ptr(dev);
	350	if (!scpd->base)
	351	return -ENOENT;
	352
	353	err = mtk_power_domain_hook(dev);
	354	if (err)
	355	return err;
	356
	357	/* get corresponding syscon phandle */
	358	err = dev_read_phandle_with_args(dev, "infracfg", NULL, 0, 0, &args);
	359	if (err)
	360	return err;
	361
	362	regmap = syscon_node_to_regmap(args.node);
	363	if (IS_ERR(regmap))
	364	return PTR_ERR(regmap);
	365
	366	scpd->infracfg = regmap_get_range(regmap, 0);
	367	if (!scpd->infracfg)
	368	return -ENOENT;
	369
	370	/* enable Infra DCM */
	371	setbits_le32(scpd->infracfg + INFRA_TOPDCM_CTRL, DCM_TOP_EN);
	372
	373	err = clk_get_bulk(dev, &bulk);
	374	if (err)
	375	return err;
	376
	377	return clk_enable_bulk(&bulk);
	378	}
	379
	380	static const struct udevice_id mtk_power_domain_ids[] = {
abb65f12 SS	381	{
	382	.compatible = "mediatek,mt7622-scpsys",
	383	.data = SCPSYS_MT7622,
	384	},
9dec738a RL	385	{
	386	.compatible = "mediatek,mt7623-scpsys",
	387	.data = SCPSYS_MT7623,
	388	},
2ae7e4dc RL	389	{
	390	.compatible = "mediatek,mt7629-scpsys",
	391	.data = SCPSYS_MT7629,
	392	},
	393	{ /* sentinel */ }
	394	};
	395
	396	struct power_domain_ops mtk_power_domain_ops = {
2ae7e4dc RL	397	.off = scpsys_power_off,
	398	.on = scpsys_power_on,
	399	.request = scpsys_power_request,
	400	};
	401
	402	U_BOOT_DRIVER(mtk_power_domain) = {
	403	.name = "mtk_power_domain",
	404	.id = UCLASS_POWER_DOMAIN,
	405	.ops = &mtk_power_domain_ops,
	406	.probe = mtk_power_domain_probe,
	407	.of_match = mtk_power_domain_ids,
41575d8e	408	.priv_auto = sizeof(struct scp_domain),
2ae7e4dc	409	};