[thirdparty/u-boot.git] / drivers / pwm / pwm-aspeed.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2022 Aspeed Technology Inc.
 *
 * PWM controller driver for Aspeed ast2600 SoCs.
 * This drivers doesn't support earlier version of the IP.
 *
 * The formula of pwm period duration:
 * period duration = ((DIV_L + 1) * (PERIOD + 1) << DIV_H) / input-clk
 *
 * The formula of pwm duty cycle duration:
 * duty cycle duration = period duration * DUTY_CYCLE_FALLING_POINT / (PERIOD + 1)
 * = ((DIV_L + 1) * DUTY_CYCLE_FALLING_POINT << DIV_H) / input-clk
 *
 * The software driver fixes the period to 255, which causes the high-frequency
 * precision of the PWM to be coarse, in exchange for the fineness of the duty cycle.
 *
 * Register usage:
 * PIN_ENABLE: When it is unset the pwm controller will always output low to the extern.
 * Use to determine whether the PWM channel is enabled or disabled
 * CLK_ENABLE: When it is unset the pwm controller will reset the duty counter to 0 and
 * output low to the PIN_ENABLE mux after that the driver can still change the pwm period
 * and duty and the value will apply when CLK_ENABLE be set again.
 * Use to determine whether duty_cycle bigger than 0.
 * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately.
 * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two
 * values are equal it means the duty cycle = 100%.
 *
 * Limitations:
 * - When changing both duty cycle and period, we cannot prevent in
 *   software that the output might produce a period with mixed
 *   settings.
 * - Disabling the PWM doesn't complete the current period.
 *
 * Improvements:
 * - When only changing one of duty cycle or period, our pwm controller will not
 *   generate the glitch, the configure will change at next cycle of pwm.
 *   This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE.
 */

#include <common.h>
#include <div64.h>
#include <dm.h>
#include <pwm.h>
#include <clk.h>
#include <reset.h>
#include <regmap.h>
#include <syscon.h>
#include <dm/device_compat.h>
#include <linux/math64.h>
#include <linux/bitfield.h>
#include <linux/time.h>
#include <asm/io.h>

/* The channel number of Aspeed pwm controller */
#define PWM_ASPEED_NR_PWMS 16

/* PWM Control Register */
#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00)
#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19)
#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18)
#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17)
#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16)
#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15)
#define PWM_ASPEED_CTRL_INVERSE BIT(14)
#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13)
#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12)
#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8)
#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0)

/* PWM Duty Cycle Register */
#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04)
#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24)
#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16)
#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8)
#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0)

/* PWM fixed value */
#define PWM_ASPEED_FIXED_PERIOD 0xff

struct aspeed_pwm_priv {
	struct clk clk;
	struct regmap *regmap;
	struct reset_ctl reset;
};

static int aspeed_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
{
	struct aspeed_pwm_priv *priv = dev_get_priv(dev);

	if (channel >= PWM_ASPEED_NR_PWMS)
		return -EINVAL;

	regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
			   PWM_ASPEED_CTRL_INVERSE,
			   FIELD_PREP(PWM_ASPEED_CTRL_INVERSE,
				      polarity));
	return 0;
}

static int aspeed_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
{
	struct aspeed_pwm_priv *priv = dev_get_priv(dev);

	if (channel >= PWM_ASPEED_NR_PWMS)
		return -EINVAL;

	regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
			   PWM_ASPEED_CTRL_PIN_ENABLE,
			   enable ? PWM_ASPEED_CTRL_PIN_ENABLE : 0);
	return 0;
}

static int aspeed_pwm_set_config(struct udevice *dev, uint channel,
				 uint period_ns, uint duty_ns)
{
	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
	u32 duty_pt;
	unsigned long rate;
	u64 div_h, div_l, divisor;
	bool clk_en;

	if (channel >= PWM_ASPEED_NR_PWMS)
		return -EINVAL;
	dev_dbg(dev, "expect period: %dns, duty_cycle: %dns\n", period_ns,
		duty_ns);

	rate = clk_get_rate(&priv->clk);
	/*
	 * Pick the smallest value for div_h so that div_l can be the biggest
	 * which results in a finer resolution near the target period value.
	 */
	divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) *
		  (PWM_ASPEED_CTRL_CLK_DIV_L + 1);
	div_h = order_base_2(div64_u64((u64)rate * period_ns + divisor - 1, divisor));
	if (div_h > 0xf)
		div_h = 0xf;

	divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h;
	div_l = div64_u64((u64)rate * period_ns, divisor);

	if (div_l == 0)
		return -ERANGE;

	div_l -= 1;

	if (div_l > 255)
		div_l = 255;

	dev_dbg(dev, "clk source: %ld div_h %lld, div_l : %lld\n", rate, div_h,
		div_l);
	/* duty_pt = duty_cycle * (PERIOD + 1) / period */
	duty_pt = div64_u64(duty_ns * (u64)rate,
			    (u64)NSEC_PER_SEC * (div_l + 1) << div_h);
	dev_dbg(dev, "duty_cycle = %d, duty_pt = %d\n", duty_ns,
		duty_pt);

	if (duty_pt == 0) {
		clk_en = 0;
	} else {
		clk_en = 1;
		if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1))
			duty_pt = 0;
		/*
		 * Fixed DUTY_CYCLE_PERIOD to its max value to get a
		 * fine-grained resolution for duty_cycle at the expense of a
		 * coarser period resolution.
		 */
		regmap_update_bits(priv->regmap, PWM_ASPEED_DUTY_CYCLE(channel),
				   PWM_ASPEED_DUTY_CYCLE_PERIOD |
				       PWM_ASPEED_DUTY_CYCLE_RISING_POINT |
				       PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
				   FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD,
					      PWM_ASPEED_FIXED_PERIOD) |
				       FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
						  duty_pt));
	}

	regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
			   PWM_ASPEED_CTRL_CLK_DIV_H |
			       PWM_ASPEED_CTRL_CLK_DIV_L |
			       PWM_ASPEED_CTRL_CLK_ENABLE,
			   FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) |
			       FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) |
			       FIELD_PREP(PWM_ASPEED_CTRL_CLK_ENABLE, clk_en));
	return 0;
}

static int aspeed_pwm_probe(struct udevice *dev)
{
	int ret;
	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
	struct udevice *parent_dev = dev_get_parent(dev);

	priv->regmap = syscon_node_to_regmap(dev_ofnode(dev->parent));
	if (IS_ERR(priv->regmap)) {
		dev_err(dev, "Couldn't get regmap\n");
		return PTR_ERR(priv->regmap);
	}

	ret = clk_get_by_index(parent_dev, 0, &priv->clk);
	if (ret < 0) {
		dev_err(dev, "get clock failed\n");
		return ret;
	}

	ret = reset_get_by_index(parent_dev, 0, &priv->reset);
	if (ret) {
		dev_err(dev, "get reset failed\n");
		return ret;
	}
	ret = reset_deassert(&priv->reset);
	if (ret) {
		dev_err(dev, "cannot deassert reset control: %pe\n",
			ERR_PTR(ret));
		return ret;
	}

	return 0;
}

static int aspeed_pwm_remove(struct udevice *dev)
{
	struct aspeed_pwm_priv *priv = dev_get_priv(dev);

	reset_assert(&priv->reset);

	return 0;
}

static const struct pwm_ops aspeed_pwm_ops = {
	.set_invert	= aspeed_pwm_set_invert,
	.set_config	= aspeed_pwm_set_config,
	.set_enable	= aspeed_pwm_set_enable,
};

static const struct udevice_id aspeed_pwm_ids[] = {
	{ .compatible = "aspeed,ast2600-pwm" },
	{ }
};

U_BOOT_DRIVER(aspeed_pwm) = {
	.name = "aspeed_pwm",
	.id = UCLASS_PWM,
	.of_match = aspeed_pwm_ids,
	.ops = &aspeed_pwm_ops,
	.probe = aspeed_pwm_probe,
	.remove = aspeed_pwm_remove,
	.priv_auto = sizeof(struct aspeed_pwm_priv),
};
Commit	Line	Data
fae101d6 BT	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2022 Aspeed Technology Inc.
	4	*
	5	* PWM controller driver for Aspeed ast2600 SoCs.
	6	* This drivers doesn't support earlier version of the IP.
	7	*
	8	* The formula of pwm period duration:
	9	* period duration = ((DIV_L + 1) * (PERIOD + 1) << DIV_H) / input-clk
	10	*
	11	* The formula of pwm duty cycle duration:
	12	* duty cycle duration = period duration * DUTY_CYCLE_FALLING_POINT / (PERIOD + 1)
	13	* = ((DIV_L + 1) * DUTY_CYCLE_FALLING_POINT << DIV_H) / input-clk
	14	*
	15	* The software driver fixes the period to 255, which causes the high-frequency
	16	* precision of the PWM to be coarse, in exchange for the fineness of the duty cycle.
	17	*
	18	* Register usage:
	19	* PIN_ENABLE: When it is unset the pwm controller will always output low to the extern.
	20	* Use to determine whether the PWM channel is enabled or disabled
	21	* CLK_ENABLE: When it is unset the pwm controller will reset the duty counter to 0 and
	22	* output low to the PIN_ENABLE mux after that the driver can still change the pwm period
	23	* and duty and the value will apply when CLK_ENABLE be set again.
	24	* Use to determine whether duty_cycle bigger than 0.
	25	* PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately.
	26	* PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two
	27	* values are equal it means the duty cycle = 100%.
	28	*
	29	* Limitations:
	30	* - When changing both duty cycle and period, we cannot prevent in
	31	* software that the output might produce a period with mixed
	32	* settings.
	33	* - Disabling the PWM doesn't complete the current period.
	34	*
	35	* Improvements:
	36	* - When only changing one of duty cycle or period, our pwm controller will not
	37	* generate the glitch, the configure will change at next cycle of pwm.
	38	* This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE.
	39	*/
	40
d678a59d	41	#include <common.h>
fae101d6 BT	42	#include <div64.h>
	43	#include <dm.h>
	44	#include <pwm.h>
	45	#include <clk.h>
	46	#include <reset.h>
	47	#include <regmap.h>
	48	#include <syscon.h>
	49	#include <dm/device_compat.h>
	50	#include <linux/math64.h>
	51	#include <linux/bitfield.h>
13248d66	52	#include <linux/time.h>
fae101d6 BT	53	#include <asm/io.h>
	54
	55	/* The channel number of Aspeed pwm controller */
	56	#define PWM_ASPEED_NR_PWMS 16
	57
	58	/* PWM Control Register */
	59	#define PWM_ASPEED_CTRL(ch) ((ch) * 0x10 + 0x00)
	60	#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19)
	61	#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18)
	62	#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17)
	63	#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16)
	64	#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15)
	65	#define PWM_ASPEED_CTRL_INVERSE BIT(14)
	66	#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13)
	67	#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12)
	68	#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8)
	69	#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0)
	70
	71	/* PWM Duty Cycle Register */
	72	#define PWM_ASPEED_DUTY_CYCLE(ch) ((ch) * 0x10 + 0x04)
	73	#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24)
	74	#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16)
	75	#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8)
	76	#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0)
	77
	78	/* PWM fixed value */
	79	#define PWM_ASPEED_FIXED_PERIOD 0xff
	80
fae101d6 BT	81	struct aspeed_pwm_priv {
	82	struct clk clk;
	83	struct regmap *regmap;
	84	struct reset_ctl reset;
	85	};
	86
	87	static int aspeed_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
	88	{
	89	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
	90
	91	if (channel >= PWM_ASPEED_NR_PWMS)
	92	return -EINVAL;
	93
	94	regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
	95	PWM_ASPEED_CTRL_INVERSE,
	96	FIELD_PREP(PWM_ASPEED_CTRL_INVERSE,
	97	polarity));
	98	return 0;
	99	}
	100
	101	static int aspeed_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
	102	{
	103	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
	104
	105	if (channel >= PWM_ASPEED_NR_PWMS)
	106	return -EINVAL;
	107
	108	regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
	109	PWM_ASPEED_CTRL_PIN_ENABLE,
	110	enable ? PWM_ASPEED_CTRL_PIN_ENABLE : 0);
	111	return 0;
	112	}
	113
	114	static int aspeed_pwm_set_config(struct udevice *dev, uint channel,
	115	uint period_ns, uint duty_ns)
	116	{
	117	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
	118	u32 duty_pt;
	119	unsigned long rate;
	120	u64 div_h, div_l, divisor;
	121	bool clk_en;
	122
	123	if (channel >= PWM_ASPEED_NR_PWMS)
	124	return -EINVAL;
	125	dev_dbg(dev, "expect period: %dns, duty_cycle: %dns\n", period_ns,
	126	duty_ns);
	127
	128	rate = clk_get_rate(&priv->clk);
	129	/*
	130	* Pick the smallest value for div_h so that div_l can be the biggest
	131	* which results in a finer resolution near the target period value.
	132	*/
	133	divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) *
	134	(PWM_ASPEED_CTRL_CLK_DIV_L + 1);
	135	div_h = order_base_2(div64_u64((u64)rate * period_ns + divisor - 1, divisor));
	136	if (div_h > 0xf)
	137	div_h = 0xf;
	138
	139	divisor = ((u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1)) << div_h;
	140	div_l = div64_u64((u64)rate * period_ns, divisor);
	141
	142	if (div_l == 0)
	143	return -ERANGE;
	144
145	div_l -= 1;
146
147	if (div_l > 255)
148	div_l = 255;
149
150	dev_dbg(dev, "clk source: %ld div_h %lld, div_l : %lld\n", rate, div_h,
151	div_l);
152	/* duty_pt = duty_cycle * (PERIOD + 1) / period */
153	duty_pt = div64_u64(duty_ns * (u64)rate,
154	(u64)NSEC_PER_SEC * (div_l + 1) << div_h);
155	dev_dbg(dev, "duty_cycle = %d, duty_pt = %d\n", duty_ns,
156	duty_pt);
157
158	if (duty_pt == 0) {
159	clk_en = 0;
160	} else {
161	clk_en = 1;
162	if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1))
163	duty_pt = 0;
164	/*
165	* Fixed DUTY_CYCLE_PERIOD to its max value to get a
166	* fine-grained resolution for duty_cycle at the expense of a
167	* coarser period resolution.
168	*/
169	regmap_update_bits(priv->regmap, PWM_ASPEED_DUTY_CYCLE(channel),
170	PWM_ASPEED_DUTY_CYCLE_PERIOD \|
171	PWM_ASPEED_DUTY_CYCLE_RISING_POINT \|
172	PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
173	FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD,
174	PWM_ASPEED_FIXED_PERIOD) \|
175	FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT,
176	duty_pt));
177	}
178
179	regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL(channel),
180	PWM_ASPEED_CTRL_CLK_DIV_H \|
181	PWM_ASPEED_CTRL_CLK_DIV_L \|
182	PWM_ASPEED_CTRL_CLK_ENABLE,
183	FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) \|
184	FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l) \|
185	FIELD_PREP(PWM_ASPEED_CTRL_CLK_ENABLE, clk_en));
186	return 0;
187	}
188
189	static int aspeed_pwm_probe(struct udevice *dev)
190	{
191	int ret;
192	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
193	struct udevice *parent_dev = dev_get_parent(dev);
194
195	priv->regmap = syscon_node_to_regmap(dev_ofnode(dev->parent));
196	if (IS_ERR(priv->regmap)) {
197	dev_err(dev, "Couldn't get regmap\n");
198	return PTR_ERR(priv->regmap);
199	}
200
201	ret = clk_get_by_index(parent_dev, 0, &priv->clk);
202	if (ret < 0) {
203	dev_err(dev, "get clock failed\n");
204	return ret;
205	}
206
207	ret = reset_get_by_index(parent_dev, 0, &priv->reset);
208	if (ret) {
209	dev_err(dev, "get reset failed\n");
210	return ret;
211	}
212	ret = reset_deassert(&priv->reset);
213	if (ret) {
214	dev_err(dev, "cannot deassert reset control: %pe\n",
215	ERR_PTR(ret));
216	return ret;
217	}
218
219	return 0;
220	}
221
222	static int aspeed_pwm_remove(struct udevice *dev)
223	{
224	struct aspeed_pwm_priv *priv = dev_get_priv(dev);
225
226	reset_assert(&priv->reset);
227
228	return 0;
229	}
230
231	static const struct pwm_ops aspeed_pwm_ops = {
232	.set_invert = aspeed_pwm_set_invert,
233	.set_config = aspeed_pwm_set_config,
234	.set_enable = aspeed_pwm_set_enable,
235	};
236
237	static const struct udevice_id aspeed_pwm_ids[] = {
238	{ .compatible = "aspeed,ast2600-pwm" },
239	{ }
240	};
241
242	U_BOOT_DRIVER(aspeed_pwm) = {
243	.name = "aspeed_pwm",
244	.id = UCLASS_PWM,
245	.of_match = aspeed_pwm_ids,
246	.ops = &aspeed_pwm_ops,
247	.probe = aspeed_pwm_probe,
248	.remove = aspeed_pwm_remove,
249	.priv_auto = sizeof(struct aspeed_pwm_priv),
250	};