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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / drivers / ram / mpc83xx_sdram.c
CommitLineData
e4061556
MS		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2018
4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
5 */
6
d678a59d 7#include <common.h>
e4061556 8#include <dm.h>
9b4a205f 9#include <init.h>
f7ae49fc 10#include <log.h>
e4061556 11#include <ram.h>
cd93d625 12#include <asm/bitops.h>
401d1c4f 13#include <asm/global_data.h>
e4061556
MS		 14#include <dt-bindings/memory/mpc83xx-sdram.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18/* Masks for the CS config register */
19static const u32 CSCONFIG_ENABLE = 0x80000000;
20
21static const u32 BANK_BITS_2;
22static const u32 BANK_BITS_3 = 0x00004000;
23
24static const u32 ROW_BITS_12;
25static const u32 ROW_BITS_13 = 0x00000100;
26static const u32 ROW_BITS_14 = 0x00000200;
27
28static const u32 COL_BITS_8;
29static const u32 COL_BITS_9 = 0x00000001;
30static const u32 COL_BITS_10 = 0x00000002;
31static const u32 COL_BITS_11 = 0x00000003;
32
33/* Shifts for the DDR SDRAM Timing Configuration 3 register */
34static const uint TIMING_CFG3_EXT_REFREC_SHIFT = (31 - 15);
35
36/* Shifts for the DDR SDRAM Timing Configuration 0 register */
37static const uint TIMING_CFG0_RWT_SHIFT = (31 - 1);
38static const uint TIMING_CFG0_WRT_SHIFT = (31 - 3);
39static const uint TIMING_CFG0_RRT_SHIFT = (31 - 5);
40static const uint TIMING_CFG0_WWT_SHIFT = (31 - 7);
41static const uint TIMING_CFG0_ACT_PD_EXIT_SHIFT = (31 - 11);
42static const uint TIMING_CFG0_PRE_PD_EXIT_SHIFT = (31 - 15);
43static const uint TIMING_CFG0_ODT_PD_EXIT_SHIFT = (31 - 23);
44static const uint TIMING_CFG0_MRS_CYC_SHIFT = (31 - 31);
45
46/* Shifts for the DDR SDRAM Timing Configuration 1 register */
47static const uint TIMING_CFG1_PRETOACT_SHIFT = (31 - 3);
48static const uint TIMING_CFG1_ACTTOPRE_SHIFT = (31 - 7);
49static const uint TIMING_CFG1_ACTTORW_SHIFT = (31 - 11);
50static const uint TIMING_CFG1_CASLAT_SHIFT = (31 - 15);
51static const uint TIMING_CFG1_REFREC_SHIFT = (31 - 19);
52static const uint TIMING_CFG1_WRREC_SHIFT = (31 - 23);
53static const uint TIMING_CFG1_ACTTOACT_SHIFT = (31 - 27);
54static const uint TIMING_CFG1_WRTORD_SHIFT = (31 - 31);
55
56/* Shifts for the DDR SDRAM Timing Configuration 2 register */
57static const uint TIMING_CFG2_CPO_SHIFT = (31 - 8);
58static const uint TIMING_CFG2_WR_DATA_DELAY_SHIFT = (31 - 21);
59static const uint TIMING_CFG2_ADD_LAT_SHIFT = (31 - 3);
60static const uint TIMING_CFG2_WR_LAT_DELAY_SHIFT = (31 - 12);
61static const uint TIMING_CFG2_RD_TO_PRE_SHIFT = (31 - 18);
62static const uint TIMING_CFG2_CKE_PLS_SHIFT = (31 - 25);
63static const uint TIMING_CFG2_FOUR_ACT_SHIFT;
64
65/* Shifts for the DDR SDRAM Control Configuration register */
66static const uint SDRAM_CFG_SREN_SHIFT = (31 - 1);
67static const uint SDRAM_CFG_ECC_EN_SHIFT = (31 - 2);
68static const uint SDRAM_CFG_RD_EN_SHIFT = (31 - 3);
69static const uint SDRAM_CFG_SDRAM_TYPE_SHIFT = (31 - 7);
70static const uint SDRAM_CFG_DYN_PWR_SHIFT = (31 - 10);
71static const uint SDRAM_CFG_DBW_SHIFT = (31 - 12);
72static const uint SDRAM_CFG_NCAP_SHIFT = (31 - 14);
73static const uint SDRAM_CFG_2T_EN_SHIFT = (31 - 16);
74static const uint SDRAM_CFG_BA_INTLV_CTL_SHIFT = (31 - 23);
75static const uint SDRAM_CFG_PCHB8_SHIFT = (31 - 27);
76static const uint SDRAM_CFG_HSE_SHIFT = (31 - 28);
77static const uint SDRAM_CFG_BI_SHIFT = (31 - 31);
78
79/* Shifts for the DDR SDRAM Control Configuration 2 register */
80static const uint SDRAM_CFG2_FRC_SR_SHIFT = (31 - 0);
81static const uint SDRAM_CFG2_DLL_RST_DIS = (31 - 2);
82static const uint SDRAM_CFG2_DQS_CFG = (31 - 5);
83static const uint SDRAM_CFG2_ODT_CFG = (31 - 10);
84static const uint SDRAM_CFG2_NUM_PR = (31 - 19);
85
86/* Shifts for the DDR SDRAM Mode register */
87static const uint SDRAM_MODE_ESD_SHIFT = (31 - 15);
88static const uint SDRAM_MODE_SD_SHIFT = (31 - 31);
89
90/* Shifts for the DDR SDRAM Mode 2 register */
91static const uint SDRAM_MODE2_ESD2_SHIFT = (31 - 15);
92static const uint SDRAM_MODE2_ESD3_SHIFT = (31 - 31);
93
94/* Shifts for the DDR SDRAM Interval Configuration register */
95static const uint SDRAM_INTERVAL_REFINT_SHIFT = (31 - 15);
96static const uint SDRAM_INTERVAL_BSTOPRE_SHIFT = (31 - 31);
97
98/* Mask for the DDR SDRAM Mode Control register */
99static const u32 SDRAM_CFG_MEM_EN = 0x80000000;
100
101int dram_init(void)
102{
103 struct udevice *ram_ctrl;
104 int ret;
105
106 /* Current assumption: There is only one RAM controller */
107 ret = uclass_first_device_err(UCLASS_RAM, &ram_ctrl);
108 if (ret) {
109 debug("%s: uclass_first_device_err failed: %d\n",
110 __func__, ret);
111 return ret;
112 }
113
114 /* FIXME(mario.six@gdsys.cc): Set gd->ram_size? */
115
116 return 0;
117}
118
119phys_size_t get_effective_memsize(void)
120{
308520b8 121 return gd->ram_size;
e4061556
MS		 122}
123
124/**
125 * struct mpc83xx_sdram_priv - Private data for MPC83xx RAM controllers
126 * @total_size: The total size of all RAM modules associated with this RAM
127 * controller in bytes
128 */
129struct mpc83xx_sdram_priv {
130 ulong total_size;
131};
132
133/**
134 * mpc83xx_sdram_static_init() - Statically initialize a RAM module.
135 * @node: Device tree node associated with ths module in question
136 * @cs: The chip select to use for this RAM module
137 * @mapaddr: The address where the RAM module should be mapped
138 * @size: The size of the RAM module to be mapped in bytes
139 *
140 * Return: 0 if OK, -ve on error
141 */
142static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
143{
144 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
145 u32 msize = size;
146 u32 msize_log2 = __ilog2(msize);
147 u32 auto_precharge, odt_rd_cfg, odt_wr_cfg, bank_bits, row_bits,
148 col_bits;
149 u32 bank_bits_mask, row_bits_mask, col_bits_mask;
150
151 /* Configure the DDR local access window */
152 out_be32(&im->sysconf.ddrlaw[cs].bar, mapaddr & 0xfffff000);
153 out_be32(&im->sysconf.ddrlaw[cs].ar, LBLAWAR_EN | (msize_log2 - 1));
154
155 out_be32(&im->ddr.csbnds[cs].csbnds, (msize - 1) >> 24);
156
157 auto_precharge = ofnode_read_u32_default(node, "auto_precharge", 0);
158 switch (auto_precharge) {
159 case AUTO_PRECHARGE_ENABLE:
160 case AUTO_PRECHARGE_DISABLE:
161 break;
162 default:
163 debug("%s: auto_precharge value %d invalid.\n",
164 ofnode_get_name(node), auto_precharge);
165 return -EINVAL;
166 }
167
168 odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0);
169 switch (odt_rd_cfg) {
170 case ODT_RD_ONLY_OTHER_DIMM:
61abced7 171 if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
8439e99d 172 !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
e4061556
MS		 173 debug("%s: odt_rd_cfg value %d invalid.\n",
174 ofnode_get_name(node), odt_rd_cfg);
175 return -EINVAL;
176 }
177 /* fall through */
178 case ODT_RD_NEVER:
179 case ODT_RD_ONLY_CURRENT:
180 case ODT_RD_ONLY_OTHER_CS:
4bc97a3b 181 if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
9403fc41 182 !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
61abced7 183 !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
8439e99d 184 !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
e4061556
MS		 185 debug("%s: odt_rd_cfg value %d invalid.\n",
186 ofnode_get_name(node), odt_rd_cfg);
187 return -EINVAL;
188 }
189 /* fall through */
190 /* Only MPC832x knows this value */
191 case ODT_RD_ALL:
192 break;
193 default:
194 debug("%s: odt_rd_cfg value %d invalid.\n",
195 ofnode_get_name(node), odt_rd_cfg);
196 return -EINVAL;
197 }
198
199 odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0);
200 switch (odt_wr_cfg) {
201 case ODT_WR_ONLY_OTHER_DIMM:
61abced7 202 if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
8439e99d 203 !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
e4061556
MS		 204 debug("%s: odt_wr_cfg value %d invalid.\n",
205 ofnode_get_name(node), odt_wr_cfg);
206 return -EINVAL;
207 }
208 /* fall through */
209 case ODT_WR_NEVER:
210 case ODT_WR_ONLY_CURRENT:
211 case ODT_WR_ONLY_OTHER_CS:
4bc97a3b 212 if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
9403fc41 213 !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
61abced7 214 !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
8439e99d 215 !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
e4061556
MS		 216 debug("%s: odt_wr_cfg value %d invalid.\n",
217 ofnode_get_name(node), odt_wr_cfg);
218 return -EINVAL;
219 }
220 /* fall through */
221 /* MPC832x only knows this value */
222 case ODT_WR_ALL:
223 break;
224 default:
225 debug("%s: odt_wr_cfg value %d invalid.\n",
226 ofnode_get_name(node), odt_wr_cfg);
227 return -EINVAL;
228 }
229
230 bank_bits = ofnode_read_u32_default(node, "bank_bits", 0);
231 switch (bank_bits) {
232 case 2:
233 bank_bits_mask = BANK_BITS_2;
234 break;
235 case 3:
236 bank_bits_mask = BANK_BITS_3;
237 break;
238 default:
239 debug("%s: bank_bits value %d invalid.\n",
240 ofnode_get_name(node), bank_bits);
241 return -EINVAL;
242 }
243
244 row_bits = ofnode_read_u32_default(node, "row_bits", 0);
245 switch (row_bits) {
246 case 12:
247 row_bits_mask = ROW_BITS_12;
248 break;
249 case 13:
250 row_bits_mask = ROW_BITS_13;
251 break;
252 case 14:
253 row_bits_mask = ROW_BITS_14;
254 break;
255 default:
256 debug("%s: row_bits value %d invalid.\n",
257 ofnode_get_name(node), row_bits);
258 return -EINVAL;
259 }
260
261 col_bits = ofnode_read_u32_default(node, "col_bits", 0);
262 switch (col_bits) {
263 case 8:
264 col_bits_mask = COL_BITS_8;
265 break;
266 case 9:
267 col_bits_mask = COL_BITS_9;
268 break;
269 case 10:
270 col_bits_mask = COL_BITS_10;
271 break;
272 case 11:
273 col_bits_mask = COL_BITS_11;
274 break;
275 default:
276 debug("%s: col_bits value %d invalid.\n",
277 ofnode_get_name(node), col_bits);
278 return -EINVAL;
279 }
280
281 /* Write CS config value */
282 out_be32(&im->ddr.cs_config[cs], CSCONFIG_ENABLE | auto_precharge |
283 odt_rd_cfg | odt_wr_cfg |
284 bank_bits_mask | row_bits_mask |
285 col_bits_mask);
286 return 0;
287}
288
289/**
290 * mpc83xx_sdram_spd_init() - Initialize a RAM module using a SPD flash.
291 * @node: Device tree node associated with ths module in question
292 * @cs: The chip select to use for this RAM module
293 * @mapaddr: The address where the RAM module should be mapped
294 * @size: The size of the RAM module to be mapped in bytes
295 *
296 * Return: 0 if OK, -ve on error
297 */
298static int mpc83xx_sdram_spd_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
299{
300 /* TODO(mario.six@gdsys.cc): Implement */
301 return 0;
302}
303
d1998a9f 304static int mpc83xx_sdram_of_to_plat(struct udevice *dev)
e4061556
MS		 305{
306 return 0;
307}
308
309static int mpc83xx_sdram_probe(struct udevice *dev)
310{
311 struct mpc83xx_sdram_priv *priv = dev_get_priv(dev);
312 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
313 int ret = 0;
314 ofnode subnode;
315 /* DDR control driver register values */
316 u32 dso, pz_override, nz_override, odt_term, ddr_type, mvref_sel, m_odr;
317 u32 ddrcdr;
318 /* DDR SDRAM Clock Control register values */
319 u32 clock_adjust;
320 /* DDR SDRAM Timing Configuration 3 register values */
321 u32 ext_refresh_rec, ext_refresh_rec_mask;
322 /* DDR SDRAM Timing Configuration 0 register values */
323 u32 read_to_write, write_to_read, read_to_read, write_to_write,
324 active_powerdown_exit, precharge_powerdown_exit,
325 odt_powerdown_exit, mode_reg_set_cycle;
326 u32 timing_cfg_0;
327 /* DDR SDRAM Timing Configuration 1 register values */
328 u32 precharge_to_activate, activate_to_precharge,
329 activate_to_readwrite, mcas_latency, refresh_recovery,
330 last_data_to_precharge, activate_to_activate,
331 last_write_data_to_read;
332 u32 timing_cfg_1;
333 /* DDR SDRAM Timing Configuration 2 register values */
334 u32 additive_latency, mcas_to_preamble_override, write_latency,
335 read_to_precharge, write_cmd_to_write_data,
336 minimum_cke_pulse_width, four_activates_window;
337 u32 timing_cfg_2;
338 /* DDR SDRAM Control Configuration register values */
339 u32 self_refresh, ecc, registered_dram, sdram_type,
340 dynamic_power_management, databus_width, nc_auto_precharge,
341 timing_2t, bank_interleaving_ctrl, precharge_bit_8, half_strength,
342 bypass_initialization;
343 u32 sdram_cfg;
344 /* DDR SDRAM Control Configuration 2 register values */
345 u32 force_self_refresh, dll_reset, dqs_config, odt_config,
346 posted_refreshes;
347 u32 sdram_cfg2;
348 /* DDR SDRAM Mode Configuration register values */
349 u32 sdmode, esdmode;
350 u32 sdram_mode;
351 /* DDR SDRAM Mode Configuration 2 register values */
352 u32 esdmode2, esdmode3;
353 u32 sdram_mode2;
354 /* DDR SDRAM Interval Configuration register values */
355 u32 refresh_interval, precharge_interval;
356 u32 sdram_interval;
357
358 priv->total_size = 0;
359
360 /* Disable both banks initially (might be re-enabled in loop below) */
361 out_be32(&im->ddr.cs_config[0], 0);
362 out_be32(&im->ddr.cs_config[1], 0);
363
364 dso = dev_read_u32_default(dev, "driver_software_override", 0);
365 if (dso > 1) {
366 debug("%s: driver_software_override value %d invalid.\n",
367 dev->name, dso);
368 return -EINVAL;
369 }
370
371 pz_override = dev_read_u32_default(dev, "p_impedance_override", 0);
372
373 switch (pz_override) {
374 case DSO_P_IMPEDANCE_HIGHEST_Z:
375 case DSO_P_IMPEDANCE_MUCH_HIGHER_Z:
376 case DSO_P_IMPEDANCE_HIGHER_Z:
377 case DSO_P_IMPEDANCE_NOMINAL:
378 case DSO_P_IMPEDANCE_LOWER_Z:
379 break;
380 default:
381 debug("%s: p_impedance_override value %d invalid.\n",
382 dev->name, pz_override);
383 return -EINVAL;
384 }
385
386 nz_override = dev_read_u32_default(dev, "n_impedance_override", 0);
387
388 switch (nz_override) {
389 case DSO_N_IMPEDANCE_HIGHEST_Z:
390 case DSO_N_IMPEDANCE_MUCH_HIGHER_Z:
391 case DSO_N_IMPEDANCE_HIGHER_Z:
392 case DSO_N_IMPEDANCE_NOMINAL:
393 case DSO_N_IMPEDANCE_LOWER_Z:
394 break;
395 default:
396 debug("%s: n_impedance_override value %d invalid.\n",
397 dev->name, nz_override);
398 return -EINVAL;
399 }
400
401 odt_term = dev_read_u32_default(dev, "odt_termination_value", 0);
402 if (odt_term > 1) {
403 debug("%s: odt_termination_value value %d invalid.\n",
404 dev->name, odt_term);
405 return -EINVAL;
406 }
407
408 ddr_type = dev_read_u32_default(dev, "ddr_type", 0);
409 if (ddr_type > 1) {
410 debug("%s: ddr_type value %d invalid.\n",
411 dev->name, ddr_type);
412 return -EINVAL;
413 }
414
415 mvref_sel = dev_read_u32_default(dev, "mvref_sel", 0);
416 if (mvref_sel > 1) {
417 debug("%s: mvref_sel value %d invalid.\n",
418 dev->name, mvref_sel);
419 return -EINVAL;
420 }
421
422 m_odr = dev_read_u32_default(dev, "m_odr", 0);
423 if (mvref_sel > 1) {
424 debug("%s: m_odr value %d invalid.\n",
425 dev->name, m_odr);
426 return -EINVAL;
427 }
428
429 ddrcdr = dso << (31 - 1) |
430 pz_override << (31 - 5) |
431 nz_override << (31 - 9) |
432 odt_term << (31 - 12) |
433 ddr_type << (31 - 13) |
434 mvref_sel << (31 - 29) |
435 m_odr << (31 - 30) | 1;
436
437 /* Configure the DDR control driver register */
438 out_be32(&im->sysconf.ddrcdr, ddrcdr);
439
440 dev_for_each_subnode(subnode, dev) {
441 u32 val[3];
442 u32 cs, addr, size;
443
444 /* CS, map address, size -> three values */
445 ofnode_read_u32_array(subnode, "reg", val, 3);
446
447 cs = val[0];
448 addr = val[1];
449 size = val[2];
450
451 if (cs > 1) {
452 debug("%s: chip select value %d invalid.\n",
453 dev->name, cs);
454 return -EINVAL;
455 }
456
457 /* TODO(mario.six@gdsys.cc): Sanity check for size. */
458
459 if (ofnode_read_bool(subnode, "read-spd"))
460 ret = mpc83xx_sdram_spd_init(subnode, cs, addr, size);
461 else
462 ret = mpc83xx_sdram_static_init(subnode, cs, addr,
463 size);
464 if (ret) {
465 debug("%s: RAM init failed.\n", dev->name);
466 return ret;
467 }
468 };
469
470 /*
471 * TODO(mario.six@gdsys.cc): This should only occur for static
472 * configuration
473 */
474
475 clock_adjust = dev_read_u32_default(dev, "clock_adjust", 0);
476 switch (clock_adjust) {
477 case CLOCK_ADJUST_025:
478 case CLOCK_ADJUST_05:
479 case CLOCK_ADJUST_075:
480 case CLOCK_ADJUST_1:
481 break;
482 default:
483 debug("%s: clock_adjust value %d invalid.\n",
484 dev->name, clock_adjust);
485 return -EINVAL;
486 }
487
488 /* Configure the DDR SDRAM Clock Control register */
489 out_be32(&im->ddr.sdram_clk_cntl, clock_adjust);
490
491 ext_refresh_rec = dev_read_u32_default(dev, "ext_refresh_rec", 0);
492 switch (ext_refresh_rec) {
493 case 0:
494 ext_refresh_rec_mask = 0 << TIMING_CFG3_EXT_REFREC_SHIFT;
495 break;
496 case 16:
497 ext_refresh_rec_mask = 1 << TIMING_CFG3_EXT_REFREC_SHIFT;
498 break;
499 case 32:
500 ext_refresh_rec_mask = 2 << TIMING_CFG3_EXT_REFREC_SHIFT;
501 break;
502 case 48:
503 ext_refresh_rec_mask = 3 << TIMING_CFG3_EXT_REFREC_SHIFT;
504 break;
505 case 64:
506 ext_refresh_rec_mask = 4 << TIMING_CFG3_EXT_REFREC_SHIFT;
507 break;
508 case 80:
509 ext_refresh_rec_mask = 5 << TIMING_CFG3_EXT_REFREC_SHIFT;
510 break;
511 case 96:
512 ext_refresh_rec_mask = 6 << TIMING_CFG3_EXT_REFREC_SHIFT;
513 break;
514 case 112:
515 ext_refresh_rec_mask = 7 << TIMING_CFG3_EXT_REFREC_SHIFT;
516 break;
517 default:
518 debug("%s: ext_refresh_rec value %d invalid.\n",
519 dev->name, ext_refresh_rec);
520 return -EINVAL;
521 }
522
523 /* Configure the DDR SDRAM Timing Configuration 3 register */
524 out_be32(&im->ddr.timing_cfg_3, ext_refresh_rec_mask);
525
526 read_to_write = dev_read_u32_default(dev, "read_to_write", 0);
527 if (read_to_write > 3) {
528 debug("%s: read_to_write value %d invalid.\n",
529 dev->name, read_to_write);
530 return -EINVAL;
531 }
532
533 write_to_read = dev_read_u32_default(dev, "write_to_read", 0);
534 if (write_to_read > 3) {
535 debug("%s: write_to_read value %d invalid.\n",
536 dev->name, write_to_read);
537 return -EINVAL;
538 }
539
540 read_to_read = dev_read_u32_default(dev, "read_to_read", 0);
541 if (read_to_read > 3) {
542 debug("%s: read_to_read value %d invalid.\n",
543 dev->name, read_to_read);
544 return -EINVAL;
545 }
546
547 write_to_write = dev_read_u32_default(dev, "write_to_write", 0);
548 if (write_to_write > 3) {
549 debug("%s: write_to_write value %d invalid.\n",
550 dev->name, write_to_write);
551 return -EINVAL;
552 }
553
554 active_powerdown_exit =
555 dev_read_u32_default(dev, "active_powerdown_exit", 0);
556 if (active_powerdown_exit > 7) {
557 debug("%s: active_powerdown_exit value %d invalid.\n",
558 dev->name, active_powerdown_exit);
559 return -EINVAL;
560 }
561
562 precharge_powerdown_exit =
563 dev_read_u32_default(dev, "precharge_powerdown_exit", 0);
564 if (precharge_powerdown_exit > 7) {
565 debug("%s: precharge_powerdown_exit value %d invalid.\n",
566 dev->name, precharge_powerdown_exit);
567 return -EINVAL;
568 }
569
570 odt_powerdown_exit = dev_read_u32_default(dev, "odt_powerdown_exit", 0);
571 if (odt_powerdown_exit > 15) {
572 debug("%s: odt_powerdown_exit value %d invalid.\n",
573 dev->name, odt_powerdown_exit);
574 return -EINVAL;
575 }
576
577 mode_reg_set_cycle = dev_read_u32_default(dev, "mode_reg_set_cycle", 0);
578 if (mode_reg_set_cycle > 15) {
579 debug("%s: mode_reg_set_cycle value %d invalid.\n",
580 dev->name, mode_reg_set_cycle);
581 return -EINVAL;
582 }
583
584 timing_cfg_0 = read_to_write << TIMING_CFG0_RWT_SHIFT |
585 write_to_read << TIMING_CFG0_WRT_SHIFT |
586 read_to_read << TIMING_CFG0_RRT_SHIFT |
587 write_to_write << TIMING_CFG0_WWT_SHIFT |
588 active_powerdown_exit << TIMING_CFG0_ACT_PD_EXIT_SHIFT |
589 precharge_powerdown_exit << TIMING_CFG0_PRE_PD_EXIT_SHIFT |
590 odt_powerdown_exit << TIMING_CFG0_ODT_PD_EXIT_SHIFT |
591 mode_reg_set_cycle << TIMING_CFG0_MRS_CYC_SHIFT;
592
593 out_be32(&im->ddr.timing_cfg_0, timing_cfg_0);
594
595 precharge_to_activate =
596 dev_read_u32_default(dev, "precharge_to_activate", 0);
597 if (precharge_to_activate > 7 || precharge_to_activate == 0) {
598 debug("%s: precharge_to_activate value %d invalid.\n",
599 dev->name, precharge_to_activate);
600 return -EINVAL;
601 }
602
603 activate_to_precharge =
604 dev_read_u32_default(dev, "activate_to_precharge", 0);
605 if (activate_to_precharge > 19) {
606 debug("%s: activate_to_precharge value %d invalid.\n",
607 dev->name, activate_to_precharge);
608 return -EINVAL;
609 }
610
611 activate_to_readwrite =
612 dev_read_u32_default(dev, "activate_to_readwrite", 0);
613 if (activate_to_readwrite > 7 || activate_to_readwrite == 0) {
614 debug("%s: activate_to_readwrite value %d invalid.\n",
615 dev->name, activate_to_readwrite);
616 return -EINVAL;
617 }
618
619 mcas_latency = dev_read_u32_default(dev, "mcas_latency", 0);
620 switch (mcas_latency) {
621 case CASLAT_20:
622 case CASLAT_25:
623 if (!IS_ENABLED(CONFIG_ARCH_MPC8308)) {
624 debug("%s: MCAS latency < 3.0 unsupported on MPC8308\n",
625 dev->name);
626 return -EINVAL;
627 }
628 /* fall through */
629 case CASLAT_30:
630 case CASLAT_35:
631 case CASLAT_40:
632 case CASLAT_45:
633 case CASLAT_50:
634 case CASLAT_55:
635 case CASLAT_60:
636 case CASLAT_65:
637 case CASLAT_70:
638 case CASLAT_75:
639 case CASLAT_80:
640 break;
641 default:
642 debug("%s: mcas_latency value %d invalid.\n",
643 dev->name, mcas_latency);
644 return -EINVAL;
645 }
646
647 refresh_recovery = dev_read_u32_default(dev, "refresh_recovery", 0);
648 if (refresh_recovery > 23 || refresh_recovery < 8) {
649 debug("%s: refresh_recovery value %d invalid.\n",
650 dev->name, refresh_recovery);
651 return -EINVAL;
652 }
653
654 last_data_to_precharge =
655 dev_read_u32_default(dev, "last_data_to_precharge", 0);
656 if (last_data_to_precharge > 7 || last_data_to_precharge == 0) {
657 debug("%s: last_data_to_precharge value %d invalid.\n",
658 dev->name, last_data_to_precharge);
659 return -EINVAL;
660 }
661
662 activate_to_activate =
663 dev_read_u32_default(dev, "activate_to_activate", 0);
664 if (activate_to_activate > 7 || activate_to_activate == 0) {
665 debug("%s: activate_to_activate value %d invalid.\n",
666 dev->name, activate_to_activate);
667 return -EINVAL;
668 }
669
670 last_write_data_to_read =
671 dev_read_u32_default(dev, "last_write_data_to_read", 0);
672 if (last_write_data_to_read > 7 || last_write_data_to_read == 0) {
673 debug("%s: last_write_data_to_read value %d invalid.\n",
674 dev->name, last_write_data_to_read);
675 return -EINVAL;
676 }
677
678 timing_cfg_1 = precharge_to_activate << TIMING_CFG1_PRETOACT_SHIFT |
679 (activate_to_precharge > 15 ?
680 activate_to_precharge - 16 :
681 activate_to_precharge) << TIMING_CFG1_ACTTOPRE_SHIFT |
682 activate_to_readwrite << TIMING_CFG1_ACTTORW_SHIFT |
683 mcas_latency << TIMING_CFG1_CASLAT_SHIFT |
684 (refresh_recovery - 8) << TIMING_CFG1_REFREC_SHIFT |
685 last_data_to_precharge << TIMING_CFG1_WRREC_SHIFT |
686 activate_to_activate << TIMING_CFG1_ACTTOACT_SHIFT |
687 last_write_data_to_read << TIMING_CFG1_WRTORD_SHIFT;
688
689 /* Configure the DDR SDRAM Timing Configuration 1 register */
690 out_be32(&im->ddr.timing_cfg_1, timing_cfg_1);
691
692 additive_latency = dev_read_u32_default(dev, "additive_latency", 0);
693 if (additive_latency > 5) {
694 debug("%s: additive_latency value %d invalid.\n",
695 dev->name, additive_latency);
696 return -EINVAL;
697 }
698
699 mcas_to_preamble_override =
700 dev_read_u32_default(dev, "mcas_to_preamble_override", 0);
701 switch (mcas_to_preamble_override) {
702 case READ_LAT_PLUS_1:
703 case READ_LAT:
704 case READ_LAT_PLUS_1_4:
705 case READ_LAT_PLUS_1_2:
706 case READ_LAT_PLUS_3_4:
707 case READ_LAT_PLUS_5_4:
708 case READ_LAT_PLUS_3_2:
709 case READ_LAT_PLUS_7_4:
710 case READ_LAT_PLUS_2:
711 case READ_LAT_PLUS_9_4:
712 case READ_LAT_PLUS_5_2:
713 case READ_LAT_PLUS_11_4:
714 case READ_LAT_PLUS_3:
715 case READ_LAT_PLUS_13_4:
716 case READ_LAT_PLUS_7_2:
717 case READ_LAT_PLUS_15_4:
718 case READ_LAT_PLUS_4:
719 case READ_LAT_PLUS_17_4:
720 case READ_LAT_PLUS_9_2:
721 case READ_LAT_PLUS_19_4:
722 break;
723 default:
724 debug("%s: mcas_to_preamble_override value %d invalid.\n",
725 dev->name, mcas_to_preamble_override);
726 return -EINVAL;
727 }
728
729 write_latency = dev_read_u32_default(dev, "write_latency", 0);
730 if (write_latency > 7 || write_latency == 0) {
731 debug("%s: write_latency value %d invalid.\n",
732 dev->name, write_latency);
733 return -EINVAL;
734 }
735
736 read_to_precharge = dev_read_u32_default(dev, "read_to_precharge", 0);
737 if (read_to_precharge > 4 || read_to_precharge == 0) {
738 debug("%s: read_to_precharge value %d invalid.\n",
739 dev->name, read_to_precharge);
740 return -EINVAL;
741 }
742
743 write_cmd_to_write_data =
744 dev_read_u32_default(dev, "write_cmd_to_write_data", 0);
745 switch (write_cmd_to_write_data) {
746 case CLOCK_DELAY_0:
747 case CLOCK_DELAY_1_4:
748 case CLOCK_DELAY_1_2:
749 case CLOCK_DELAY_3_4:
750 case CLOCK_DELAY_1:
751 case CLOCK_DELAY_5_4:
752 case CLOCK_DELAY_3_2:
753 break;
754 default:
755 debug("%s: write_cmd_to_write_data value %d invalid.\n",
756 dev->name, write_cmd_to_write_data);
757 return -EINVAL;
758 }
759
760 minimum_cke_pulse_width =
761 dev_read_u32_default(dev, "minimum_cke_pulse_width", 0);
762 if (minimum_cke_pulse_width > 4 || minimum_cke_pulse_width == 0) {
763 debug("%s: minimum_cke_pulse_width value %d invalid.\n",
764 dev->name, minimum_cke_pulse_width);
765 return -EINVAL;
766 }
767
768 four_activates_window =
769 dev_read_u32_default(dev, "four_activates_window", 0);
770 if (four_activates_window > 20 || four_activates_window == 0) {
771 debug("%s: four_activates_window value %d invalid.\n",
772 dev->name, four_activates_window);
773 return -EINVAL;
774 }
775
776 timing_cfg_2 = additive_latency << TIMING_CFG2_ADD_LAT_SHIFT |
777 mcas_to_preamble_override << TIMING_CFG2_CPO_SHIFT |
778 write_latency << TIMING_CFG2_WR_LAT_DELAY_SHIFT |
779 read_to_precharge << TIMING_CFG2_RD_TO_PRE_SHIFT |
780 write_cmd_to_write_data << TIMING_CFG2_WR_DATA_DELAY_SHIFT |
781 minimum_cke_pulse_width << TIMING_CFG2_CKE_PLS_SHIFT |
782 four_activates_window << TIMING_CFG2_FOUR_ACT_SHIFT;
783
784 out_be32(&im->ddr.timing_cfg_2, timing_cfg_2);
785
786 self_refresh = dev_read_u32_default(dev, "self_refresh", 0);
787 switch (self_refresh) {
788 case SREN_DISABLE:
789 case SREN_ENABLE:
790 break;
791 default:
792 debug("%s: self_refresh value %d invalid.\n",
793 dev->name, self_refresh);
794 return -EINVAL;
795 }
796
797 ecc = dev_read_u32_default(dev, "ecc", 0);
798 switch (ecc) {
799 case ECC_DISABLE:
800 case ECC_ENABLE:
801 break;
802 default:
803 debug("%s: ecc value %d invalid.\n", dev->name, ecc);
804 return -EINVAL;
805 }
806
807 registered_dram = dev_read_u32_default(dev, "registered_dram", 0);
808 switch (registered_dram) {
809 case RD_DISABLE:
810 case RD_ENABLE:
811 break;
812 default:
813 debug("%s: registered_dram value %d invalid.\n",
814 dev->name, registered_dram);
815 return -EINVAL;
816 }
817
818 sdram_type = dev_read_u32_default(dev, "sdram_type", 0);
819 switch (sdram_type) {
820 case TYPE_DDR1:
821 case TYPE_DDR2:
822 break;
823 default:
824 debug("%s: sdram_type value %d invalid.\n",
825 dev->name, sdram_type);
826 return -EINVAL;
827 }
828
829 dynamic_power_management =
830 dev_read_u32_default(dev, "dynamic_power_management", 0);
831 switch (dynamic_power_management) {
832 case DYN_PWR_DISABLE:
833 case DYN_PWR_ENABLE:
834 break;
835 default:
836 debug("%s: dynamic_power_management value %d invalid.\n",
837 dev->name, dynamic_power_management);
838 return -EINVAL;
839 }
840
841 databus_width = dev_read_u32_default(dev, "databus_width", 0);
842 switch (databus_width) {
843 case DATA_BUS_WIDTH_16:
844 case DATA_BUS_WIDTH_32:
845 break;
846 default:
847 debug("%s: databus_width value %d invalid.\n",
848 dev->name, databus_width);
849 return -EINVAL;
850 }
851
852 nc_auto_precharge = dev_read_u32_default(dev, "nc_auto_precharge", 0);
853 switch (nc_auto_precharge) {
854 case NCAP_DISABLE:
855 case NCAP_ENABLE:
856 break;
857 default:
858 debug("%s: nc_auto_precharge value %d invalid.\n",
859 dev->name, nc_auto_precharge);
860 return -EINVAL;
861 }
862
863 timing_2t = dev_read_u32_default(dev, "timing_2t", 0);
864 switch (timing_2t) {
865 case TIMING_1T:
866 case TIMING_2T:
867 break;
868 default:
869 debug("%s: timing_2t value %d invalid.\n",
870 dev->name, timing_2t);
871 return -EINVAL;
872 }
873
874 bank_interleaving_ctrl =
875 dev_read_u32_default(dev, "bank_interleaving_ctrl", 0);
876 switch (bank_interleaving_ctrl) {
877 case INTERLEAVE_NONE:
878 case INTERLEAVE_1_AND_2:
879 break;
880 default:
881 debug("%s: bank_interleaving_ctrl value %d invalid.\n",
882 dev->name, bank_interleaving_ctrl);
883 return -EINVAL;
884 }
885
886 precharge_bit_8 = dev_read_u32_default(dev, "precharge_bit_8", 0);
887 switch (precharge_bit_8) {
888 case PRECHARGE_MA_10:
889 case PRECHARGE_MA_8:
890 break;
891 default:
892 debug("%s: precharge_bit_8 value %d invalid.\n",
893 dev->name, precharge_bit_8);
894 return -EINVAL;
895 }
896
897 half_strength = dev_read_u32_default(dev, "half_strength", 0);
898 switch (half_strength) {
899 case STRENGTH_FULL:
900 case STRENGTH_HALF:
901 break;
902 default:
903 debug("%s: half_strength value %d invalid.\n",
904 dev->name, half_strength);
905 return -EINVAL;
906 }
907
908 bypass_initialization =
909 dev_read_u32_default(dev, "bypass_initialization", 0);
910 switch (bypass_initialization) {
911 case INITIALIZATION_DONT_BYPASS:
912 case INITIALIZATION_BYPASS:
913 break;
914 default:
915 debug("%s: bypass_initialization value %d invalid.\n",
916 dev->name, bypass_initialization);
917 return -EINVAL;
918 }
919
920 sdram_cfg = self_refresh << SDRAM_CFG_SREN_SHIFT |
921 ecc << SDRAM_CFG_ECC_EN_SHIFT |
922 registered_dram << SDRAM_CFG_RD_EN_SHIFT |
923 sdram_type << SDRAM_CFG_SDRAM_TYPE_SHIFT |
924 dynamic_power_management << SDRAM_CFG_DYN_PWR_SHIFT |
925 databus_width << SDRAM_CFG_DBW_SHIFT |
926 nc_auto_precharge << SDRAM_CFG_NCAP_SHIFT |
927 timing_2t << SDRAM_CFG_2T_EN_SHIFT |
928 bank_interleaving_ctrl << SDRAM_CFG_BA_INTLV_CTL_SHIFT |
929 precharge_bit_8 << SDRAM_CFG_PCHB8_SHIFT |
930 half_strength << SDRAM_CFG_HSE_SHIFT |
931 bypass_initialization << SDRAM_CFG_BI_SHIFT;
932
933 out_be32(&im->ddr.sdram_cfg, sdram_cfg);
934
935 force_self_refresh = dev_read_u32_default(dev, "force_self_refresh", 0);
936 switch (force_self_refresh) {
937 case MODE_NORMAL:
938 case MODE_REFRESH:
939 break;
940 default:
941 debug("%s: force_self_refresh value %d invalid.\n",
942 dev->name, force_self_refresh);
943 return -EINVAL;
944 }
945
946 dll_reset = dev_read_u32_default(dev, "dll_reset", 0);
947 switch (dll_reset) {
948 case DLL_RESET_ENABLE:
949 case DLL_RESET_DISABLE:
950 break;
951 default:
952 debug("%s: dll_reset value %d invalid.\n",
953 dev->name, dll_reset);
954 return -EINVAL;
955 }
956
957 dqs_config = dev_read_u32_default(dev, "dqs_config", 0);
958 switch (dqs_config) {
959 case DQS_TRUE:
960 break;
961 default:
962 debug("%s: dqs_config value %d invalid.\n",
963 dev->name, dqs_config);
964 return -EINVAL;
965 }
966
967 odt_config = dev_read_u32_default(dev, "odt_config", 0);
968 switch (odt_config) {
969 case ODT_ASSERT_NEVER:
970 case ODT_ASSERT_WRITES:
971 case ODT_ASSERT_READS:
972 case ODT_ASSERT_ALWAYS:
973 break;
974 default:
975 debug("%s: odt_config value %d invalid.\n",
976 dev->name, odt_config);
977 return -EINVAL;
978 }
979
980 posted_refreshes = dev_read_u32_default(dev, "posted_refreshes", 0);
981 if (posted_refreshes > 8 || posted_refreshes == 0) {
982 debug("%s: posted_refreshes value %d invalid.\n",
983 dev->name, posted_refreshes);
984 return -EINVAL;
985 }
986
987 sdram_cfg2 = force_self_refresh << SDRAM_CFG2_FRC_SR_SHIFT |
988 dll_reset << SDRAM_CFG2_DLL_RST_DIS |
989 dqs_config << SDRAM_CFG2_DQS_CFG |
990 odt_config << SDRAM_CFG2_ODT_CFG |
991 posted_refreshes << SDRAM_CFG2_NUM_PR;
992
993 out_be32(&im->ddr.sdram_cfg2, sdram_cfg2);
994
995 sdmode = dev_read_u32_default(dev, "sdmode", 0);
996 if (sdmode > 0xFFFF) {
997 debug("%s: sdmode value %d invalid.\n",
998 dev->name, sdmode);
999 return -EINVAL;
1000 }
1001
1002 esdmode = dev_read_u32_default(dev, "esdmode", 0);
1003 if (esdmode > 0xFFFF) {
1004 debug("%s: esdmode value %d invalid.\n", dev->name, esdmode);
1005 return -EINVAL;
1006 }
1007
1008 sdram_mode = sdmode << SDRAM_MODE_SD_SHIFT |
1009 esdmode << SDRAM_MODE_ESD_SHIFT;
1010
1011 out_be32(&im->ddr.sdram_mode, sdram_mode);
1012
1013 esdmode2 = dev_read_u32_default(dev, "esdmode2", 0);
1014 if (esdmode2 > 0xFFFF) {
1015 debug("%s: esdmode2 value %d invalid.\n", dev->name, esdmode2);
1016 return -EINVAL;
1017 }
1018
1019 esdmode3 = dev_read_u32_default(dev, "esdmode3", 0);
1020 if (esdmode3 > 0xFFFF) {
1021 debug("%s: esdmode3 value %d invalid.\n", dev->name, esdmode3);
1022 return -EINVAL;
1023 }
1024
1025 sdram_mode2 = esdmode2 << SDRAM_MODE2_ESD2_SHIFT |
1026 esdmode3 << SDRAM_MODE2_ESD3_SHIFT;
1027
1028 out_be32(&im->ddr.sdram_mode2, sdram_mode2);
1029
1030 refresh_interval = dev_read_u32_default(dev, "refresh_interval", 0);
1031 if (refresh_interval > 0xFFFF) {
1032 debug("%s: refresh_interval value %d invalid.\n",
1033 dev->name, refresh_interval);
1034 return -EINVAL;
1035 }
1036
1037 precharge_interval = dev_read_u32_default(dev, "precharge_interval", 0);
1038 if (precharge_interval > 0x3FFF) {
1039 debug("%s: precharge_interval value %d invalid.\n",
1040 dev->name, precharge_interval);
1041 return -EINVAL;
1042 }
1043
1044 sdram_interval = refresh_interval << SDRAM_INTERVAL_REFINT_SHIFT |
1045 precharge_interval << SDRAM_INTERVAL_BSTOPRE_SHIFT;
1046
1047 out_be32(&im->ddr.sdram_interval, sdram_interval);
1048 sync();
1049
1050 /* Enable DDR controller */
1051 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
1052 sync();
1053
1054 dev_for_each_subnode(subnode, dev) {
1055 u32 val[3];
1056 u32 addr, size;
1057
1058 /* CS, map address, size -> three values */
1059 ofnode_read_u32_array(subnode, "reg", val, 3);
1060
1061 addr = val[1];
1062 size = val[2];
1063
1064 priv->total_size += get_ram_size((long int *)addr, size);
1065 };
1066
1067 gd->ram_size = priv->total_size;
1068
1069 return 0;
1070}
1071
1072static int mpc83xx_sdram_get_info(struct udevice *dev, struct ram_info *info)
1073{
1074 /* TODO(mario.six@gdsys.cc): Implement */
1075 return 0;
1076}
1077
1078static struct ram_ops mpc83xx_sdram_ops = {
1079 .get_info = mpc83xx_sdram_get_info,
1080};
1081
1082static const struct udevice_id mpc83xx_sdram_ids[] = {
1083 { .compatible = "fsl,mpc83xx-mem-controller" },
1084 { /* sentinel */ }
1085};
1086
1087U_BOOT_DRIVER(mpc83xx_sdram) = {
1088 .name = "mpc83xx_sdram",
1089 .id = UCLASS_RAM,
1090 .of_match = mpc83xx_sdram_ids,
1091 .ops = &mpc83xx_sdram_ops,
d1998a9f 1092 .of_to_plat = mpc83xx_sdram_of_to_plat,
e4061556 1093 .probe = mpc83xx_sdram_probe,
41575d8e 1094 .priv_auto = sizeof(struct mpc83xx_sdram_priv),
e4061556 1095};
"Das U-Boot" Source Tree