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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
fe60f06d SW |
2 | /* |
3 | * Copyright (c) 2016, NVIDIA CORPORATION. | |
fe60f06d SW |
4 | */ |
5 | ||
d678a59d | 6 | #include <common.h> |
fe60f06d | 7 | #include <dm.h> |
f7ae49fc | 8 | #include <log.h> |
336d4615 | 9 | #include <malloc.h> |
fe60f06d SW |
10 | #include <reset-uclass.h> |
11 | #include <asm/arch/clock.h> | |
12 | #include <asm/arch-tegra/clk_rst.h> | |
13 | ||
14 | static int tegra_car_reset_request(struct reset_ctl *reset_ctl) | |
15 | { | |
16 | debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, | |
17 | reset_ctl->dev, reset_ctl->id); | |
18 | ||
19 | /* PERIPH_ID_COUNT varies per SoC */ | |
20 | if (reset_ctl->id >= PERIPH_ID_COUNT) | |
21 | return -EINVAL; | |
22 | ||
23 | return 0; | |
24 | } | |
25 | ||
fe60f06d SW |
26 | static int tegra_car_reset_assert(struct reset_ctl *reset_ctl) |
27 | { | |
28 | debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, | |
29 | reset_ctl->dev, reset_ctl->id); | |
30 | ||
31 | reset_set_enable(reset_ctl->id, 1); | |
32 | ||
33 | return 0; | |
34 | } | |
35 | ||
36 | static int tegra_car_reset_deassert(struct reset_ctl *reset_ctl) | |
37 | { | |
38 | debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, | |
39 | reset_ctl->dev, reset_ctl->id); | |
40 | ||
41 | reset_set_enable(reset_ctl->id, 0); | |
42 | ||
43 | return 0; | |
44 | } | |
45 | ||
46 | struct reset_ops tegra_car_reset_ops = { | |
47 | .request = tegra_car_reset_request, | |
fe60f06d SW |
48 | .rst_assert = tegra_car_reset_assert, |
49 | .rst_deassert = tegra_car_reset_deassert, | |
50 | }; | |
51 | ||
fe60f06d SW |
52 | U_BOOT_DRIVER(tegra_car_reset) = { |
53 | .name = "tegra_car_reset", | |
54 | .id = UCLASS_RESET, | |
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55 | .ops = &tegra_car_reset_ops, |
56 | }; |