[people/ms/u-boot.git] / drivers / rtc / ds1337.c

/*
 * (C) Copyright 2001-2008
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Keith Outwater, keith_outwater@mvis.com`
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
 * DS1337 Real Time Clock (RTC).
 */

#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>

#if defined(CONFIG_CMD_DATE)

/*---------------------------------------------------------------------*/
#undef DEBUG_RTC

#ifdef DEBUG_RTC
#define DEBUGR(fmt,args...) printf(fmt ,##args)
#else
#define DEBUGR(fmt,args...)
#endif
/*---------------------------------------------------------------------*/

/*
 * RTC register addresses
 */
#define RTC_SEC_REG_ADDR	0x0
#define RTC_MIN_REG_ADDR	0x1
#define RTC_HR_REG_ADDR		0x2
#define RTC_DAY_REG_ADDR	0x3
#define RTC_DATE_REG_ADDR	0x4
#define RTC_MON_REG_ADDR	0x5
#define RTC_YR_REG_ADDR		0x6
#define RTC_CTL_REG_ADDR	0x0e
#define RTC_STAT_REG_ADDR	0x0f
#define RTC_TC_REG_ADDR		0x10

/*
 * RTC control register bits
 */
#define RTC_CTL_BIT_A1IE	0x1	/* Alarm 1 interrupt enable	*/
#define RTC_CTL_BIT_A2IE	0x2	/* Alarm 2 interrupt enable	*/
#define RTC_CTL_BIT_INTCN	0x4	/* Interrupt control		*/
#define RTC_CTL_BIT_RS1		0x8	/* Rate select 1		*/
#define RTC_CTL_BIT_RS2		0x10	/* Rate select 2		*/
#define RTC_CTL_BIT_DOSC	0x80	/* Disable Oscillator		*/

/*
 * RTC status register bits
 */
#define RTC_STAT_BIT_A1F	0x1	/* Alarm 1 flag			*/
#define RTC_STAT_BIT_A2F	0x2	/* Alarm 2 flag			*/
#define RTC_STAT_BIT_OSF	0x80	/* Oscillator stop flag		*/


static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);

/*
 * Get the current time from the RTC
 */
int rtc_get (struct rtc_time *tmp)
{
	int rel = 0;
	uchar sec, min, hour, mday, wday, mon_cent, year, control, status;

	control = rtc_read (RTC_CTL_REG_ADDR);
	status = rtc_read (RTC_STAT_REG_ADDR);
	sec = rtc_read (RTC_SEC_REG_ADDR);
	min = rtc_read (RTC_MIN_REG_ADDR);
	hour = rtc_read (RTC_HR_REG_ADDR);
	wday = rtc_read (RTC_DAY_REG_ADDR);
	mday = rtc_read (RTC_DATE_REG_ADDR);
	mon_cent = rtc_read (RTC_MON_REG_ADDR);
	year = rtc_read (RTC_YR_REG_ADDR);

	DEBUGR ("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
		"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
		year, mon_cent, mday, wday, hour, min, sec, control, status);

	if (status & RTC_STAT_BIT_OSF) {
		printf ("### Warning: RTC oscillator has stopped\n");
		/* clear the OSF flag */
		rtc_write (RTC_STAT_REG_ADDR,
			   rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
		rel = -1;
	}

	tmp->tm_sec  = bcd2bin (sec & 0x7F);
	tmp->tm_min  = bcd2bin (min & 0x7F);
	tmp->tm_hour = bcd2bin (hour & 0x3F);
	tmp->tm_mday = bcd2bin (mday & 0x3F);
	tmp->tm_mon  = bcd2bin (mon_cent & 0x1F);
	tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
	tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
	tmp->tm_yday = 0;
	tmp->tm_isdst= 0;

	DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);

	return rel;
}


/*
 * Set the RTC
 */
int rtc_set (struct rtc_time *tmp)
{
	uchar century;

	DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
		tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
		tmp->tm_hour, tmp->tm_min, tmp->tm_sec);

	rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));

	century = (tmp->tm_year >= 2000) ? 0x80 : 0;
	rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);

	rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
	rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
	rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
	rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
	rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));

	return 0;
}


/*
 * Reset the RTC.  We also enable the oscillator output on the
 * SQW/INTB* pin and program it for 32,768 Hz output. Note that
 * according to the datasheet, turning on the square wave output
 * increases the current drain on the backup battery from about
 * 600 nA to 2uA. Define CONFIG_SYS_RTC_DS1337_NOOSC if you wish to turn
 * off the OSC output.
 */
#ifdef CONFIG_SYS_RTC_DS1337_NOOSC
 #define RTC_DS1337_RESET_VAL \
	(RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
#else
 #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
#endif
void rtc_reset (void)
{
	rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
#ifdef CONFIG_SYS_DS1339_TCR_VAL
	rtc_write (RTC_TC_REG_ADDR, CONFIG_SYS_DS1339_TCR_VAL);
#endif
}


/*
 * Helper functions
 */

static
uchar rtc_read (uchar reg)
{
	return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
}


static void rtc_write (uchar reg, uchar val)
{
	i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}

#endif
Commit	Line	Data
5d3207da	1	/*
5b5eb9ca	2	* (C) Copyright 2001-2008
5d3207da WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	* Keith Outwater, keith_outwater@mvis.com`
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/*
	26	* Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
	27	* DS1337 Real Time Clock (RTC).
	28	*/
	29
	30	#include <common.h>
	31	#include <command.h>
	32	#include <rtc.h>
	33	#include <i2c.h>
	34
871c18dd	35	#if defined(CONFIG_CMD_DATE)
5d3207da WD	36
	37	/---------------------------------------------------------------------/
	38	#undef DEBUG_RTC
	39
	40	#ifdef DEBUG_RTC
	41	#define DEBUGR(fmt,args...) printf(fmt ,##args)
	42	#else
	43	#define DEBUGR(fmt,args...)
	44	#endif
	45	/---------------------------------------------------------------------/
	46
	47	/*
	48	* RTC register addresses
	49	*/
	50	#define RTC_SEC_REG_ADDR 0x0
	51	#define RTC_MIN_REG_ADDR 0x1
	52	#define RTC_HR_REG_ADDR 0x2
	53	#define RTC_DAY_REG_ADDR 0x3
	54	#define RTC_DATE_REG_ADDR 0x4
	55	#define RTC_MON_REG_ADDR 0x5
	56	#define RTC_YR_REG_ADDR 0x6
	57	#define RTC_CTL_REG_ADDR 0x0e
	58	#define RTC_STAT_REG_ADDR 0x0f
b0078c87	59	#define RTC_TC_REG_ADDR 0x10
5d3207da WD	60
	61	/*
	62	* RTC control register bits
	63	*/
5b5eb9ca WD	64	#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
	65	#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
	66	#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
	67	#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
	68	#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
	69	#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
5d3207da WD	70
	71	/*
	72	* RTC status register bits
	73	*/
5b5eb9ca WD	74	#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
	75	#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
	76	#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
5d3207da WD	77
	78
	79	static uchar rtc_read (uchar reg);
	80	static void rtc_write (uchar reg, uchar val);
5d3207da WD	81
	82	/*
	83	* Get the current time from the RTC
	84	*/
b73a19e1	85	int rtc_get (struct rtc_time *tmp)
5d3207da	86	{
b73a19e1	87	int rel = 0;
5d3207da WD	88	uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
	89
	90	control = rtc_read (RTC_CTL_REG_ADDR);
	91	status = rtc_read (RTC_STAT_REG_ADDR);
	92	sec = rtc_read (RTC_SEC_REG_ADDR);
	93	min = rtc_read (RTC_MIN_REG_ADDR);
	94	hour = rtc_read (RTC_HR_REG_ADDR);
	95	wday = rtc_read (RTC_DAY_REG_ADDR);
	96	mday = rtc_read (RTC_DATE_REG_ADDR);
	97	mon_cent = rtc_read (RTC_MON_REG_ADDR);
	98	year = rtc_read (RTC_YR_REG_ADDR);
	99
	100	DEBUGR ("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
	101	"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
	102	year, mon_cent, mday, wday, hour, min, sec, control, status);
	103
	104	if (status & RTC_STAT_BIT_OSF) {
	105	printf ("### Warning: RTC oscillator has stopped\n");
	106	/* clear the OSF flag */
	107	rtc_write (RTC_STAT_REG_ADDR,
	108	rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
b73a19e1	109	rel = -1;
5d3207da WD	110	}
	111
	112	tmp->tm_sec = bcd2bin (sec & 0x7F);
	113	tmp->tm_min = bcd2bin (min & 0x7F);
	114	tmp->tm_hour = bcd2bin (hour & 0x3F);
	115	tmp->tm_mday = bcd2bin (mday & 0x3F);
	116	tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
	117	tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
	118	tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
	119	tmp->tm_yday = 0;
	120	tmp->tm_isdst= 0;
	121
	122	DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
	123	tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	124	tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
b73a19e1 YT	125
b73a19e1 YT	126	return rel;
5d3207da WD	127	}
	128
	129
	130	/*
	131	* Set the RTC
	132	*/
d1e23194	133	int rtc_set (struct rtc_time *tmp)
5d3207da WD	134	{
	135	uchar century;
	136
	137	DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
	138	tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
	139	tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
	140
	141	rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
	142
	143	century = (tmp->tm_year >= 2000) ? 0x80 : 0;
	144	rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) \| century);
	145
	146	rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
	147	rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
	148	rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
	149	rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
	150	rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
d1e23194 JCPV	151
d1e23194 JCPV	152	return 0;
5d3207da WD	153	}
	154
	155
	156	/*
	157	* Reset the RTC. We also enable the oscillator output on the
	158	* SQW/INTB* pin and program it for 32,768 Hz output. Note that
	159	* according to the datasheet, turning on the square wave output
	160	* increases the current drain on the backup battery from about
6d0f6bcf	161	* 600 nA to 2uA. Define CONFIG_SYS_RTC_DS1337_NOOSC if you wish to turn
da8808df	162	* off the OSC output.
5d3207da	163	*/
6d0f6bcf	164	#ifdef CONFIG_SYS_RTC_DS1337_NOOSC
da8808df	165	#define RTC_DS1337_RESET_VAL \
5b5eb9ca	166	(RTC_CTL_BIT_INTCN \| RTC_CTL_BIT_RS1 \| RTC_CTL_BIT_RS2)
da8808df JT	167	#else
	168	#define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 \| RTC_CTL_BIT_RS2)
	169	#endif
5d3207da WD	170	void rtc_reset (void)
5d3207da WD	171	{
da8808df	172	rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
b0078c87 WP	173	#ifdef CONFIG_SYS_DS1339_TCR_VAL
	174	rtc_write (RTC_TC_REG_ADDR, CONFIG_SYS_DS1339_TCR_VAL);
	175	#endif
5d3207da WD	176	}
	177
	178
	179	/*
	180	* Helper functions
	181	*/
	182
	183	static
	184	uchar rtc_read (uchar reg)
	185	{
6d0f6bcf	186	return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
5d3207da WD	187	}
	188
	189
	190	static void rtc_write (uchar reg, uchar val)
	191	{
6d0f6bcf	192	i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
5d3207da WD	193	}
5d3207da WD	194
068b60a0	195	#endif