[people/ms/u-boot.git] / drivers / serial / atmel_usart.c

/*
 * Copyright (C) 2004-2006 Atmel Corporation
 *
 * Modified to support C structur SoC access by
 * Andreas Bießmann <biessmann@corscience.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <common.h>
#include <watchdog.h>

#include <asm/io.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>

#include "atmel_usart.h"

DECLARE_GLOBAL_DATA_PTR;

void serial_setbrg(void)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
	unsigned long divisor;
	unsigned long usart_hz;

	/*
	 *              Master Clock
	 * Baud Rate = --------------
	 *                16 * CD
	 */
	usart_hz = get_usart_clk_rate(CONFIG_USART_ID);
	divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate;
	writel(USART3_BF(CD, divisor), &usart->brgr);
}

int serial_init(void)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;

	writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);

	serial_setbrg();

	writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
	writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
			   | USART3_BF(USCLKS, USART3_USCLKS_MCK)
			   | USART3_BF(CHRL, USART3_CHRL_8)
			   | USART3_BF(PAR, USART3_PAR_NONE)
			   | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
			   &usart->mr);

	return 0;
}

void serial_putc(char c)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;

	if (c == '\n')
		serial_putc('\r');

	while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
	writel(c, &usart->thr);
}

void serial_puts(const char *s)
{
	while (*s)
		serial_putc(*s++);
}

int serial_getc(void)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;

	while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
		 WATCHDOG_RESET();
	return readl(&usart->rhr);
}

int serial_tstc(void)
{
	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
	return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
}
Commit	Line	Data
f93ae788 WD	1	/*
	2	* Copyright (C) 2004-2006 Atmel Corporation
	3	*
125637c5 AB	4	* Modified to support C structur SoC access by
	5	* Andreas Bießmann <biessmann@corscience.de>
	6	*
f93ae788 WD	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21	#include <common.h>
843a2654	22	#include <watchdog.h>
f93ae788	23
f93ae788	24	#include <asm/io.h>
df548d3c	25	#include <asm/arch/clk.h>
329f0f52	26	#include <asm/arch/hardware.h>
f93ae788 WD	27
	28	#include "atmel_usart.h"
	29
	30	DECLARE_GLOBAL_DATA_PTR;
	31
	32	void serial_setbrg(void)
	33	{
329f0f52	34	atmel_usart3_t usart = (atmel_usart3_t )CONFIG_USART_BASE;
f93ae788 WD	35	unsigned long divisor;
	36	unsigned long usart_hz;
	37
	38	/*
	39	* Master Clock
	40	* Baud Rate = --------------
	41	* 16 * CD
	42	*/
329f0f52	43	usart_hz = get_usart_clk_rate(CONFIG_USART_ID);
f93ae788	44	divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate;
125637c5	45	writel(USART3_BF(CD, divisor), &usart->brgr);
f93ae788 WD	46	}
	47
	48	int serial_init(void)
	49	{
329f0f52	50	atmel_usart3_t usart = (atmel_usart3_t )CONFIG_USART_BASE;
125637c5 AB	51
125637c5 AB	52	writel(USART3_BIT(RSTRX) \| USART3_BIT(RSTTX), &usart->cr);
f93ae788 WD	53
	54	serial_setbrg();
	55
125637c5 AB	56	writel(USART3_BIT(RXEN) \| USART3_BIT(TXEN), &usart->cr);
125637c5 AB	57	writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
df548d3c HS	58	\| USART3_BF(USCLKS, USART3_USCLKS_MCK)
	59	\| USART3_BF(CHRL, USART3_CHRL_8)
	60	\| USART3_BF(PAR, USART3_PAR_NONE)
125637c5 AB	61	\| USART3_BF(NBSTOP, USART3_NBSTOP_1)),
125637c5 AB	62	&usart->mr);
f93ae788 WD	63
	64	return 0;
	65	}
	66
	67	void serial_putc(char c)
	68	{
329f0f52	69	atmel_usart3_t usart = (atmel_usart3_t )CONFIG_USART_BASE;
125637c5	70
f93ae788 WD	71	if (c == '\n')
	72	serial_putc('\r');
	73
125637c5 AB	74	while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
125637c5 AB	75	writel(c, &usart->thr);
f93ae788 WD	76	}
	77
	78	void serial_puts(const char *s)
	79	{
	80	while (*s)
	81	serial_putc(*s++);
	82	}
	83
	84	int serial_getc(void)
	85	{
329f0f52	86	atmel_usart3_t usart = (atmel_usart3_t )CONFIG_USART_BASE;
125637c5 AB	87
125637c5 AB	88	while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
843a2654	89	WATCHDOG_RESET();
125637c5	90	return readl(&usart->rhr);
f93ae788 WD	91	}
	92
	93	int serial_tstc(void)
	94	{
329f0f52	95	atmel_usart3_t usart = (atmel_usart3_t )CONFIG_USART_BASE;
125637c5	96	return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
f93ae788	97	}